1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "llvm/ADT/OwningPtr.h"
20 #include "llvm/Analysis/Passes.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Verifier.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSubtargetInfo.h"
32 #include "llvm/PassManager.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/FormattedStream.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetLowering.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetSubtargetInfo.h"
45 #include "llvm/Transforms/Scalar.h"
50 void initializeNVVMReflectPass(PassRegistry&);
51 void initializeGenericToNVVMPass(PassRegistry&);
52 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
55 extern "C" void LLVMInitializeNVPTXTarget() {
56 // Register the target.
57 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
58 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
60 // FIXME: This pass is really intended to be invoked during IR optimization,
61 // but it's very NVPTX-specific.
62 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
63 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
64 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
67 static std::string computeDataLayout(const NVPTXSubtarget &ST) {
68 std::string Ret = "e";
73 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
78 NVPTXTargetMachine::NVPTXTargetMachine(
79 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
80 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
81 CodeGenOpt::Level OL, bool is64bit)
82 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
83 Subtarget(TT, CPU, FS, is64bit), DL(computeDataLayout(Subtarget)),
84 InstrInfo(*this), TLInfo(*this), TSInfo(*this),
86 *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
90 void NVPTXTargetMachine32::anchor() {}
92 NVPTXTargetMachine32::NVPTXTargetMachine32(
93 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
94 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
96 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
98 void NVPTXTargetMachine64::anchor() {}
100 NVPTXTargetMachine64::NVPTXTargetMachine64(
101 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
102 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
103 CodeGenOpt::Level OL)
104 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
107 class NVPTXPassConfig : public TargetPassConfig {
109 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
110 : TargetPassConfig(TM, PM) {}
112 NVPTXTargetMachine &getNVPTXTargetMachine() const {
113 return getTM<NVPTXTargetMachine>();
116 virtual void addIRPasses();
117 virtual bool addInstSelector();
118 virtual bool addPreRegAlloc();
119 virtual bool addPostRegAlloc();
121 virtual FunctionPass *createTargetRegisterAllocator(bool) override;
122 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
123 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
125 } // end anonymous namespace
127 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
128 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
132 void NVPTXPassConfig::addIRPasses() {
133 // The following passes are known to not play well with virtual regs hanging
134 // around after register allocation (which in our case, is *all* registers).
135 // We explicitly disable them here. We do, however, need some functionality
136 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
137 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
138 disablePass(&PrologEpilogCodeInserterID);
139 disablePass(&MachineCopyPropagationID);
140 disablePass(&BranchFolderPassID);
141 disablePass(&TailDuplicateID);
143 TargetPassConfig::addIRPasses();
144 addPass(createNVPTXAssignValidGlobalNamesPass());
145 addPass(createGenericToNVVMPass());
148 bool NVPTXPassConfig::addInstSelector() {
149 addPass(createLowerAggrCopies());
150 addPass(createAllocaHoisting());
151 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
155 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
156 bool NVPTXPassConfig::addPostRegAlloc() {
157 addPass(createNVPTXPrologEpilogPass());
161 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
162 return 0; // No reg alloc
165 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
166 assert(!RegAllocPass && "NVPTX uses no regalloc!");
167 addPass(&PHIEliminationID);
168 addPass(&TwoAddressInstructionPassID);
171 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
172 assert(!RegAllocPass && "NVPTX uses no regalloc!");
174 addPass(&ProcessImplicitDefsID);
175 addPass(&LiveVariablesID);
176 addPass(&MachineLoopInfoID);
177 addPass(&PHIEliminationID);
179 addPass(&TwoAddressInstructionPassID);
180 addPass(&RegisterCoalescerID);
182 // PreRA instruction scheduling.
183 if (addPass(&MachineSchedulerID))
184 printAndVerify("After Machine Scheduling");
187 addPass(&StackSlotColoringID);
189 // FIXME: Needs physical registers
190 //addPass(&PostRAMachineLICMID);
192 printAndVerify("After StackSlotColoring");