1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "NVPTXTargetTransformInfo.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSubtargetInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
53 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
54 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
55 void initializeNVPTXLowerStructArgsPass(PassRegistry &);
58 extern "C" void LLVMInitializeNVPTXTarget() {
59 // Register the target.
60 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
61 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
63 // FIXME: This pass is really intended to be invoked during IR optimization,
64 // but it's very NVPTX-specific.
65 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
66 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
67 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
68 initializeNVPTXFavorNonGenericAddrSpacesPass(
69 *PassRegistry::getPassRegistry());
70 initializeNVPTXLowerStructArgsPass(*PassRegistry::getPassRegistry());
73 static std::string computeDataLayout(bool is64Bit) {
74 std::string Ret = "e";
79 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
84 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
85 StringRef CPU, StringRef FS,
86 const TargetOptions &Options,
87 Reloc::Model RM, CodeModel::Model CM,
88 CodeGenOpt::Level OL, bool is64bit)
89 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
90 TLOF(make_unique<NVPTXTargetObjectFile>()),
91 DL(computeDataLayout(is64bit)),
92 Subtarget(TT, CPU, FS, *this, is64bit) {
96 NVPTXTargetMachine::~NVPTXTargetMachine() {}
98 void NVPTXTargetMachine32::anchor() {}
100 NVPTXTargetMachine32::NVPTXTargetMachine32(
101 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
102 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
103 CodeGenOpt::Level OL)
104 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
106 void NVPTXTargetMachine64::anchor() {}
108 NVPTXTargetMachine64::NVPTXTargetMachine64(
109 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
110 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
111 CodeGenOpt::Level OL)
112 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
115 class NVPTXPassConfig : public TargetPassConfig {
117 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
118 : TargetPassConfig(TM, PM) {}
120 NVPTXTargetMachine &getNVPTXTargetMachine() const {
121 return getTM<NVPTXTargetMachine>();
124 void addIRPasses() override;
125 bool addInstSelector() override;
126 void addPostRegAlloc() override;
127 void addMachineSSAOptimization() override;
129 FunctionPass *createTargetRegisterAllocator(bool) override;
130 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
131 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
133 } // end anonymous namespace
135 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
136 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
140 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
141 return TargetIRAnalysis(
142 [this](Function &) { return TargetTransformInfo(NVPTXTTIImpl(this)); });
145 void NVPTXPassConfig::addIRPasses() {
146 // The following passes are known to not play well with virtual regs hanging
147 // around after register allocation (which in our case, is *all* registers).
148 // We explicitly disable them here. We do, however, need some functionality
149 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
150 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
151 disablePass(&PrologEpilogCodeInserterID);
152 disablePass(&MachineCopyPropagationID);
153 disablePass(&BranchFolderPassID);
154 disablePass(&TailDuplicateID);
156 addPass(createNVPTXImageOptimizerPass());
157 TargetPassConfig::addIRPasses();
158 addPass(createNVPTXAssignValidGlobalNamesPass());
159 addPass(createGenericToNVVMPass());
160 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
161 addPass(createStraightLineStrengthReducePass());
162 addPass(createSeparateConstOffsetFromGEPPass());
163 // The SeparateConstOffsetFromGEP pass creates variadic bases that can be used
164 // by multiple GEPs. Run GVN or EarlyCSE to really reuse them. GVN generates
165 // significantly better code than EarlyCSE for some of our benchmarks.
166 if (getOptLevel() == CodeGenOpt::Aggressive)
167 addPass(createGVNPass());
169 addPass(createEarlyCSEPass());
170 // Both FavorNonGenericAddrSpaces and SeparateConstOffsetFromGEP may leave
171 // some dead code. We could remove dead code in an ad-hoc manner, but that
172 // requires manual work and might be error-prone.
174 // The FavorNonGenericAddrSpaces pass shortcuts unnecessary addrspacecasts,
175 // and leave them unused.
177 // SeparateConstOffsetFromGEP rebuilds a new index from the old index, and the
178 // old index and some of its intermediate results may become unused.
179 addPass(createDeadCodeEliminationPass());
182 bool NVPTXPassConfig::addInstSelector() {
183 const NVPTXSubtarget &ST =
184 getTM<NVPTXTargetMachine>().getSubtarget<NVPTXSubtarget>();
186 addPass(createLowerAggrCopies());
187 addPass(createAllocaHoisting());
188 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
190 if (!ST.hasImageHandles())
191 addPass(createNVPTXReplaceImageHandlesPass());
196 void NVPTXPassConfig::addPostRegAlloc() {
197 addPass(createNVPTXPrologEpilogPass(), false);
200 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
201 return nullptr; // No reg alloc
204 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
205 assert(!RegAllocPass && "NVPTX uses no regalloc!");
206 addPass(&PHIEliminationID);
207 addPass(&TwoAddressInstructionPassID);
210 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
211 assert(!RegAllocPass && "NVPTX uses no regalloc!");
213 addPass(&ProcessImplicitDefsID);
214 addPass(&LiveVariablesID);
215 addPass(&MachineLoopInfoID);
216 addPass(&PHIEliminationID);
218 addPass(&TwoAddressInstructionPassID);
219 addPass(&RegisterCoalescerID);
221 // PreRA instruction scheduling.
222 if (addPass(&MachineSchedulerID))
223 printAndVerify("After Machine Scheduling");
226 addPass(&StackSlotColoringID);
228 // FIXME: Needs physical registers
229 //addPass(&PostRAMachineLICMID);
231 printAndVerify("After StackSlotColoring");
234 void NVPTXPassConfig::addMachineSSAOptimization() {
235 // Pre-ra tail duplication.
236 if (addPass(&EarlyTailDuplicateID))
237 printAndVerify("After Pre-RegAlloc TailDuplicate");
239 // Optimize PHIs before DCE: removing dead PHI cycles may make more
240 // instructions dead.
241 addPass(&OptimizePHIsID);
243 // This pass merges large allocas. StackSlotColoring is a different pass
244 // which merges spill slots.
245 addPass(&StackColoringID);
247 // If the target requests it, assign local variables to stack slots relative
248 // to one another and simplify frame index references where possible.
249 addPass(&LocalStackSlotAllocationID);
251 // With optimization, dead code should already be eliminated. However
252 // there is one known exception: lowered code for arguments that are only
253 // used by tail calls, where the tail calls reuse the incoming stack
254 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
255 addPass(&DeadMachineInstructionElimID);
256 printAndVerify("After codegen DCE pass");
258 // Allow targets to insert passes that improve instruction level parallelism,
259 // like if-conversion. Such passes will typically need dominator trees and
260 // loop info, just like LICM and CSE below.
262 printAndVerify("After ILP optimizations");
264 addPass(&MachineLICMID);
265 addPass(&MachineCSEID);
267 addPass(&MachineSinkingID);
268 printAndVerify("After Machine LICM, CSE and Sinking passes");
270 addPass(&PeepholeOptimizerID);
271 printAndVerify("After codegen peephole optimization pass");