1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXSplitBBatBar.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/Analysis/Verifier.h"
23 #include "llvm/Assembly/PrintModulePass.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/PassManager.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
55 extern "C" void LLVMInitializeNVPTXTarget() {
56 // Register the target.
57 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
58 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
60 RegisterMCAsmInfo<NVPTXMCAsmInfo> A(TheNVPTXTarget32);
61 RegisterMCAsmInfo<NVPTXMCAsmInfo> B(TheNVPTXTarget64);
63 // FIXME: This pass is really intended to be invoked during IR optimization,
64 // but it's very NVPTX-specific.
65 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
66 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
69 NVPTXTargetMachine::NVPTXTargetMachine(
70 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
71 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
72 CodeGenOpt::Level OL, bool is64bit)
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
74 Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()),
75 InstrInfo(*this), TLInfo(*this), TSInfo(*this),
77 *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
81 void NVPTXTargetMachine32::anchor() {}
83 NVPTXTargetMachine32::NVPTXTargetMachine32(
84 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
85 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
89 void NVPTXTargetMachine64::anchor() {}
91 NVPTXTargetMachine64::NVPTXTargetMachine64(
92 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
93 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
95 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
98 class NVPTXPassConfig : public TargetPassConfig {
100 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
101 : TargetPassConfig(TM, PM) {}
103 NVPTXTargetMachine &getNVPTXTargetMachine() const {
104 return getTM<NVPTXTargetMachine>();
107 virtual void addIRPasses();
108 virtual bool addInstSelector();
109 virtual bool addPreRegAlloc();
110 virtual bool addPostRegAlloc();
112 virtual FunctionPass *createTargetRegisterAllocator(bool) LLVM_OVERRIDE;
113 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
114 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
116 } // end anonymous namespace
118 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
119 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
123 void NVPTXPassConfig::addIRPasses() {
124 // The following passes are known to not play well with virtual regs hanging
125 // around after register allocation (which in our case, is *all* registers).
126 // We explicitly disable them here. We do, however, need some functionality
127 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
128 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
129 disablePass(&PrologEpilogCodeInserterID);
130 disablePass(&MachineCopyPropagationID);
131 disablePass(&BranchFolderPassID);
133 TargetPassConfig::addIRPasses();
134 addPass(createGenericToNVVMPass());
137 bool NVPTXPassConfig::addInstSelector() {
138 addPass(createLowerAggrCopies());
139 addPass(createSplitBBatBarPass());
140 addPass(createAllocaHoisting());
141 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
145 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
146 bool NVPTXPassConfig::addPostRegAlloc() {
147 addPass(createNVPTXPrologEpilogPass());
151 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
152 return 0; // No reg alloc
155 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
156 assert(!RegAllocPass && "NVPTX uses no regalloc!");
157 addPass(&PHIEliminationID);
158 addPass(&TwoAddressInstructionPassID);
161 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
162 assert(!RegAllocPass && "NVPTX uses no regalloc!");
164 addPass(&ProcessImplicitDefsID);
165 addPass(&LiveVariablesID);
166 addPass(&MachineLoopInfoID);
167 addPass(&PHIEliminationID);
169 addPass(&TwoAddressInstructionPassID);
170 addPass(&RegisterCoalescerID);
172 // PreRA instruction scheduling.
173 if (addPass(&MachineSchedulerID))
174 printAndVerify("After Machine Scheduling");
177 addPass(&StackSlotColoringID);
179 // FIXME: Needs physical registers
180 //addPass(&PostRAMachineLICMID);
182 printAndVerify("After StackSlotColoring");