2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
16 #include "PIC16ISelLowering.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
31 static const char *getIntrinsicName(unsigned opcode) {
34 default: assert (0 && "do not know intrinsic name");
35 // Arithmetic Right shift for integer types.
36 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
37 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
38 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
40 // Left shift for integer types.
41 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
42 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
43 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
45 // Logical Right Shift for integer types.
46 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
47 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
48 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
50 // Multiply for integer types.
51 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
52 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
53 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
55 // Signed division for integers.
56 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
57 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
59 // Unsigned division for integers.
60 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
61 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
63 // Signed Modulas for integers.
64 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
65 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
67 // Unsigned Modulas for integers.
68 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
69 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
71 //////////////////////
72 // LIBCALLS FOR FLOATS
73 //////////////////////
75 // Float to signed integrals
76 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
77 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
78 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
80 // Signed integrals to float. char and int are first sign extended to i32
81 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
82 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
84 // Float to Unsigned conversions.
85 // Signed conversion can be used for unsigned conversion as well.
86 // In signed and unsigned versions only the interpretation of the
87 // MSB is different. Bit representation remains the same.
88 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
89 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
90 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
92 // Unsigned to Float conversions. char and int are first zero extended
93 // before being converted to float.
94 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
96 // Floating point add, sub, mul, div.
97 case RTLIB::ADD_F32: Basename = "add.f32"; break;
98 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
99 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
100 case RTLIB::DIV_F32: Basename = "div.f32"; break;
102 // Floating point comparison
103 case RTLIB::O_F32: Basename = "unordered.f32"; break;
104 case RTLIB::UO_F32: Basename = "unordered.f32"; break;
105 case RTLIB::OLE_F32: Basename = "le.f32"; break;
106 case RTLIB::OGE_F32: Basename = "ge.f32"; break;
107 case RTLIB::OLT_F32: Basename = "lt.f32"; break;
108 case RTLIB::OGT_F32: Basename = "gt.f32"; break;
109 case RTLIB::OEQ_F32: Basename = "eq.f32"; break;
110 case RTLIB::UNE_F32: Basename = "neq.f32"; break;
113 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
114 std::string tagname = PAN::getTagName(PAN::LIBCALL);
115 std::string Fullname = prefix + tagname + Basename;
117 // The name has to live through program life.
118 char *tmp = new char[Fullname.size() + 1];
119 strcpy (tmp, Fullname.c_str());
124 // PIC16TargetLowering Constructor.
125 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
126 : TargetLowering(TM), TmpSize(0) {
128 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
130 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
132 setShiftAmountType(MVT::i8);
133 setShiftAmountFlavor(Extend);
135 // SRA library call names
136 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
137 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
138 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
140 // SHL library call names
141 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
142 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
143 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
145 // SRL library call names
146 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
147 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
148 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
150 // MUL Library call names
151 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
152 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
153 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
155 // Signed division lib call names
156 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
157 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
159 // Unsigned division lib call names
160 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
161 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
163 // Signed remainder lib call names
164 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
165 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
167 // Unsigned remainder lib call names
168 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
169 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
171 // Floating point to signed int conversions.
172 setLibcallName(RTLIB::FPTOSINT_F32_I8,
173 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
174 setLibcallName(RTLIB::FPTOSINT_F32_I16,
175 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
176 setLibcallName(RTLIB::FPTOSINT_F32_I32,
177 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
179 // Signed int to floats.
180 setLibcallName(RTLIB::SINTTOFP_I32_F32,
181 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
183 // Floating points to unsigned ints.
184 setLibcallName(RTLIB::FPTOUINT_F32_I8,
185 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
186 setLibcallName(RTLIB::FPTOUINT_F32_I16,
187 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
188 setLibcallName(RTLIB::FPTOUINT_F32_I32,
189 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
191 // Unsigned int to floats.
192 setLibcallName(RTLIB::UINTTOFP_I32_F32,
193 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
195 // Floating point add, sub, mul ,div.
196 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
197 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
198 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
199 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
201 // Floationg point comparison
202 setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32));
203 setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32));
204 setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32));
205 setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32));
206 setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32));
207 setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32));
208 setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32));
210 // Return value comparisons of floating point calls.
211 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
220 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
221 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
223 setOperationAction(ISD::LOAD, MVT::i8, Legal);
224 setOperationAction(ISD::LOAD, MVT::i16, Custom);
225 setOperationAction(ISD::LOAD, MVT::i32, Custom);
227 setOperationAction(ISD::STORE, MVT::i8, Legal);
228 setOperationAction(ISD::STORE, MVT::i16, Custom);
229 setOperationAction(ISD::STORE, MVT::i32, Custom);
231 setOperationAction(ISD::ADDE, MVT::i8, Custom);
232 setOperationAction(ISD::ADDC, MVT::i8, Custom);
233 setOperationAction(ISD::SUBE, MVT::i8, Custom);
234 setOperationAction(ISD::SUBC, MVT::i8, Custom);
235 setOperationAction(ISD::SUB, MVT::i8, Custom);
236 setOperationAction(ISD::ADD, MVT::i8, Custom);
237 setOperationAction(ISD::ADD, MVT::i16, Custom);
239 setOperationAction(ISD::OR, MVT::i8, Custom);
240 setOperationAction(ISD::AND, MVT::i8, Custom);
241 setOperationAction(ISD::XOR, MVT::i8, Custom);
243 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
244 setOperationAction(ISD::CALL, MVT::i16, Custom);
245 setOperationAction(ISD::RET, MVT::Other, Custom);
247 setOperationAction(ISD::MUL, MVT::i8, Custom);
248 setOperationAction(ISD::MUL, MVT::i16, Expand);
249 setOperationAction(ISD::MUL, MVT::i32, Expand);
251 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
252 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
253 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
254 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
255 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
256 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
257 setOperationAction(ISD::MULHU, MVT::i8, Expand);
258 setOperationAction(ISD::MULHU, MVT::i16, Expand);
259 setOperationAction(ISD::MULHU, MVT::i32, Expand);
260 setOperationAction(ISD::MULHS, MVT::i8, Expand);
261 setOperationAction(ISD::MULHS, MVT::i16, Expand);
262 setOperationAction(ISD::MULHS, MVT::i32, Expand);
264 setOperationAction(ISD::SRA, MVT::i8, Custom);
265 setOperationAction(ISD::SRA, MVT::i16, Expand);
266 setOperationAction(ISD::SRA, MVT::i32, Expand);
267 setOperationAction(ISD::SHL, MVT::i8, Custom);
268 setOperationAction(ISD::SHL, MVT::i16, Expand);
269 setOperationAction(ISD::SHL, MVT::i32, Expand);
270 setOperationAction(ISD::SRL, MVT::i8, Custom);
271 setOperationAction(ISD::SRL, MVT::i16, Expand);
272 setOperationAction(ISD::SRL, MVT::i32, Expand);
274 // PIC16 does not support shift parts
275 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
276 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
277 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
278 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
279 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
280 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
281 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
282 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
283 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
286 // PIC16 does not have a SETCC, expand it to SELECT_CC.
287 setOperationAction(ISD::SETCC, MVT::i8, Expand);
288 setOperationAction(ISD::SELECT, MVT::i8, Expand);
289 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
290 setOperationAction(ISD::BRIND, MVT::Other, Expand);
292 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
293 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
295 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
296 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
298 // Now deduce the information based on the above mentioned
300 computeRegisterProperties();
303 // getOutFlag - Extract the flag result if the Op has it.
304 static SDValue getOutFlag(SDValue &Op) {
305 // Flag is the last value of the node.
306 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
308 assert (Flag.getValueType() == MVT::Flag
309 && "Node does not have an out Flag");
313 // Get the TmpOffset for FrameIndex
314 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
315 std::map<unsigned, unsigned>::iterator
316 MapIt = FiTmpOffsetMap.find(FI);
317 if (MapIt != FiTmpOffsetMap.end())
318 return MapIt->second;
320 // This FI (FrameIndex) is not yet mapped, so map it
321 FiTmpOffsetMap[FI] = TmpSize;
323 return FiTmpOffsetMap[FI];
326 // To extract chain value from the SDValue Nodes
327 // This function will help to maintain the chain extracting
328 // code at one place. In case of any change in future it will
329 // help maintain the code.
330 static SDValue getChain(SDValue &Op) {
331 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
333 // If the last value returned in Flag then the chain is
334 // second last value returned.
335 if (Chain.getValueType() == MVT::Flag)
336 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
338 // All nodes may not produce a chain. Therefore following assert
339 // verifies that the node is returning a chain only.
340 assert (Chain.getValueType() == MVT::Other
341 && "Node does not have a chain");
346 /// PopulateResults - Helper function to LowerOperation.
347 /// If a node wants to return multiple results after lowering,
348 /// it stuffs them into an array of SDValue called Results.
350 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
351 if (N.getOpcode() == ISD::MERGE_VALUES) {
352 int NumResults = N.getNumOperands();
353 for( int i = 0; i < NumResults; i++)
354 Results.push_back(N.getOperand(i));
357 Results.push_back(N);
360 MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
364 /// The type legalizer framework of generating legalizer can generate libcalls
365 /// only when the operand/result types are illegal.
366 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
367 /// For example an arithmetic right shift. These functions are used to lower
368 /// such operations that generate libcall for legal types.
371 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
373 PIC16LibcallNames[Call] = Name;
377 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
378 return PIC16LibcallNames[Call];
382 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
383 MVT RetVT, const SDValue *Ops,
384 unsigned NumOps, bool isSigned,
385 SelectionDAG &DAG, DebugLoc dl) {
387 TargetLowering::ArgListTy Args;
388 Args.reserve(NumOps);
390 TargetLowering::ArgListEntry Entry;
391 for (unsigned i = 0; i != NumOps; ++i) {
393 Entry.Ty = Entry.Node.getValueType().getTypeForMVT(*DAG.getContext());
394 Entry.isSExt = isSigned;
395 Entry.isZExt = !isSigned;
396 Args.push_back(Entry);
398 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
400 const Type *RetTy = RetVT.getTypeForMVT(*DAG.getContext());
401 std::pair<SDValue,SDValue> CallInfo =
402 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
403 false, 0, CallingConv::C, false, Callee, Args, DAG, dl);
405 return CallInfo.first;
408 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
410 default: return NULL;
411 case PIC16ISD::Lo: return "PIC16ISD::Lo";
412 case PIC16ISD::Hi: return "PIC16ISD::Hi";
413 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
414 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
415 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
416 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
417 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
418 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
419 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
420 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
421 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
422 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
423 case PIC16ISD::BCF: return "PIC16ISD::BCF";
424 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
425 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
426 case PIC16ISD::RLF: return "PIC16ISD::RLF";
427 case PIC16ISD::RRF: return "PIC16ISD::RRF";
428 case PIC16ISD::CALL: return "PIC16ISD::CALL";
429 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
430 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
431 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
432 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
433 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
437 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
438 SmallVectorImpl<SDValue>&Results,
441 switch (N->getOpcode()) {
442 case ISD::GlobalAddress:
443 Results.push_back(ExpandGlobalAddress(N, DAG));
445 case ISD::ExternalSymbol:
446 Results.push_back(ExpandExternalSymbol(N, DAG));
449 Results.push_back(ExpandStore(N, DAG));
452 PopulateResults(ExpandLoad(N, DAG), Results);
455 // Results.push_back(ExpandAdd(N, DAG));
457 case ISD::FrameIndex:
458 Results.push_back(ExpandFrameIndex(N, DAG));
461 assert (0 && "not implemented");
466 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
468 // Currently handling FrameIndex of size MVT::i16 only
469 // One example of this scenario is when return value is written on
472 if (N->getValueType(0) != MVT::i16)
475 // Expand the FrameIndex into ExternalSymbol and a Constant node
476 // The constant will represent the frame index number
477 // Get the current function frame
478 MachineFunction &MF = DAG.getMachineFunction();
479 const Function *Func = MF.getFunction();
480 const std::string Name = Func->getName();
482 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
483 // FIXME there isn't really debug info here
484 DebugLoc dl = FR->getDebugLoc();
486 // Expand FrameIndex like GlobalAddress and ExternalSymbol
487 // Also use Offset field for lo and hi parts. The default
492 SDValue FI = SDValue(N,0);
493 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
494 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
495 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
496 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
497 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
501 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
502 StoreSDNode *St = cast<StoreSDNode>(N);
503 SDValue Chain = St->getChain();
504 SDValue Src = St->getValue();
505 SDValue Ptr = St->getBasePtr();
506 MVT ValueType = Src.getValueType();
507 unsigned StoreOffset = 0;
508 DebugLoc dl = N->getDebugLoc();
510 SDValue PtrLo, PtrHi;
511 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
513 if (ValueType == MVT::i8) {
514 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
516 DAG.getConstant (0 + StoreOffset, MVT::i8));
518 else if (ValueType == MVT::i16) {
519 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
520 SDValue SrcLo, SrcHi;
521 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
522 SDValue ChainLo = Chain, ChainHi = Chain;
523 if (Chain.getOpcode() == ISD::TokenFactor) {
524 ChainLo = Chain.getOperand(0);
525 ChainHi = Chain.getOperand(1);
527 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
530 DAG.getConstant (0 + StoreOffset, MVT::i8));
532 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
534 DAG.getConstant (1 + StoreOffset, MVT::i8));
536 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
539 else if (ValueType == MVT::i32) {
540 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
541 SDValue SrcLo, SrcHi;
542 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
544 // Get the expanded parts of each of SrcLo and SrcHi.
545 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
546 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
547 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
549 SDValue ChainLo = Chain, ChainHi = Chain;
550 if (Chain.getOpcode() == ISD::TokenFactor) {
551 ChainLo = Chain.getOperand(0);
552 ChainHi = Chain.getOperand(1);
554 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
556 if (ChainLo.getOpcode() == ISD::TokenFactor) {
557 ChainLo1 = ChainLo.getOperand(0);
558 ChainLo2 = ChainLo.getOperand(1);
560 if (ChainHi.getOpcode() == ISD::TokenFactor) {
561 ChainHi1 = ChainHi.getOperand(0);
562 ChainHi2 = ChainHi.getOperand(1);
564 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
566 SrcLo1, PtrLo, PtrHi,
567 DAG.getConstant (0 + StoreOffset, MVT::i8));
569 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
570 SrcLo2, PtrLo, PtrHi,
571 DAG.getConstant (1 + StoreOffset, MVT::i8));
573 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
574 SrcHi1, PtrLo, PtrHi,
575 DAG.getConstant (2 + StoreOffset, MVT::i8));
577 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
578 SrcHi2, PtrLo, PtrHi,
579 DAG.getConstant (3 + StoreOffset, MVT::i8));
581 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
582 getChain(Store1), getChain(Store2));
583 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
584 getChain(Store3), getChain(Store4));
585 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
589 assert (0 && "value type not supported");
594 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
596 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
597 // FIXME there isn't really debug info here
598 DebugLoc dl = ES->getDebugLoc();
600 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
601 SDValue Offset = DAG.getConstant(0, MVT::i8);
602 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
603 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
605 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
608 // ExpandGlobalAddress -
609 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
610 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
611 // FIXME there isn't really debug info here
612 DebugLoc dl = G->getDebugLoc();
614 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
617 SDValue Offset = DAG.getConstant(0, MVT::i8);
618 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
619 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
621 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
624 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
625 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
627 if (Op.getOpcode() == ISD::BUILD_PAIR) {
628 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
634 // Return true if DirectAddress is in ROM_SPACE
635 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
637 // RomAddress is a GlobalAddress in ROM_SPACE_
638 // If the Op is not a GlobalAddress return NULL without checking
640 if (!isDirectAddress(Op))
643 // Its a GlobalAddress.
644 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
645 SDValue TGA = Op.getOperand(0).getOperand(0);
646 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
648 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
651 // Any other address space return it false
656 // GetExpandedParts - This function is on the similiar lines as
657 // the GetExpandedInteger in type legalizer is. This returns expanded
658 // parts of Op in Lo and Hi.
660 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
661 SDValue &Lo, SDValue &Hi) {
662 SDNode *N = Op.getNode();
663 DebugLoc dl = N->getDebugLoc();
664 MVT NewVT = getTypeToTransformTo(N->getValueType(0));
666 // Extract the lo component.
667 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
668 DAG.getConstant(0, MVT::i8));
670 // extract the hi component
671 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
672 DAG.getConstant(1, MVT::i8));
675 // Legalize FrameIndex into ExternalSymbol and offset.
677 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
678 SDValue &ES, int &Offset) {
680 MachineFunction &MF = DAG.getMachineFunction();
681 const Function *Func = MF.getFunction();
682 MachineFrameInfo *MFI = MF.getFrameInfo();
683 const std::string Name = Func->getName();
685 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
687 // FrameIndices are not stack offsets. But they represent the request
688 // for space on stack. That space requested may be more than one byte.
689 // Therefore, to calculate the stack offset that a FrameIndex aligns
690 // with, we need to traverse all the FrameIndices available earlier in
691 // the list and add their requested size.
692 unsigned FIndex = FR->getIndex();
694 if (FIndex < ReservedFrameCount) {
695 tmpName = createESName(PAN::getFrameLabel(Name));
696 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
698 for (unsigned i=0; i<FIndex ; ++i) {
699 Offset += MFI->getObjectSize(i);
702 // FrameIndex has been made for some temporary storage
703 tmpName = createESName(PAN::getTempdataLabel(Name));
704 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
705 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
711 // This function legalizes the PIC16 Addresses. If the Pointer is
712 // -- Direct address variable residing
713 // --> then a Banksel for that variable will be created.
715 // --> then it will be treated as an indirect address.
716 // -- Indirect address
717 // --> then the address will be loaded into FSR
718 // -- ADD with constant operand
719 // --> then constant operand of ADD will be returned as Offset
720 // and non-constant operand of ADD will be treated as pointer.
721 // Returns the high and lo part of the address, and the offset(in case of ADD).
723 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
724 SDValue &Lo, SDValue &Hi,
725 unsigned &Offset, DebugLoc dl) {
727 // Offset, by default, should be 0
730 // If the pointer is ADD with constant,
731 // return the constant value as the offset
732 if (Ptr.getOpcode() == ISD::ADD) {
733 SDValue OperLeft = Ptr.getOperand(0);
734 SDValue OperRight = Ptr.getOperand(1);
735 if ((OperLeft.getOpcode() == ISD::Constant) &&
736 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
737 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
739 } else if ((OperRight.getOpcode() == ISD::Constant) &&
740 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
741 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
746 // If the pointer is Type i8 and an external symbol
747 // then treat it as direct address.
748 // One example for such case is storing and loading
749 // from function frame during a call
750 if (Ptr.getValueType() == MVT::i8) {
751 switch (Ptr.getOpcode()) {
752 case ISD::TargetExternalSymbol:
754 Hi = DAG.getConstant(1, MVT::i8);
759 // Expansion of FrameIndex has Lo/Hi parts
760 if (isDirectAddress(Ptr)) {
761 SDValue TFI = Ptr.getOperand(0).getOperand(0);
763 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
764 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
765 Hi = DAG.getConstant(1, MVT::i8);
766 Offset += FrameOffset;
768 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
769 // FrameIndex has already been expanded.
770 // Now just make use of its expansion
772 Hi = DAG.getConstant(1, MVT::i8);
773 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
774 assert (FOffset.getOpcode() == ISD::Constant &&
775 "Invalid operand of PIC16ISD::Lo");
776 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
781 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
782 // Direct addressing case for RAM variables. The Hi part is constant
783 // and the Lo part is the TGA itself.
784 Lo = Ptr.getOperand(0).getOperand(0);
786 // For direct addresses Hi is a constant. Value 1 for the constant
787 // signifies that banksel needs to generated for it. Value 0 for
788 // the constant signifies that banksel does not need to be generated
789 // for it. Mark it as 1 now and optimize later.
790 Hi = DAG.getConstant(1, MVT::i8);
794 // Indirect addresses. Get the hi and lo parts of ptr.
795 GetExpandedParts(Ptr, DAG, Lo, Hi);
797 // Put the hi and lo parts into FSR.
798 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
799 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
804 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
805 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
806 SDValue Chain = LD->getChain();
807 SDValue Ptr = LD->getBasePtr();
808 DebugLoc dl = LD->getDebugLoc();
810 SDValue Load, Offset;
813 SDValue PtrLo, PtrHi;
816 // Legalize direct/indirect addresses. This will give the lo and hi parts
817 // of the address and the offset.
818 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
820 // Load from the pointer (direct address or FSR)
821 VT = N->getValueType(0);
822 unsigned NumLoads = VT.getSizeInBits() / 8;
823 std::vector<SDValue> PICLoads;
825 MVT MemVT = LD->getMemoryVT();
826 if(ISD::isNON_EXTLoad(N)) {
827 for (iter=0; iter<NumLoads ; ++iter) {
828 // Add the pointer offset if any
829 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
830 Tys = DAG.getVTList(MVT::i8, MVT::Other);
831 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
833 PICLoads.push_back(Load);
836 // If it is extended load then use PIC16Load for Memory Bytes
837 // and for all extended bytes perform action based on type of
838 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
841 // For extended loads this is the memory value type
842 // i.e. without any extension
843 MVT MemVT = LD->getMemoryVT();
844 unsigned MemBytes = MemVT.getSizeInBits() / 8;
845 // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
847 if (MemBytes == 0) MemBytes = 1;
849 unsigned ExtdBytes = VT.getSizeInBits() / 8;
850 Offset = DAG.getConstant(LoadOffset, MVT::i8);
852 Tys = DAG.getVTList(MVT::i8, MVT::Other);
853 // For MemBytes generate PIC16Load with proper offset
854 for (iter=0; iter < MemBytes; ++iter) {
855 // Add the pointer offset if any
856 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
857 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
859 PICLoads.push_back(Load);
862 // For SignExtendedLoad
863 if (ISD::isSEXTLoad(N)) {
864 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
866 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
867 DAG.getConstant(7, MVT::i8));
868 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
869 PICLoads.push_back(SRA);
871 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
872 //} else if (ISD::isZEXTLoad(N)) {
873 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
874 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
875 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
876 PICLoads.push_back(ConstZero);
883 // Operand of Load is illegal -- Load itself is legal
886 else if (VT == MVT::i16) {
887 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
888 if (MemVT == MVT::i8)
889 Chain = getChain(PICLoads[0]);
891 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
892 getChain(PICLoads[0]), getChain(PICLoads[1]));
893 } else if (VT == MVT::i32) {
895 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
896 PICLoads[0], PICLoads[1]);
897 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
898 PICLoads[2], PICLoads[3]);
899 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
900 if (MemVT == MVT::i8)
901 Chain = getChain(PICLoads[0]);
902 else if (MemVT == MVT::i16)
903 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
904 getChain(PICLoads[0]), getChain(PICLoads[1]));
907 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
908 getChain(PICLoads[0]), getChain(PICLoads[1]));
909 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
910 getChain(PICLoads[2]), getChain(PICLoads[3]));
911 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
912 Chains[0], Chains[1]);
915 Tys = DAG.getVTList(VT, MVT::Other);
916 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
919 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
920 // We should have handled larger operands in type legalizer itself.
921 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
923 SDNode *N = Op.getNode();
924 SDValue Value = N->getOperand(0);
925 SDValue Amt = N->getOperand(1);
926 PIC16ISD::PIC16Libcall CallCode;
927 switch (N->getOpcode()) {
929 CallCode = PIC16ISD::SRA_I8;
932 CallCode = PIC16ISD::SLL_I8;
935 CallCode = PIC16ISD::SRL_I8;
938 assert ( 0 && "This shift is not implemented yet.");
941 SmallVector<SDValue, 2> Ops(2);
944 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
945 true, DAG, N->getDebugLoc());
950 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
951 SmallVectorImpl<SDValue>&Results,
953 SDValue Op = SDValue(N, 0);
956 switch (Op.getOpcode()) {
957 case ISD::FORMAL_ARGUMENTS:
958 Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
960 Res = ExpandLoad(Op.getNode(), DAG); break;
962 Res = LowerCALL(Op, DAG); break;
964 // All other operations are handled in LowerOperation.
965 Res = LowerOperation(Op, DAG);
967 Results.push_back(Res);
974 unsigned NumValues = N->getNumValues();
975 for (i = 0; i < NumValues ; i++) {
976 Results.push_back(SDValue(N, i));
980 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
981 switch (Op.getOpcode()) {
982 case ISD::FORMAL_ARGUMENTS:
983 return LowerFORMAL_ARGUMENTS(Op, DAG);
987 return LowerADD(Op, DAG);
991 return LowerSUB(Op, DAG);
993 return ExpandLoad(Op.getNode(), DAG);
995 return ExpandStore(Op.getNode(), DAG);
999 return LowerShift(Op, DAG);
1003 return LowerBinOp(Op, DAG);
1005 return LowerCALL(Op, DAG);
1007 return LowerRET(Op, DAG);
1009 return LowerBR_CC(Op, DAG);
1010 case ISD::SELECT_CC:
1011 return LowerSELECT_CC(Op, DAG);
1016 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
1019 assert (Op.getValueType() == MVT::i8
1020 && "illegal value type to store on stack.");
1022 MachineFunction &MF = DAG.getMachineFunction();
1023 const Function *Func = MF.getFunction();
1024 const std::string FuncName = Func->getName();
1027 // Put the value on stack.
1028 // Get a stack slot index and convert to es.
1029 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
1030 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
1031 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1033 // Store the value to ES.
1034 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1037 DAG.getConstant (1, MVT::i8), // Banksel.
1038 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1041 // Load the value from ES.
1042 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1043 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1044 ES, DAG.getConstant (1, MVT::i8),
1045 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1048 return Load.getValue(0);
1051 SDValue PIC16TargetLowering::
1052 LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag,
1053 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1054 SelectionDAG &DAG) {
1055 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1056 unsigned NumOps = TheCall->getNumArgs();
1057 DebugLoc dl = TheCall->getDebugLoc();
1059 // If call has no arguments then do nothing and return.
1063 std::vector<SDValue> Ops;
1064 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1065 SDValue Arg, StoreRet;
1067 // For PIC16 ABI the arguments come after the return value.
1068 unsigned RetVals = TheCall->getNumRetVals();
1069 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1070 // Get the arguments
1071 Arg = TheCall->getArg(i);
1074 Ops.push_back(Chain);
1076 Ops.push_back(DataAddr_Lo);
1077 Ops.push_back(DataAddr_Hi);
1078 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1079 Ops.push_back(InFlag);
1081 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1083 Chain = getChain(StoreRet);
1084 InFlag = getOutFlag(StoreRet);
1090 SDValue PIC16TargetLowering::
1091 LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue ArgLabel,
1092 SDValue InFlag, SelectionDAG &DAG) {
1093 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1094 unsigned NumOps = TheCall->getNumArgs();
1095 DebugLoc dl = TheCall->getDebugLoc();
1097 SDValue Arg, StoreAt;
1100 unsigned ArgCount=0;
1102 // If call has no arguments then do nothing and return.
1106 // FIXME: This portion of code currently assumes only
1107 // primitive types being passed as arguments.
1109 // Legalize the address before use
1110 SDValue PtrLo, PtrHi;
1111 unsigned AddressOffset;
1112 int StoreOffset = 0;
1113 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1116 std::vector<SDValue> Ops;
1117 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1118 for (unsigned i=ArgCount, Offset = 0; i<NumOps; i++) {
1120 Arg = TheCall->getArg(i);
1121 StoreOffset = (Offset + AddressOffset);
1123 // Store the argument on frame
1126 Ops.push_back(Chain);
1128 Ops.push_back(PtrLo);
1129 Ops.push_back(PtrHi);
1130 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1131 Ops.push_back(InFlag);
1133 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1135 Chain = getChain(StoreRet);
1136 InFlag = getOutFlag(StoreRet);
1138 // Update the frame offset to be used for next argument
1139 ArgVT = Arg.getValueType();
1140 Size = ArgVT.getSizeInBits();
1141 Size = Size/8; // Calculate size in bytes
1142 Offset += Size; // Increase the frame offset
1147 SDValue PIC16TargetLowering::
1148 LowerIndirectCallReturn (SDValue Op, SDValue Chain, SDValue InFlag,
1149 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1150 SelectionDAG &DAG) {
1151 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1152 DebugLoc dl = TheCall->getDebugLoc();
1153 unsigned RetVals = TheCall->getNumRetVals();
1155 // If call does not have anything to return
1156 // then do nothing and go back.
1160 // Call has something to return
1161 std::vector<SDValue> ResultVals;
1164 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1165 for(unsigned i=0;i<RetVals;i++) {
1166 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1167 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1169 InFlag = getOutFlag(LoadRet);
1170 Chain = getChain(LoadRet);
1171 ResultVals.push_back(LoadRet);
1173 ResultVals.push_back(Chain);
1174 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1178 SDValue PIC16TargetLowering::
1179 LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue RetLabel,
1180 SDValue InFlag, SelectionDAG &DAG) {
1181 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1182 DebugLoc dl = TheCall->getDebugLoc();
1183 // Currently handling primitive types only. They will come in
1185 unsigned RetVals = TheCall->getNumRetVals();
1187 std::vector<SDValue> ResultVals;
1189 // Return immediately if the return type is void
1193 // Call has something to return
1195 // Legalize the address before use
1198 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1200 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1203 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1205 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1206 DAG.getConstant(LdOffset + Offset, MVT::i8),
1209 InFlag = getOutFlag(LoadRet);
1211 Chain = getChain(LoadRet);
1213 ResultVals.push_back(LoadRet);
1216 // To return use MERGE_VALUES
1217 ResultVals.push_back(Chain);
1218 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1222 SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1223 SDValue Chain = Op.getOperand(0);
1224 DebugLoc dl = Op.getDebugLoc();
1226 if (Op.getNumOperands() == 1) // return void
1229 // return should have odd number of operands
1230 if ((Op.getNumOperands() % 2) == 0 ) {
1231 LLVM_UNREACHABLE("Do not know how to return this many arguments!");
1234 // Number of values to return
1235 unsigned NumRet = (Op.getNumOperands() / 2);
1237 // Function returns value always on stack with the offset starting
1239 MachineFunction &MF = DAG.getMachineFunction();
1240 const Function *F = MF.getFunction();
1241 std::string FuncName = F->getName();
1243 const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
1244 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1245 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1246 SDValue BS = DAG.getConstant(1, MVT::i8);
1248 for(unsigned i=0;i<NumRet; ++i) {
1249 RetVal = Op.getNode()->getOperand(2*i + 1);
1250 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1252 DAG.getConstant (i, MVT::i8));
1255 return DAG.getNode(ISD::RET, dl, MVT::Other, Chain);
1258 // CALL node may have some operands non-legal to PIC16. Generate new CALL
1259 // node with all the operands legal.
1260 // Currently only Callee operand of the CALL node is non-legal. This function
1261 // legalizes the Callee operand and uses all other operands as are to generate
1264 SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) {
1265 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1266 SDValue Chain = TheCall->getChain();
1267 SDValue Callee = TheCall->getCallee();
1268 DebugLoc dl = TheCall->getDebugLoc();
1271 assert(Callee.getValueType() == MVT::i16 &&
1272 "Don't know how to legalize this call node!!!");
1273 assert(Callee.getOpcode() == ISD::BUILD_PAIR &&
1274 "Don't know how to legalize this call node!!!");
1276 if (isDirectAddress(Callee)) {
1277 // Come here for direct calls
1278 Callee = Callee.getOperand(0).getOperand(0);
1280 // Come here for indirect calls
1282 // Indirect addresses. Get the hi and lo parts of ptr.
1283 GetExpandedParts(Callee, DAG, Lo, Hi);
1284 // Connect Lo and Hi parts of the callee with the PIC16Connect
1285 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1287 std::vector<SDValue> Ops;
1288 Ops.push_back(Chain);
1289 Ops.push_back(Callee);
1291 // Add the call arguments and their flags
1292 unsigned NumArgs = TheCall->getNumArgs();
1293 for(i=0;i<NumArgs;i++) {
1294 Ops.push_back(TheCall->getArg(i));
1295 Ops.push_back(TheCall->getArgFlagsVal(i));
1297 std::vector<MVT> NodeTys;
1298 unsigned NumRets = TheCall->getNumRetVals();
1299 for(i=0;i<NumRets;i++)
1300 NodeTys.push_back(TheCall->getRetValType(i));
1302 // Return a Chain as well
1303 NodeTys.push_back(MVT::Other);
1305 SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
1306 // Generate new call with all the operands legal
1307 return DAG.getCall(TheCall->getCallingConv(), dl,
1308 TheCall->isVarArg(), TheCall->isTailCall(),
1309 TheCall->isInreg(), VTs, &Ops[0], Ops.size(),
1310 TheCall->getNumFixedArgs());
1313 void PIC16TargetLowering::
1314 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1315 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1316 SelectionDAG &DAG) {
1317 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1318 && "Don't know what to do of such callee!!");
1319 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1320 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1321 Chain = getChain(SeqStart);
1322 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1324 // Get the Lo and Hi part of code address
1325 SDValue Lo = Callee.getOperand(0);
1326 SDValue Hi = Callee.getOperand(1);
1328 SDValue Data_Lo, Data_Hi;
1329 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1330 // Subtract 2 from Address to get the Lower part of DataAddress.
1331 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1332 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1333 DAG.getConstant(2, MVT::i8));
1334 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1335 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1336 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1337 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1338 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1340 Chain = getChain(Call);
1341 OperFlag = getOutFlag(Call);
1342 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1344 Chain = getChain(SeqEnd);
1345 OperFlag = getOutFlag(SeqEnd);
1347 // Low part of Data Address
1348 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1350 // Make the second call.
1351 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1352 Chain = getChain(SeqStart);
1353 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1355 // Subtract 1 from Address to get high part of data address.
1356 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1357 DAG.getConstant(1, MVT::i8));
1358 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1359 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1360 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1362 // Use new Lo to make another CALLW
1363 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1364 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1365 Chain = getChain(Call);
1366 OperFlag = getOutFlag(Call);
1367 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1369 Chain = getChain(SeqEnd);
1370 OperFlag = getOutFlag(SeqEnd);
1371 // Hi part of Data Address
1372 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1376 SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1377 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1378 SDValue Chain = TheCall->getChain();
1379 SDValue Callee = TheCall->getCallee();
1380 DebugLoc dl = TheCall->getDebugLoc();
1381 if (Callee.getValueType() == MVT::i16 &&
1382 Callee.getOpcode() == ISD::BUILD_PAIR) {
1383 // Control should come here only from TypeLegalizer for lowering
1385 // Legalize the non-legal arguments of call and return the
1386 // new call with legal arguments.
1387 return LegalizeCALL(Op, DAG);
1389 // Control should come here from Legalize DAG.
1390 // Here all the operands of CALL node should be legal.
1392 // If this is an indirect call then to pass the arguments
1393 // and read the return value back, we need the data address
1394 // of the function being called.
1395 // To get the data address two more calls need to be made.
1397 // The flag to track if this is a direct or indirect call.
1398 bool IsDirectCall = true;
1399 unsigned RetVals = TheCall->getNumRetVals();
1400 unsigned NumArgs = TheCall->getNumArgs();
1402 SDValue DataAddr_Lo, DataAddr_Hi;
1403 if (Callee.getOpcode() == PIC16ISD::PIC16Connect) {
1404 IsDirectCall = false; // This is indirect call
1405 // Read DataAddress only if we have to pass arguments or
1406 // read return value.
1407 if ((RetVals > 0) || (NumArgs > 0))
1408 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1411 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1413 // Start the call sequence.
1414 // Carring the Constant 0 along the CALLSEQSTART
1415 // because there is nothing else to carry.
1416 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1417 Chain = getChain(SeqStart);
1418 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1421 // For any direct call - callee will be GlobalAddressNode or
1423 SDValue ArgLabel, RetLabel;
1425 // Considering the GlobalAddressNode case here.
1426 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1427 GlobalValue *GV = G->getGlobal();
1428 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1429 Name = G->getGlobal()->getName();
1430 } else {// Considering the ExternalSymbol case here
1431 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1432 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1433 Name = ES->getSymbol();
1436 // Label for argument passing
1437 const char *argFrame = createESName(PAN::getArgsLabel(Name));
1438 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1440 // Label for reading return value
1441 const char *retName = createESName(PAN::getRetvalLabel(Name));
1442 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1445 SDValue CodeAddr_Lo = Callee.getOperand(0);
1446 SDValue CodeAddr_Hi = Callee.getOperand(1);
1448 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1449 DAG.getConstant(2, MVT::i8));*/
1451 // move Hi part in PCLATH
1452 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1453 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1457 // Pass the argument to function before making the call.
1460 CallArgs = LowerDirectCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
1461 Chain = getChain(CallArgs);
1462 OperFlag = getOutFlag(CallArgs);
1464 CallArgs = LowerIndirectCallArguments(Op, Chain, OperFlag, DataAddr_Lo,
1466 Chain = getChain(CallArgs);
1467 OperFlag = getOutFlag(CallArgs);
1470 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1471 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1473 Chain = getChain(PICCall);
1474 OperFlag = getOutFlag(PICCall);
1477 // Carrying the Constant 0 along the CALLSEQSTART
1478 // because there is nothing else to carry.
1479 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1481 Chain = getChain(SeqEnd);
1482 OperFlag = getOutFlag(SeqEnd);
1484 // Lower the return value reading after the call.
1486 return LowerDirectCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
1488 return LowerIndirectCallReturn(Op, Chain, OperFlag, DataAddr_Lo,
1492 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1493 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1494 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1495 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1500 // NeedToConvertToMemOp - Returns true if one of the operands of the
1501 // operation 'Op' needs to be put into memory. Also returns the
1502 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1503 // no instruction that can operation on two registers. Most insns take
1504 // one register and one memory operand (addwf) / Constant (addlw).
1505 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1506 // If one of the operand is a constant, return false.
1507 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1508 Op.getOperand(1).getOpcode() == ISD::Constant)
1511 // Return false if one of the operands is already a direct
1512 // load and that operand has only one use.
1513 if (isDirectLoad(Op.getOperand(0))) {
1514 if (Op.getOperand(0).hasOneUse())
1519 if (isDirectLoad(Op.getOperand(1))) {
1520 if (Op.getOperand(1).hasOneUse())
1528 // LowerBinOp - Lower a commutative binary operation that does not
1529 // affect status flag carry.
1530 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1531 DebugLoc dl = Op.getDebugLoc();
1533 // We should have handled larger operands in type legalizer itself.
1534 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1537 if (NeedToConvertToMemOp(Op, MemOp)) {
1538 // Put one value on stack.
1539 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1541 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1549 // LowerADD - Lower all types of ADD operations including the ones
1550 // that affects carry.
1551 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1552 // We should have handled larger operands in type legalizer itself.
1553 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1554 DebugLoc dl = Op.getDebugLoc();
1556 if (NeedToConvertToMemOp(Op, MemOp)) {
1557 // Put one value on stack.
1558 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1560 // ADDC and ADDE produce two results.
1561 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1563 // ADDE has three operands, the last one is the carry bit.
1564 if (Op.getOpcode() == ISD::ADDE)
1565 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1566 NewVal, Op.getOperand(2));
1567 // ADDC has two operands.
1568 else if (Op.getOpcode() == ISD::ADDC)
1569 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1571 // ADD it is. It produces only one result.
1573 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1580 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1581 DebugLoc dl = Op.getDebugLoc();
1582 // We should have handled larger operands in type legalizer itself.
1583 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1585 // Nothing to do if the first operand is already a direct load and it has
1587 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1590 // Put first operand on stack.
1591 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1593 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1594 if (Op.getOpcode() == ISD::SUBE)
1595 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1598 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1601 void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
1602 unsigned NumArgs = F->arg_size();
1604 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1607 ReservedFrameCount = NumArgs;
1609 ReservedFrameCount = NumArgs + 1;
1612 // LowerFORMAL_ARGUMENTS - Argument values are loaded from the
1613 // <fname>.args + offset. All arguments are already broken to leaglized
1614 // types, so the offset just runs from 0 to NumArgVals - 1.
1616 SDValue PIC16TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1617 SelectionDAG &DAG) {
1618 SmallVector<SDValue, 8> ArgValues;
1619 unsigned NumArgVals = Op.getNode()->getNumValues() - 1;
1620 DebugLoc dl = Op.getDebugLoc();
1621 SDValue Chain = Op.getOperand(0); // Formal arguments' chain
1624 // Get the callee's name to create the <fname>.args label to pass args.
1625 MachineFunction &MF = DAG.getMachineFunction();
1626 const Function *F = MF.getFunction();
1627 std::string FuncName = F->getName();
1629 // Reset the map of FI and TmpOffset
1630 ResetTmpOffsetMap();
1631 // Initialize the ReserveFrameCount
1632 InitReservedFrameCount(F);
1634 // Create the <fname>.args external symbol.
1635 const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
1636 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1638 // Load arg values from the label + offset.
1639 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1640 SDValue BS = DAG.getConstant(1, MVT::i8);
1641 for (unsigned i = 0; i < NumArgVals ; ++i) {
1642 SDValue Offset = DAG.getConstant(i, MVT::i8);
1643 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1645 Chain = getChain(PICLoad);
1646 ArgValues.push_back(PICLoad);
1649 // Return a MERGE_VALUE node.
1650 ArgValues.push_back(Op.getOperand(0));
1651 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1652 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1655 // Perform DAGCombine of PIC16Load.
1656 // FIXME - Need a more elaborate comment here.
1657 SDValue PIC16TargetLowering::
1658 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1659 SelectionDAG &DAG = DCI.DAG;
1660 SDValue Chain = N->getOperand(0);
1661 if (N->hasNUsesOfValue(0, 0)) {
1662 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1667 // For all the functions with arguments some STORE nodes are generated
1668 // that store the argument on the frameindex. However in PIC16 the arguments
1669 // are passed on stack only. Therefore these STORE nodes are redundant.
1670 // To remove these STORE nodes will be removed in PerformStoreCombine
1672 // Currently this function is doint nothing and will be updated for removing
1673 // unwanted store operations
1674 SDValue PIC16TargetLowering::
1675 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1676 return SDValue(N, 0);
1678 // Storing an undef value is of no use, so remove it
1679 if (isStoringUndef(N, Chain, DAG)) {
1680 return Chain; // remove the store and return the chain
1682 //else everything is ok.
1683 return SDValue(N, 0);
1687 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1688 DAGCombinerInfo &DCI) const {
1689 switch (N->getOpcode()) {
1691 return PerformStoreCombine(N, DCI);
1692 case PIC16ISD::PIC16Load:
1693 return PerformPIC16LoadCombine(N, DCI);
1698 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1700 default: assert(0 && "Unknown condition code!");
1701 case ISD::SETNE: return PIC16CC::NE;
1702 case ISD::SETEQ: return PIC16CC::EQ;
1703 case ISD::SETGT: return PIC16CC::GT;
1704 case ISD::SETGE: return PIC16CC::GE;
1705 case ISD::SETLT: return PIC16CC::LT;
1706 case ISD::SETLE: return PIC16CC::LE;
1707 case ISD::SETULT: return PIC16CC::ULT;
1708 case ISD::SETULE: return PIC16CC::ULE;
1709 case ISD::SETUGE: return PIC16CC::UGE;
1710 case ISD::SETUGT: return PIC16CC::UGT;
1714 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1715 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1716 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1717 ISD::CondCode CC, unsigned &SPCC) {
1718 if (isa<ConstantSDNode>(RHS) &&
1719 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1721 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1722 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1723 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1724 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1725 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1726 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1727 SDValue CMPCC = LHS.getOperand(3);
1728 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1729 LHS = CMPCC.getOperand(0);
1730 RHS = CMPCC.getOperand(1);
1734 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1735 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1736 unsigned CC, SDValue &PIC16CC,
1737 SelectionDAG &DAG, DebugLoc dl) {
1738 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1740 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1741 // i.e. a < 12 can be rewritten as 12 > a.
1742 if (RHS.getOpcode() == ISD::Constant) {
1751 CondCode = PIC16CC::GT;
1754 CondCode = PIC16CC::LT;
1757 CondCode = PIC16CC::UGT;
1760 CondCode = PIC16CC::ULT;
1763 CondCode = PIC16CC::LE;
1766 CondCode = PIC16CC::GE;
1769 CondCode = PIC16CC::UGE;
1772 CondCode = PIC16CC::ULE;
1777 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1779 // These are signed comparisons.
1780 SDValue Mask = DAG.getConstant(128, MVT::i8);
1781 if (isSignedComparison(CondCode)) {
1782 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1783 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1786 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1787 // We can use a subtract operation to set the condition codes. But
1788 // we need to put one operand in memory if required.
1789 // Nothing to do if the first operand is already a valid type (direct load
1790 // for subwf and literal for sublw) and it is used by this operation only.
1791 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1793 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1795 // else convert the first operand to mem.
1796 LHS = ConvertToMemOperand (LHS, DAG, dl);
1797 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1801 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1802 SDValue LHS = Op.getOperand(0);
1803 SDValue RHS = Op.getOperand(1);
1804 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1805 SDValue TrueVal = Op.getOperand(2);
1806 SDValue FalseVal = Op.getOperand(3);
1807 unsigned ORIGCC = ~0;
1808 DebugLoc dl = Op.getDebugLoc();
1810 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1811 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1813 // A setcc: lhs, rhs, cc is expanded by llvm to
1814 // select_cc: result of setcc, 0, 1, 0, setne
1815 // We can think of it as:
1816 // select_cc: lhs, rhs, 1, 0, cc
1817 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1818 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1821 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1823 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1824 FalseVal, PIC16CC, Cmp.getValue(1));
1828 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1829 MachineBasicBlock *BB) const {
1830 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1831 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1832 DebugLoc dl = MI->getDebugLoc();
1834 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1835 // control-flow pattern. The incoming instruction knows the destination vreg
1836 // to set, the condition code register to branch on, the true/false values to
1837 // select between, and a branch opcode to use.
1838 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1839 MachineFunction::iterator It = BB;
1846 // fallthrough --> copy0MBB
1847 MachineBasicBlock *thisMBB = BB;
1848 MachineFunction *F = BB->getParent();
1849 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1850 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1851 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1852 F->insert(It, copy0MBB);
1853 F->insert(It, sinkMBB);
1855 // Update machine-CFG edges by transferring all successors of the current
1856 // block to the new block which will contain the Phi node for the select.
1857 sinkMBB->transferSuccessors(BB);
1858 // Next, add the true and fallthrough blocks as its successors.
1859 BB->addSuccessor(copy0MBB);
1860 BB->addSuccessor(sinkMBB);
1863 // %FalseValue = ...
1864 // # fallthrough to sinkMBB
1867 // Update machine-CFG edges
1868 BB->addSuccessor(sinkMBB);
1871 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1874 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1875 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1876 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1878 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1883 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1884 SDValue Chain = Op.getOperand(0);
1885 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1886 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1887 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1888 SDValue Dest = Op.getOperand(4); // BB to jump to
1889 unsigned ORIGCC = ~0;
1890 DebugLoc dl = Op.getDebugLoc();
1892 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1893 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1894 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1895 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1897 // Get the Compare insn and condition code.
1899 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1901 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,