1 //===-- PIC16ISelLowering.cpp - PIC16 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pic16-lower"
17 #include "PIC16ISelLowering.h"
18 #include "PIC16TargetMachine.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/Support/Debug.h"
36 const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const
39 case PIC16ISD::Hi : return "PIC16ISD::Hi";
40 case PIC16ISD::Lo : return "PIC16ISD::Lo";
41 case PIC16ISD::Package : return "PIC16ISD::Package";
42 case PIC16ISD::Wrapper : return "PIC16ISD::Wrapper";
43 case PIC16ISD::SetBank : return "PIC16ISD::SetBank";
44 case PIC16ISD::SetPage : return "PIC16ISD::SetPage";
45 case PIC16ISD::Branch : return "PIC16ISD::Branch";
46 case PIC16ISD::Cmp : return "PIC16ISD::Cmp";
47 case PIC16ISD::BTFSS : return "PIC16ISD::BTFSS";
48 case PIC16ISD::BTFSC : return "PIC16ISD::BTFSC";
49 case PIC16ISD::XORCC : return "PIC16ISD::XORCC";
50 case PIC16ISD::SUBCC : return "PIC16ISD::SUBCC";
51 default : return NULL;
56 PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
58 // Set up the register classes.
59 addRegisterClass(MVT::i8, PIC16::CPURegsRegisterClass);
60 addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass);
62 // Load extented operations for i1 types must be promoted .
63 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
64 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
65 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setOperationAction(ISD::ADD, MVT::i1, Promote);
68 setOperationAction(ISD::ADD, MVT::i8, Legal);
69 setOperationAction(ISD::ADD, MVT::i16, Custom);
70 setOperationAction(ISD::ADD, MVT::i32, Expand);
71 setOperationAction(ISD::ADD, MVT::i64, Expand);
73 setOperationAction(ISD::SUB, MVT::i1, Promote);
74 setOperationAction(ISD::SUB, MVT::i8, Legal);
75 setOperationAction(ISD::SUB, MVT::i16, Custom);
76 setOperationAction(ISD::SUB, MVT::i32, Expand);
77 setOperationAction(ISD::SUB, MVT::i64, Expand);
79 setOperationAction(ISD::ADDC, MVT::i1, Promote);
80 setOperationAction(ISD::ADDC, MVT::i8, Legal);
81 setOperationAction(ISD::ADDC, MVT::i16, Custom);
82 setOperationAction(ISD::ADDC, MVT::i32, Expand);
83 setOperationAction(ISD::ADDC, MVT::i64, Expand);
85 setOperationAction(ISD::ADDE, MVT::i1, Promote);
86 setOperationAction(ISD::ADDE, MVT::i8, Legal);
87 setOperationAction(ISD::ADDE, MVT::i16, Custom);
88 setOperationAction(ISD::ADDE, MVT::i32, Expand);
89 setOperationAction(ISD::ADDE, MVT::i64, Expand);
91 setOperationAction(ISD::SUBC, MVT::i1, Promote);
92 setOperationAction(ISD::SUBC, MVT::i8, Legal);
93 setOperationAction(ISD::SUBC, MVT::i16, Custom);
94 setOperationAction(ISD::SUBC, MVT::i32, Expand);
95 setOperationAction(ISD::SUBC, MVT::i64, Expand);
97 setOperationAction(ISD::SUBE, MVT::i1, Promote);
98 setOperationAction(ISD::SUBE, MVT::i8, Legal);
99 setOperationAction(ISD::SUBE, MVT::i16, Custom);
100 setOperationAction(ISD::SUBE, MVT::i32, Expand);
101 setOperationAction(ISD::SUBE, MVT::i64, Expand);
103 // PIC16 does not have these NodeTypes below.
104 setOperationAction(ISD::SETCC, MVT::i1, Expand);
105 setOperationAction(ISD::SETCC, MVT::i8, Expand);
106 setOperationAction(ISD::SETCC, MVT::Other, Expand);
107 setOperationAction(ISD::SELECT_CC, MVT::i1, Custom);
108 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
110 setOperationAction(ISD::BRCOND, MVT::i1, Expand);
111 setOperationAction(ISD::BRCOND, MVT::i8, Expand);
112 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
114 setOperationAction(ISD::BR_CC, MVT::i1, Custom);
115 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 // FIXME: Do we really need to Custom lower the GA ??
121 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
122 setOperationAction(ISD::RET, MVT::Other, Custom);
124 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
125 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
126 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
127 setOperationAction(ISD::ROTL, MVT::i32, Expand);
128 setOperationAction(ISD::ROTR, MVT::i32, Expand);
129 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
131 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
132 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
133 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
135 // We don't have line number support yet.
136 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
137 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
138 setOperationAction(ISD::LABEL, MVT::Other, Expand);
140 // Use the default for now.
141 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
142 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
144 setOperationAction(ISD::LOAD, MVT::i1, Promote);
145 setOperationAction(ISD::LOAD, MVT::i8, Legal);
147 setTargetDAGCombine(ISD::LOAD);
148 setTargetDAGCombine(ISD::STORE);
149 setTargetDAGCombine(ISD::ADDE);
150 setTargetDAGCombine(ISD::ADDC);
151 setTargetDAGCombine(ISD::ADD);
152 setTargetDAGCombine(ISD::SUBE);
153 setTargetDAGCombine(ISD::SUBC);
154 setTargetDAGCombine(ISD::SUB);
156 setStackPointerRegisterToSaveRestore(PIC16::STKPTR);
157 computeRegisterProperties();
161 SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
163 SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other);
164 switch (Op.getOpcode()) {
166 DOUT << "reduce store\n";
169 case ISD::FORMAL_ARGUMENTS:
170 DOUT << "==== lowering formal args\n";
171 return LowerFORMAL_ARGUMENTS(Op, DAG);
173 case ISD::GlobalAddress:
174 DOUT << "==== lowering GA\n";
175 return LowerGlobalAddress(Op, DAG);
178 DOUT << "==== lowering ret\n";
179 return LowerRET(Op, DAG);
181 case ISD::FrameIndex:
182 DOUT << "==== lowering frame index\n";
183 return LowerFrameIndex(Op, DAG);
186 DOUT << "==== lowering adde\n";
194 DOUT << "==== lowering BR_CC\n";
195 return LowerBR_CC(Op, DAG);
201 //===----------------------------------------------------------------------===//
202 // Lower helper functions
203 //===----------------------------------------------------------------------===//
205 SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
207 MVT::ValueType VT = Op.getValueType();
208 SDOperand Chain = Op.getOperand(0);
209 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
210 SDOperand LHS = Op.getOperand(2);
211 SDOperand RHS = Op.getOperand(3);
212 SDOperand JumpVal = Op.getOperand(4);
215 unsigned branchOpcode;
216 SDOperand branchOperand;
218 SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG, MVT::i8);
219 SDOperand CPUReg = DAG.getRegister(PIC16::WREG, MVT::i8);
222 assert(0 && "This condition code is not handled yet!!");
227 cmpOpcode = PIC16ISD::XORCC;
228 branchOpcode = PIC16ISD::BTFSS;
229 branchOperand = DAG.getConstant(2, MVT::i8);
234 cmpOpcode = PIC16ISD::XORCC;
235 branchOpcode = PIC16ISD::BTFSC;
236 branchOperand = DAG.getConstant(2, MVT::i8);
240 assert(0 && "Greater Than condition code is not handled yet!!");
246 cmpOpcode = PIC16ISD::SUBCC;
247 branchOpcode = PIC16ISD::BTFSS;
248 branchOperand = DAG.getConstant(1, MVT::i8);
253 cmpOpcode = PIC16ISD::SUBCC;
254 branchOpcode = PIC16ISD::BTFSC;
255 branchOperand = DAG.getConstant(1,MVT::i8);
259 assert(0 && "Less Than Equal condition code is not handled yet!!");
264 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
265 SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
266 Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand,
267 StatusReg, CmpValue);
272 //===----------------------------------------------------------------------===//
273 // Misc Lower Operation implementation
274 //===----------------------------------------------------------------------===//
276 // LowerGlobalAddress - Create a constant pool entry for global value
277 // and wrap it in a wrapper node.
279 PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
281 MVT::ValueType PtrVT = getPointerTy();
282 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
283 GlobalValue *GV = GSDN->getGlobal();
285 // FIXME: for now only do the ram.
286 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
287 SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
288 CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank);
294 PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG)
296 switch(Op.getNumOperands()) {
298 assert(0 && "Do not know how to return this many arguments!");
302 return SDOperand(); // ret void is legal
307 PIC16TargetLowering::LowerFrameIndex(SDOperand N, SelectionDAG &DAG)
309 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
310 return DAG.getTargetFrameIndex(FIN->getIndex(), MVT::i32);
317 PIC16TargetLowering::LowerLOAD(SDNode *N,
319 DAGCombinerInfo &DCI) const
322 SDOperand TF; //TokenFactor
323 SDOperand OutChains[2];
324 SDOperand Chain = N->getOperand(0);
325 SDOperand Src = N->getOperand(1);
329 // If this load is directly stored, replace the load value with the stored
331 // FIXME: Handle store large -> read small portion.
332 // FIXME: Handle TRUNCSTORE/LOADEXT
333 LoadSDNode *LD = cast<LoadSDNode>(N);
334 SDOperand Ptr = LD->getBasePtr();
335 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
336 if (ISD::isNON_TRUNCStore(Chain.Val)) {
337 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
338 if (PrevST->getBasePtr() == Ptr &&
339 PrevST->getValue().getValueType() == N->getValueType(0))
340 return DCI.CombineTo(N, Chain.getOperand(1), Chain);
344 if (N->getValueType(0) != MVT::i16)
347 SDOperand toWorklist;
348 Outs[0] = DAG.getLoad(MVT::i8, Chain, Src, NULL, 0);
349 toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src,
350 DAG.getConstant(1, MVT::i16));
351 Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
352 // FIXME: Add to worklist may not be needed.
353 // It is meant to merge sequences of add with constant into one.
354 DCI.AddToWorklist(toWorklist.Val);
356 // Create the tokenfactors and carry it on to the build_pair node
357 OutChains[0] = Outs[0].getValue(1);
358 OutChains[1] = Outs[1].getValue(1);
359 TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &OutChains[0], 2);
361 VTList = DAG.getVTList(MVT::i16, MVT::Flag);
362 retVal = DAG.getNode (PIC16ISD::Package, VTList, &Outs[0], 2);
364 DCI.CombineTo (N, retVal, TF);
370 PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
371 DAGCombinerInfo &DCI) const
373 bool changed = false;
375 SDOperand LoOps[3], HiOps[3];
376 SDOperand OutOps[3]; // [0]:left, [1]:right, [2]:carry
381 unsigned AS = 0, ASE = 0, ASC=0;
383 InOp[0] = N->getOperand(0);
384 InOp[1] = N->getOperand(1);
386 switch (N->getOpcode()) {
388 if (InOp[0].getOpcode() == ISD::Constant &&
389 InOp[1].getOpcode() == ISD::Constant) {
390 ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
391 ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
392 return DAG.getConstant(CST0->getValue() + CST1->getValue(), MVT::i16);
404 if (InOp[0].getOpcode() == ISD::Constant &&
405 InOp[1].getOpcode() == ISD::Constant) {
406 ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
407 ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
408 return DAG.getConstant(CST0->getValue() - CST1->getValue(), MVT::i16);
420 assert ((N->getValueType(0) == MVT::i16)
421 && "expecting an MVT::i16 node for lowering");
422 assert ((N->getOperand(0).getValueType() == MVT::i16)
423 && (N->getOperand(1).getValueType() == MVT::i16)
424 && "both inputs to addx/subx:i16 must be i16");
426 for (i = 0; i < 2; i++) {
427 if (InOp[i].getOpcode() == ISD::GlobalAddress) {
428 // We don't want to lower subs/adds with global address yet.
431 else if (InOp[i].getOpcode() == ISD::Constant) {
433 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(InOp[i]);
434 LoOps[i] = DAG.getConstant(CST->getValue() & 0xFF, MVT::i8);
435 HiOps[i] = DAG.getConstant(CST->getValue() >> 8, MVT::i8);
437 else if (InOp[i].getOpcode() == PIC16ISD::Package) {
438 LoOps[i] = InOp[i].getOperand(0);
439 HiOps[i] = InOp[i].getOperand(1);
441 else if (InOp[i].getOpcode() == ISD::LOAD) {
443 // LowerLOAD returns a Package node or it may combine and return
445 SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
447 // So If LowerLOAD returns something other than Package,
448 // then just call ADD again.
449 if (lowered.getOpcode() != PIC16ISD::Package)
450 return LowerADDSUB(N, DAG, DCI);
452 LoOps[i] = lowered.getOperand(0);
453 HiOps[i] = lowered.getOperand(1);
455 else if ((InOp[i].getOpcode() == ISD::ADD) ||
456 (InOp[i].getOpcode() == ISD::ADDE) ||
457 (InOp[i].getOpcode() == ISD::ADDC) ||
458 (InOp[i].getOpcode() == ISD::SUB) ||
459 (InOp[i].getOpcode() == ISD::SUBE) ||
460 (InOp[i].getOpcode() == ISD::SUBC)) {
462 // Must call LowerADDSUB recursively here,
463 // LowerADDSUB returns a Package node.
464 SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
466 LoOps[i] = lowered.getOperand(0);
467 HiOps[i] = lowered.getOperand(1);
469 else if (InOp[i].getOpcode() == ISD::SIGN_EXTEND) {
470 // FIXME: I am just zero extending. for now.
472 LoOps[i] = InOp[i].getOperand(0);
473 HiOps[i] = DAG.getConstant(0, MVT::i8);
476 DAG.setGraphColor(N, "blue");
478 assert (0 && "not implemented yet");
482 assert (changed && "nothing changed while lowering SUBx/ADDx");
484 VTList = DAG.getVTList(MVT::i8, MVT::Flag);
485 if (N->getOpcode() == ASE) {
486 // We must take in the existing carry
487 // if this node is part of an existing subx/addx sequence.
488 LoOps[2] = N->getOperand(2).getValue(1);
489 as1 = DAG.getNode (ASE, VTList, LoOps, 3);
492 as1 = DAG.getNode (ASC, VTList, LoOps, 2);
494 HiOps[2] = as1.getValue(1);
495 as2 = DAG.getNode (ASE, VTList, HiOps, 3);
496 // We must build a pair that also provides the carry from sube/adde.
499 OutOps[2] = as2.getValue(1);
500 // Breaking an original i16, so lets make the Package also an i16.
501 if (N->getOpcode() == ASE) {
502 VTList = DAG.getVTList(MVT::i16, MVT::Flag);
503 retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 3);
504 DCI.CombineTo (N, retVal, OutOps[2]);
506 else if (N->getOpcode() == ASC) {
507 VTList = DAG.getVTList(MVT::i16, MVT::Flag);
508 retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 2);
509 DCI.CombineTo (N, retVal, OutOps[2]);
511 else if (N->getOpcode() == AS) {
512 VTList = DAG.getVTList(MVT::i16);
513 retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 2);
514 DCI.CombineTo (N, retVal);
521 //===----------------------------------------------------------------------===//
522 // Calling Convention Implementation
523 //===----------------------------------------------------------------------===//
525 #include "PIC16GenCallingConv.inc"
527 //===----------------------------------------------------------------------===//
528 // CALL Calling Convention Implementation
529 //===----------------------------------------------------------------------===//
532 //===----------------------------------------------------------------------===//
533 // FORMAL_ARGUMENTS Calling Convention Implementation
534 //===----------------------------------------------------------------------===//
535 SDOperand PIC16TargetLowering::
536 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
538 SmallVector<SDOperand, 8> ArgValues;
539 SDOperand Root = Op.getOperand(0);
541 // Return the new list of results.
542 // FIXME: Just copy right now.
543 ArgValues.push_back(Root);
545 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), &ArgValues[0],
546 ArgValues.size()).getValue(Op.ResNo);
550 //===----------------------------------------------------------------------===//
551 // Return Value Calling Convention Implementation
552 //===----------------------------------------------------------------------===//
554 //===----------------------------------------------------------------------===//
555 // PIC16 Inline Assembly Support
556 //===----------------------------------------------------------------------===//
558 //===----------------------------------------------------------------------===//
559 // Target Optimization Hooks
560 //===----------------------------------------------------------------------===//
562 SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
563 DAGCombinerInfo &DCI) const
567 SelectionDAG &DAG = DCI.DAG;
569 switch (N->getOpcode()) {
573 case PIC16ISD::Package:
574 DOUT << "==== combining PIC16ISD::Package\n";
579 if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
580 (N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
581 // Do not touch pointer adds.
590 if (N->getValueType(0) == MVT::i16) {
591 SDOperand retVal = LowerADDSUB(N, DAG,DCI);
592 // LowerADDSUB has already combined the result,
593 // so we just return nothing to avoid assertion failure from llvm
594 // if N has been deleted already.
597 else if (N->getValueType(0) == MVT::i8) {
599 for (int i=0; i<2; i++) {
600 if (N->getOperand (i).getOpcode() == PIC16ISD::Package) {
602 "don't want to have PIC16ISD::Package as intput to add:i8");
608 // FIXME: split this large chunk of code.
611 SDOperand Chain = N->getOperand(0);
612 SDOperand Src = N->getOperand(1);
613 SDOperand Dest = N->getOperand(2);
614 unsigned int DstOff = 0;
618 // if source operand is expected to be extended to
619 // some higher type then - remove this extension
620 // SDNode and do the extension manually
621 if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
622 (Src.getOpcode() == ISD::SIGN_EXTEND) ||
623 (Src.getOpcode() == ISD::ZERO_EXTEND)) {
624 Src = Src.Val->getOperand(0);
625 Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
629 switch(Src.getValueType()) {
646 if (isa<GlobalAddressSDNode>(Dest) && isa<LoadSDNode>(Src) &&
647 (Src.getValueType() != MVT::i8)) {
648 //create direct addressing a = b
649 Chain = Src.getOperand(0);
650 for (i=0; i<NUM_STORES; i++) {
651 SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
652 DAG.getConstant(DstOff, MVT::i16));
653 SDOperand LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
654 SDOperand DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
655 DAG.getConstant(DstOff, MVT::i16));
656 Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0);
661 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
664 else if (isa<GlobalAddressSDNode>(Dest) && isa<ConstantSDNode>(Src)
665 && (Src.getValueType() != MVT::i8)) {
666 //create direct addressing a = CONST
667 CST = dyn_cast<ConstantSDNode>(Src);
668 for (i = 0; i < NUM_STORES; i++) {
669 SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
670 SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
671 DAG.getConstant(DstOff, MVT::i16));
672 Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0);
677 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
680 else if (isa<LoadSDNode>(Dest) && isa<ConstantSDNode>(Src)
681 && (Src.getValueType() != MVT::i8)) {
682 // Create indirect addressing.
683 CST = dyn_cast<ConstantSDNode>(Src);
684 Chain = Dest.getOperand(0);
686 Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0);
687 Chain = Load.getValue(1);
688 for (i=0; i<NUM_STORES; i++) {
689 SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
690 Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0);
695 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
698 else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) {
699 // GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src);
702 else if (Src.getOpcode() == PIC16ISD::Package) {
703 StoreSDNode *st = dyn_cast<StoreSDNode>(N);
704 SDOperand toWorkList, retVal;
705 Chain = N->getOperand(0);
707 if (st->isTruncatingStore()) {
708 retVal = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
711 toWorkList = DAG.getNode(ISD::ADD, MVT::i16, Dest,
712 DAG.getConstant(1, MVT::i16));
713 Stores[1] = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
714 Stores[0] = DAG.getStore(Chain, Src.getOperand(1), toWorkList, NULL,
717 // We want to merge sequence of add with constant to one add and a
718 // constant, so add the ADD node to worklist to have llvm do that
720 DCI.AddToWorklist(toWorkList.Val);
722 // We don't need the Package so add to worklist so llvm deletes it
723 DCI.AddToWorklist(Src.Val);
724 retVal = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 2);
729 else if (Src.getOpcode() == ISD::TRUNCATE) {
738 SDOperand Ptr = N->getOperand(1);
739 if (Ptr.getOpcode() == PIC16ISD::Package) {
740 assert (0 && "not implemented yet");
749 //===----------------------------------------------------------------------===//
751 //===----------------------------------------------------------------------===//
752 const SDOperand *PIC16TargetLowering::
753 findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const
756 if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8))
758 for (i=0; i<Src.getNumOperands(); i++) {
759 const SDOperand *retVal = findLoadi8(Src.getOperand(i),DAG);
760 if (retVal) return retVal;