2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
15 #include "PIC16ABINames.h"
16 #include "PIC16ISelLowering.h"
17 #include "PIC16TargetObjectFile.h"
18 #include "PIC16TargetMachine.h"
19 #include "PIC16MachineFunctionInfo.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/Function.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Support/ErrorHandling.h"
34 static const char *getIntrinsicName(unsigned opcode) {
37 default: llvm_unreachable("do not know intrinsic name");
38 // Arithmetic Right shift for integer types.
39 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
40 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
41 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
43 // Left shift for integer types.
44 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
45 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
46 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
48 // Logical Right Shift for integer types.
49 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
50 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
51 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
53 // Multiply for integer types.
54 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
55 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
56 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
58 // Signed division for integers.
59 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
60 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
62 // Unsigned division for integers.
63 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
64 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
66 // Signed Modulas for integers.
67 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
68 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
70 // Unsigned Modulas for integers.
71 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
72 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
74 //////////////////////
75 // LIBCALLS FOR FLOATS
76 //////////////////////
78 // Float to signed integrals
79 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
80 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
81 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
83 // Signed integrals to float. char and int are first sign extended to i32
84 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
85 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
87 // Float to Unsigned conversions.
88 // Signed conversion can be used for unsigned conversion as well.
89 // In signed and unsigned versions only the interpretation of the
90 // MSB is different. Bit representation remains the same.
91 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
92 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
93 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
95 // Unsigned to Float conversions. char and int are first zero extended
96 // before being converted to float.
97 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
99 // Floating point add, sub, mul, div.
100 case RTLIB::ADD_F32: Basename = "add.f32"; break;
101 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
102 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
103 case RTLIB::DIV_F32: Basename = "div.f32"; break;
105 // Floating point comparison
106 case RTLIB::O_F32: Basename = "unordered.f32"; break;
107 case RTLIB::UO_F32: Basename = "unordered.f32"; break;
108 case RTLIB::OLE_F32: Basename = "le.f32"; break;
109 case RTLIB::OGE_F32: Basename = "ge.f32"; break;
110 case RTLIB::OLT_F32: Basename = "lt.f32"; break;
111 case RTLIB::OGT_F32: Basename = "gt.f32"; break;
112 case RTLIB::OEQ_F32: Basename = "eq.f32"; break;
113 case RTLIB::UNE_F32: Basename = "neq.f32"; break;
116 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
117 std::string tagname = PAN::getTagName(PAN::LIBCALL);
118 std::string Fullname = prefix + tagname + Basename;
120 // The name has to live through program life.
121 return ESNames::createESName(Fullname);
124 // getStdLibCallName - Get the name for the standard library function.
125 static const char *getStdLibCallName(unsigned opcode) {
126 std::string BaseName;
128 case RTLIB::COS_F32: BaseName = "cos";
130 case RTLIB::SIN_F32: BaseName = "sin";
132 case RTLIB::MEMCPY: BaseName = "memcpy";
134 case RTLIB::MEMSET: BaseName = "memset";
136 case RTLIB::MEMMOVE: BaseName = "memmove";
138 default: llvm_unreachable("do not know std lib call name");
140 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
141 std::string LibCallName = prefix + BaseName;
143 // The name has to live through program life.
144 return ESNames::createESName(LibCallName);
147 // PIC16TargetLowering Constructor.
148 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
149 : TargetLowering(TM, new PIC16TargetObjectFile()) {
151 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
153 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
155 setShiftAmountType(MVT::i8);
157 // Std lib call names
158 setLibcallName(RTLIB::COS_F32, getStdLibCallName(RTLIB::COS_F32));
159 setLibcallName(RTLIB::SIN_F32, getStdLibCallName(RTLIB::SIN_F32));
160 setLibcallName(RTLIB::MEMCPY, getStdLibCallName(RTLIB::MEMCPY));
161 setLibcallName(RTLIB::MEMSET, getStdLibCallName(RTLIB::MEMSET));
162 setLibcallName(RTLIB::MEMMOVE, getStdLibCallName(RTLIB::MEMMOVE));
164 // SRA library call names
165 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
166 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
167 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
169 // SHL library call names
170 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
171 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
172 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
174 // SRL library call names
175 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
176 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
177 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
179 // MUL Library call names
180 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
181 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
182 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
184 // Signed division lib call names
185 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
186 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
188 // Unsigned division lib call names
189 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
190 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
192 // Signed remainder lib call names
193 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
194 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
196 // Unsigned remainder lib call names
197 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
198 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
200 // Floating point to signed int conversions.
201 setLibcallName(RTLIB::FPTOSINT_F32_I8,
202 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
203 setLibcallName(RTLIB::FPTOSINT_F32_I16,
204 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
205 setLibcallName(RTLIB::FPTOSINT_F32_I32,
206 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
208 // Signed int to floats.
209 setLibcallName(RTLIB::SINTTOFP_I32_F32,
210 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
212 // Floating points to unsigned ints.
213 setLibcallName(RTLIB::FPTOUINT_F32_I8,
214 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
215 setLibcallName(RTLIB::FPTOUINT_F32_I16,
216 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
217 setLibcallName(RTLIB::FPTOUINT_F32_I32,
218 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
220 // Unsigned int to floats.
221 setLibcallName(RTLIB::UINTTOFP_I32_F32,
222 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
224 // Floating point add, sub, mul ,div.
225 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
226 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
227 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
228 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
230 // Floationg point comparison
231 setLibcallName(RTLIB::O_F32, getIntrinsicName(RTLIB::O_F32));
232 setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32));
233 setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32));
234 setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32));
235 setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32));
236 setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32));
237 setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32));
238 setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32));
240 // Return value comparisons of floating point calls.
241 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
242 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
243 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
244 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
245 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
246 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
247 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
248 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
250 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
251 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
253 setOperationAction(ISD::LOAD, MVT::i8, Legal);
254 setOperationAction(ISD::LOAD, MVT::i16, Custom);
255 setOperationAction(ISD::LOAD, MVT::i32, Custom);
257 setOperationAction(ISD::STORE, MVT::i8, Legal);
258 setOperationAction(ISD::STORE, MVT::i16, Custom);
259 setOperationAction(ISD::STORE, MVT::i32, Custom);
260 setOperationAction(ISD::STORE, MVT::i64, Custom);
262 setOperationAction(ISD::ADDE, MVT::i8, Custom);
263 setOperationAction(ISD::ADDC, MVT::i8, Custom);
264 setOperationAction(ISD::SUBE, MVT::i8, Custom);
265 setOperationAction(ISD::SUBC, MVT::i8, Custom);
266 setOperationAction(ISD::SUB, MVT::i8, Custom);
267 setOperationAction(ISD::ADD, MVT::i8, Custom);
268 setOperationAction(ISD::ADD, MVT::i16, Custom);
270 setOperationAction(ISD::OR, MVT::i8, Custom);
271 setOperationAction(ISD::AND, MVT::i8, Custom);
272 setOperationAction(ISD::XOR, MVT::i8, Custom);
274 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
276 setOperationAction(ISD::MUL, MVT::i8, Custom);
278 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
279 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
280 setOperationAction(ISD::MULHU, MVT::i8, Expand);
281 setOperationAction(ISD::MULHS, MVT::i8, Expand);
283 setOperationAction(ISD::SRA, MVT::i8, Custom);
284 setOperationAction(ISD::SHL, MVT::i8, Custom);
285 setOperationAction(ISD::SRL, MVT::i8, Custom);
287 setOperationAction(ISD::ROTL, MVT::i8, Expand);
288 setOperationAction(ISD::ROTR, MVT::i8, Expand);
290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
292 // PIC16 does not support shift parts
293 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
294 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
295 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
298 // PIC16 does not have a SETCC, expand it to SELECT_CC.
299 setOperationAction(ISD::SETCC, MVT::i8, Expand);
300 setOperationAction(ISD::SELECT, MVT::i8, Expand);
301 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
302 setOperationAction(ISD::BRIND, MVT::Other, Expand);
304 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
305 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
307 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
308 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
310 // Now deduce the information based on the above mentioned
312 computeRegisterProperties();
315 std::pair<const TargetRegisterClass*, uint8_t>
316 PIC16TargetLowering::findRepresentativeClass(EVT VT) const {
317 switch (VT.getSimpleVT().SimpleTy) {
319 return TargetLowering::findRepresentativeClass(VT);
321 return std::make_pair(PIC16::FSR16RegisterClass, 1);
325 // getOutFlag - Extract the flag result if the Op has it.
326 static SDValue getOutFlag(SDValue &Op) {
327 // Flag is the last value of the node.
328 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
330 assert (Flag.getValueType() == MVT::Flag
331 && "Node does not have an out Flag");
335 // Get the TmpOffset for FrameIndex
336 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size,
337 MachineFunction &MF) const {
338 PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>();
339 std::map<unsigned, unsigned> &FiTmpOffsetMap = FuncInfo->getFiTmpOffsetMap();
341 std::map<unsigned, unsigned>::iterator
342 MapIt = FiTmpOffsetMap.find(FI);
343 if (MapIt != FiTmpOffsetMap.end())
344 return MapIt->second;
346 // This FI (FrameIndex) is not yet mapped, so map it
347 FiTmpOffsetMap[FI] = FuncInfo->getTmpSize();
348 FuncInfo->setTmpSize(FuncInfo->getTmpSize() + size);
349 return FiTmpOffsetMap[FI];
352 void PIC16TargetLowering::ResetTmpOffsetMap(SelectionDAG &DAG) const {
353 MachineFunction &MF = DAG.getMachineFunction();
354 PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>();
355 FuncInfo->getFiTmpOffsetMap().clear();
356 FuncInfo->setTmpSize(0);
359 // To extract chain value from the SDValue Nodes
360 // This function will help to maintain the chain extracting
361 // code at one place. In case of any change in future it will
362 // help maintain the code.
363 static SDValue getChain(SDValue &Op) {
364 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
366 // If the last value returned in Flag then the chain is
367 // second last value returned.
368 if (Chain.getValueType() == MVT::Flag)
369 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
371 // All nodes may not produce a chain. Therefore following assert
372 // verifies that the node is returning a chain only.
373 assert (Chain.getValueType() == MVT::Other
374 && "Node does not have a chain");
379 /// PopulateResults - Helper function to LowerOperation.
380 /// If a node wants to return multiple results after lowering,
381 /// it stuffs them into an array of SDValue called Results.
383 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
384 if (N.getOpcode() == ISD::MERGE_VALUES) {
385 int NumResults = N.getNumOperands();
386 for( int i = 0; i < NumResults; i++)
387 Results.push_back(N.getOperand(i));
390 Results.push_back(N);
394 PIC16TargetLowering::getSetCCResultType(EVT ValType) const {
399 PIC16TargetLowering::getCmpLibcallReturnType() const {
403 /// The type legalizer framework of generating legalizer can generate libcalls
404 /// only when the operand/result types are illegal.
405 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
406 /// For example an arithmetic right shift. These functions are used to lower
407 /// such operations that generate libcall for legal types.
410 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
412 PIC16LibcallNames[Call] = Name;
416 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) const {
417 return PIC16LibcallNames[Call];
421 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
422 EVT RetVT, const SDValue *Ops,
423 unsigned NumOps, bool isSigned,
424 SelectionDAG &DAG, DebugLoc dl) const {
426 TargetLowering::ArgListTy Args;
427 Args.reserve(NumOps);
429 TargetLowering::ArgListEntry Entry;
430 for (unsigned i = 0; i != NumOps; ++i) {
432 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
433 Entry.isSExt = isSigned;
434 Entry.isZExt = !isSigned;
435 Args.push_back(Entry);
438 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16);
440 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
441 std::pair<SDValue,SDValue> CallInfo =
442 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
443 false, 0, CallingConv::C, false,
444 /*isReturnValueUsed=*/true,
445 Callee, Args, DAG, dl);
447 return CallInfo.first;
450 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
452 default: return NULL;
453 case PIC16ISD::Lo: return "PIC16ISD::Lo";
454 case PIC16ISD::Hi: return "PIC16ISD::Hi";
455 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
456 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
457 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
458 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
459 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
460 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
461 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
462 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
463 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
464 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
465 case PIC16ISD::BCF: return "PIC16ISD::BCF";
466 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
467 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
468 case PIC16ISD::RLF: return "PIC16ISD::RLF";
469 case PIC16ISD::RRF: return "PIC16ISD::RRF";
470 case PIC16ISD::CALL: return "PIC16ISD::CALL";
471 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
472 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
473 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
474 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
475 case PIC16ISD::RET: return "PIC16ISD::RET";
476 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
480 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
481 SmallVectorImpl<SDValue>&Results,
482 SelectionDAG &DAG) const {
484 switch (N->getOpcode()) {
485 case ISD::GlobalAddress:
486 Results.push_back(ExpandGlobalAddress(N, DAG));
488 case ISD::ExternalSymbol:
489 Results.push_back(ExpandExternalSymbol(N, DAG));
492 Results.push_back(ExpandStore(N, DAG));
495 PopulateResults(ExpandLoad(N, DAG), Results);
498 // Results.push_back(ExpandAdd(N, DAG));
500 case ISD::FrameIndex:
501 Results.push_back(ExpandFrameIndex(N, DAG));
504 assert (0 && "not implemented");
509 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N,
510 SelectionDAG &DAG) const {
512 // Currently handling FrameIndex of size MVT::i16 only
513 // One example of this scenario is when return value is written on
516 if (N->getValueType(0) != MVT::i16)
519 // Expand the FrameIndex into ExternalSymbol and a Constant node
520 // The constant will represent the frame index number
521 // Get the current function frame
522 MachineFunction &MF = DAG.getMachineFunction();
523 const Function *Func = MF.getFunction();
524 const std::string Name = Func->getName();
526 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
527 // FIXME there isn't really debug info here
528 DebugLoc dl = FR->getDebugLoc();
530 // Expand FrameIndex like GlobalAddress and ExternalSymbol
531 // Also use Offset field for lo and hi parts. The default
536 SDValue FI = SDValue(N,0);
537 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
538 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
539 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
540 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
541 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
545 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) const {
546 StoreSDNode *St = cast<StoreSDNode>(N);
547 SDValue Chain = St->getChain();
548 SDValue Src = St->getValue();
549 SDValue Ptr = St->getBasePtr();
550 EVT ValueType = Src.getValueType();
551 unsigned StoreOffset = 0;
552 DebugLoc dl = N->getDebugLoc();
554 SDValue PtrLo, PtrHi;
555 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
557 if (ValueType == MVT::i8) {
558 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
560 DAG.getConstant (0 + StoreOffset, MVT::i8));
562 else if (ValueType == MVT::i16) {
563 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
564 SDValue SrcLo, SrcHi;
565 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
566 SDValue ChainLo = Chain, ChainHi = Chain;
567 // FIXME: This makes unsafe assumptions. The Chain may be a TokenFactor
568 // created for an unrelated purpose, in which case it may not have
569 // exactly two operands. Also, even if it does have two operands, they
570 // may not be the low and high parts of an aligned load that was split.
571 if (Chain.getOpcode() == ISD::TokenFactor) {
572 ChainLo = Chain.getOperand(0);
573 ChainHi = Chain.getOperand(1);
575 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
578 DAG.getConstant (0 + StoreOffset, MVT::i8));
580 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
582 DAG.getConstant (1 + StoreOffset, MVT::i8));
584 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
587 else if (ValueType == MVT::i32) {
588 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
589 SDValue SrcLo, SrcHi;
590 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
592 // Get the expanded parts of each of SrcLo and SrcHi.
593 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
594 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
595 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
597 SDValue ChainLo = Chain, ChainHi = Chain;
598 // FIXME: This makes unsafe assumptions; see the FIXME above.
599 if (Chain.getOpcode() == ISD::TokenFactor) {
600 ChainLo = Chain.getOperand(0);
601 ChainHi = Chain.getOperand(1);
603 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
605 // FIXME: This makes unsafe assumptions; see the FIXME above.
606 if (ChainLo.getOpcode() == ISD::TokenFactor) {
607 ChainLo1 = ChainLo.getOperand(0);
608 ChainLo2 = ChainLo.getOperand(1);
610 // FIXME: This makes unsafe assumptions; see the FIXME above.
611 if (ChainHi.getOpcode() == ISD::TokenFactor) {
612 ChainHi1 = ChainHi.getOperand(0);
613 ChainHi2 = ChainHi.getOperand(1);
615 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
617 SrcLo1, PtrLo, PtrHi,
618 DAG.getConstant (0 + StoreOffset, MVT::i8));
620 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
621 SrcLo2, PtrLo, PtrHi,
622 DAG.getConstant (1 + StoreOffset, MVT::i8));
624 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
625 SrcHi1, PtrLo, PtrHi,
626 DAG.getConstant (2 + StoreOffset, MVT::i8));
628 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
629 SrcHi2, PtrLo, PtrHi,
630 DAG.getConstant (3 + StoreOffset, MVT::i8));
632 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
633 getChain(Store1), getChain(Store2));
634 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
635 getChain(Store3), getChain(Store4));
636 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
638 } else if (ValueType == MVT::i64) {
639 SDValue SrcLo, SrcHi;
640 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
641 SDValue ChainLo = Chain, ChainHi = Chain;
642 // FIXME: This makes unsafe assumptions; see the FIXME above.
643 if (Chain.getOpcode() == ISD::TokenFactor) {
644 ChainLo = Chain.getOperand(0);
645 ChainHi = Chain.getOperand(1);
647 SDValue Store1 = DAG.getStore(ChainLo, dl, SrcLo, Ptr, NULL,
648 0 + StoreOffset, false, false, 0);
650 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
651 DAG.getConstant(4, Ptr.getValueType()));
652 SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, NULL,
653 1 + StoreOffset, false, false, 0);
655 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1,
658 assert (0 && "value type not supported");
663 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N,
666 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
667 // FIXME there isn't really debug info here
668 DebugLoc dl = ES->getDebugLoc();
670 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
671 SDValue Offset = DAG.getConstant(0, MVT::i8);
672 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
673 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
675 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
678 // ExpandGlobalAddress -
679 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N,
680 SelectionDAG &DAG) const {
681 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
682 // FIXME there isn't really debug info here
683 DebugLoc dl = G->getDebugLoc();
685 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), N->getDebugLoc(),
689 SDValue Offset = DAG.getConstant(0, MVT::i8);
690 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
691 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
693 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
696 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) const {
697 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
699 if (Op.getOpcode() == ISD::BUILD_PAIR) {
700 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
706 // Return true if DirectAddress is in ROM_SPACE
707 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) const {
709 // RomAddress is a GlobalAddress in ROM_SPACE_
710 // If the Op is not a GlobalAddress return NULL without checking
712 if (!isDirectAddress(Op))
715 // Its a GlobalAddress.
716 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
717 SDValue TGA = Op.getOperand(0).getOperand(0);
718 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
720 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
723 // Any other address space return it false
728 // GetExpandedParts - This function is on the similiar lines as
729 // the GetExpandedInteger in type legalizer is. This returns expanded
730 // parts of Op in Lo and Hi.
732 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
733 SDValue &Lo, SDValue &Hi) const {
734 SDNode *N = Op.getNode();
735 DebugLoc dl = N->getDebugLoc();
736 EVT NewVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
738 // Extract the lo component.
739 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
740 DAG.getConstant(0, MVT::i8));
742 // extract the hi component
743 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
744 DAG.getConstant(1, MVT::i8));
747 // Legalize FrameIndex into ExternalSymbol and offset.
749 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
750 SDValue &ES, int &Offset) const {
752 MachineFunction &MF = DAG.getMachineFunction();
753 const Function *Func = MF.getFunction();
754 MachineFrameInfo *MFI = MF.getFrameInfo();
755 PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>();
756 const std::string Name = Func->getName();
758 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
760 // FrameIndices are not stack offsets. But they represent the request
761 // for space on stack. That space requested may be more than one byte.
762 // Therefore, to calculate the stack offset that a FrameIndex aligns
763 // with, we need to traverse all the FrameIndices available earlier in
764 // the list and add their requested size.
765 unsigned FIndex = FR->getIndex();
767 if (FIndex < FuncInfo->getReservedFrameCount()) {
768 tmpName = ESNames::createESName(PAN::getFrameLabel(Name));
769 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
771 for (unsigned i=0; i<FIndex ; ++i) {
772 Offset += MFI->getObjectSize(i);
775 // FrameIndex has been made for some temporary storage
776 tmpName = ESNames::createESName(PAN::getTempdataLabel(Name));
777 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
778 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex), MF);
784 // This function legalizes the PIC16 Addresses. If the Pointer is
785 // -- Direct address variable residing
786 // --> then a Banksel for that variable will be created.
788 // --> then it will be treated as an indirect address.
789 // -- Indirect address
790 // --> then the address will be loaded into FSR
791 // -- ADD with constant operand
792 // --> then constant operand of ADD will be returned as Offset
793 // and non-constant operand of ADD will be treated as pointer.
794 // Returns the high and lo part of the address, and the offset(in case of ADD).
796 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
797 SDValue &Lo, SDValue &Hi,
798 unsigned &Offset, DebugLoc dl) const {
800 // Offset, by default, should be 0
803 // If the pointer is ADD with constant,
804 // return the constant value as the offset
805 if (Ptr.getOpcode() == ISD::ADD) {
806 SDValue OperLeft = Ptr.getOperand(0);
807 SDValue OperRight = Ptr.getOperand(1);
808 if ((OperLeft.getOpcode() == ISD::Constant) &&
809 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
810 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
812 } else if ((OperRight.getOpcode() == ISD::Constant) &&
813 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
814 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
819 // If the pointer is Type i8 and an external symbol
820 // then treat it as direct address.
821 // One example for such case is storing and loading
822 // from function frame during a call
823 if (Ptr.getValueType() == MVT::i8) {
824 switch (Ptr.getOpcode()) {
825 case ISD::TargetExternalSymbol:
827 Hi = DAG.getConstant(1, MVT::i8);
832 // Expansion of FrameIndex has Lo/Hi parts
833 if (isDirectAddress(Ptr)) {
834 SDValue TFI = Ptr.getOperand(0).getOperand(0);
836 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
837 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
838 Hi = DAG.getConstant(1, MVT::i8);
839 Offset += FrameOffset;
841 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
842 // FrameIndex has already been expanded.
843 // Now just make use of its expansion
845 Hi = DAG.getConstant(1, MVT::i8);
846 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
847 assert (FOffset.getOpcode() == ISD::Constant &&
848 "Invalid operand of PIC16ISD::Lo");
849 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
854 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
855 // Direct addressing case for RAM variables. The Hi part is constant
856 // and the Lo part is the TGA itself.
857 Lo = Ptr.getOperand(0).getOperand(0);
859 // For direct addresses Hi is a constant. Value 1 for the constant
860 // signifies that banksel needs to generated for it. Value 0 for
861 // the constant signifies that banksel does not need to be generated
862 // for it. Mark it as 1 now and optimize later.
863 Hi = DAG.getConstant(1, MVT::i8);
867 // Indirect addresses. Get the hi and lo parts of ptr.
868 GetExpandedParts(Ptr, DAG, Lo, Hi);
870 // Put the hi and lo parts into FSR.
871 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
872 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
877 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) const {
878 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
879 SDValue Chain = LD->getChain();
880 SDValue Ptr = LD->getBasePtr();
881 DebugLoc dl = LD->getDebugLoc();
883 SDValue Load, Offset;
886 SDValue PtrLo, PtrHi;
889 // Legalize direct/indirect addresses. This will give the lo and hi parts
890 // of the address and the offset.
891 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
893 // Load from the pointer (direct address or FSR)
894 VT = N->getValueType(0);
895 unsigned NumLoads = VT.getSizeInBits() / 8;
896 std::vector<SDValue> PICLoads;
898 EVT MemVT = LD->getMemoryVT();
899 if(ISD::isNON_EXTLoad(N)) {
900 for (iter=0; iter<NumLoads ; ++iter) {
901 // Add the pointer offset if any
902 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
903 Tys = DAG.getVTList(MVT::i8, MVT::Other);
904 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
906 PICLoads.push_back(Load);
909 // If it is extended load then use PIC16Load for Memory Bytes
910 // and for all extended bytes perform action based on type of
911 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
914 // For extended loads this is the memory value type
915 // i.e. without any extension
916 EVT MemVT = LD->getMemoryVT();
917 unsigned MemBytes = MemVT.getSizeInBits() / 8;
918 // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
920 if (MemBytes == 0) MemBytes = 1;
922 unsigned ExtdBytes = VT.getSizeInBits() / 8;
923 Offset = DAG.getConstant(LoadOffset, MVT::i8);
925 Tys = DAG.getVTList(MVT::i8, MVT::Other);
926 // For MemBytes generate PIC16Load with proper offset
927 for (iter=0; iter < MemBytes; ++iter) {
928 // Add the pointer offset if any
929 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
930 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
932 PICLoads.push_back(Load);
935 // For SignExtendedLoad
936 if (ISD::isSEXTLoad(N)) {
937 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
939 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
940 DAG.getConstant(7, MVT::i8));
941 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
942 PICLoads.push_back(SRA);
944 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
945 //} else if (ISD::isZEXTLoad(N)) {
946 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
947 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
948 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
949 PICLoads.push_back(ConstZero);
956 // Operand of Load is illegal -- Load itself is legal
959 else if (VT == MVT::i16) {
960 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
961 if ((MemVT == MVT::i8) || (MemVT == MVT::i1))
962 Chain = getChain(PICLoads[0]);
964 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
965 getChain(PICLoads[0]), getChain(PICLoads[1]));
966 } else if (VT == MVT::i32) {
968 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
969 PICLoads[0], PICLoads[1]);
970 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
971 PICLoads[2], PICLoads[3]);
972 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
973 if ((MemVT == MVT::i8) || (MemVT == MVT::i1))
974 Chain = getChain(PICLoads[0]);
975 else if (MemVT == MVT::i16)
976 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
977 getChain(PICLoads[0]), getChain(PICLoads[1]));
980 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
981 getChain(PICLoads[0]), getChain(PICLoads[1]));
982 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
983 getChain(PICLoads[2]), getChain(PICLoads[3]));
984 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
985 Chains[0], Chains[1]);
988 Tys = DAG.getVTList(VT, MVT::Other);
989 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
992 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
993 // We should have handled larger operands in type legalizer itself.
994 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
996 SDNode *N = Op.getNode();
997 SDValue Value = N->getOperand(0);
998 SDValue Amt = N->getOperand(1);
999 PIC16ISD::PIC16Libcall CallCode;
1000 switch (N->getOpcode()) {
1002 CallCode = PIC16ISD::SRA_I8;
1005 CallCode = PIC16ISD::SLL_I8;
1008 CallCode = PIC16ISD::SRL_I8;
1011 assert ( 0 && "This shift is not implemented yet.");
1014 SmallVector<SDValue, 2> Ops(2);
1017 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
1018 true, DAG, N->getDebugLoc());
1022 SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
1023 // We should have handled larger operands in type legalizer itself.
1024 assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
1026 SDNode *N = Op.getNode();
1027 SmallVector<SDValue, 2> Ops(2);
1028 Ops[0] = N->getOperand(0);
1029 Ops[1] = N->getOperand(1);
1030 SDValue Call = MakePIC16Libcall(PIC16ISD::MUL_I8, N->getValueType(0),
1031 &Ops[0], 2, true, DAG, N->getDebugLoc());
1036 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
1037 SmallVectorImpl<SDValue>&Results,
1038 SelectionDAG &DAG) const {
1039 SDValue Op = SDValue(N, 0);
1042 switch (Op.getOpcode()) {
1044 Res = ExpandLoad(Op.getNode(), DAG); break;
1046 // All other operations are handled in LowerOperation.
1047 Res = LowerOperation(Op, DAG);
1049 Results.push_back(Res);
1056 unsigned NumValues = N->getNumValues();
1057 for (i = 0; i < NumValues ; i++) {
1058 Results.push_back(SDValue(N, i));
1062 SDValue PIC16TargetLowering::LowerOperation(SDValue Op,
1063 SelectionDAG &DAG) const {
1064 switch (Op.getOpcode()) {
1068 return LowerADD(Op, DAG);
1072 return LowerSUB(Op, DAG);
1074 return ExpandLoad(Op.getNode(), DAG);
1076 return ExpandStore(Op.getNode(), DAG);
1078 return LowerMUL(Op, DAG);
1082 return LowerShift(Op, DAG);
1086 return LowerBinOp(Op, DAG);
1088 return LowerBR_CC(Op, DAG);
1089 case ISD::SELECT_CC:
1090 return LowerSELECT_CC(Op, DAG);
1095 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
1097 DebugLoc dl) const {
1098 assert (Op.getValueType() == MVT::i8
1099 && "illegal value type to store on stack.");
1101 MachineFunction &MF = DAG.getMachineFunction();
1102 const Function *Func = MF.getFunction();
1103 const std::string FuncName = Func->getName();
1106 // Put the value on stack.
1107 // Get a stack slot index and convert to es.
1108 int FI = MF.getFrameInfo()->CreateStackObject(1, 1, false);
1109 const char *tmpName = ESNames::createESName(PAN::getTempdataLabel(FuncName));
1110 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1112 // Store the value to ES.
1113 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1116 DAG.getConstant (1, MVT::i8), // Banksel.
1117 DAG.getConstant (GetTmpOffsetForFI(FI, 1, MF),
1120 // Load the value from ES.
1121 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1122 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1123 ES, DAG.getConstant (1, MVT::i8),
1124 DAG.getConstant (GetTmpOffsetForFI(FI, 1, MF),
1127 return Load.getValue(0);
1130 SDValue PIC16TargetLowering::
1131 LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
1132 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1133 const SmallVectorImpl<ISD::OutputArg> &Outs,
1134 const SmallVectorImpl<SDValue> &OutVals,
1135 const SmallVectorImpl<ISD::InputArg> &Ins,
1136 DebugLoc dl, SelectionDAG &DAG) const {
1137 unsigned NumOps = Outs.size();
1139 // If call has no arguments then do nothing and return.
1143 std::vector<SDValue> Ops;
1144 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1145 SDValue Arg, StoreRet;
1147 // For PIC16 ABI the arguments come after the return value.
1148 unsigned RetVals = Ins.size();
1149 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1150 // Get the arguments
1154 Ops.push_back(Chain);
1156 Ops.push_back(DataAddr_Lo);
1157 Ops.push_back(DataAddr_Hi);
1158 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1159 Ops.push_back(InFlag);
1161 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1163 Chain = getChain(StoreRet);
1164 InFlag = getOutFlag(StoreRet);
1170 SDValue PIC16TargetLowering::
1171 LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
1172 const SmallVectorImpl<ISD::OutputArg> &Outs,
1173 const SmallVectorImpl<SDValue> &OutVals,
1174 DebugLoc dl, SelectionDAG &DAG) const {
1175 unsigned NumOps = Outs.size();
1177 SDValue Arg, StoreAt;
1181 // If call has no arguments then do nothing and return.
1185 // FIXME: This portion of code currently assumes only
1186 // primitive types being passed as arguments.
1188 // Legalize the address before use
1189 SDValue PtrLo, PtrHi;
1190 unsigned AddressOffset;
1191 int StoreOffset = 0;
1192 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1195 std::vector<SDValue> Ops;
1196 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1197 for (unsigned i=0, Offset = 0; i<NumOps; i++) {
1200 StoreOffset = (Offset + AddressOffset);
1202 // Store the argument on frame
1205 Ops.push_back(Chain);
1207 Ops.push_back(PtrLo);
1208 Ops.push_back(PtrHi);
1209 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1210 Ops.push_back(InFlag);
1212 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1214 Chain = getChain(StoreRet);
1215 InFlag = getOutFlag(StoreRet);
1217 // Update the frame offset to be used for next argument
1218 ArgVT = Arg.getValueType();
1219 Size = ArgVT.getSizeInBits();
1220 Size = Size/8; // Calculate size in bytes
1221 Offset += Size; // Increase the frame offset
1226 SDValue PIC16TargetLowering::
1227 LowerIndirectCallReturn(SDValue Chain, SDValue InFlag,
1228 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1229 const SmallVectorImpl<ISD::InputArg> &Ins,
1230 DebugLoc dl, SelectionDAG &DAG,
1231 SmallVectorImpl<SDValue> &InVals) const {
1232 unsigned RetVals = Ins.size();
1234 // If call does not have anything to return
1235 // then do nothing and go back.
1239 // Call has something to return
1242 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1243 for(unsigned i=0;i<RetVals;i++) {
1244 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1245 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1247 InFlag = getOutFlag(LoadRet);
1248 Chain = getChain(LoadRet);
1249 InVals.push_back(LoadRet);
1254 SDValue PIC16TargetLowering::
1255 LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag,
1256 const SmallVectorImpl<ISD::InputArg> &Ins,
1257 DebugLoc dl, SelectionDAG &DAG,
1258 SmallVectorImpl<SDValue> &InVals) const {
1260 // Currently handling primitive types only. They will come in
1262 unsigned RetVals = Ins.size();
1264 // Return immediately if the return type is void
1268 // Call has something to return
1270 // Legalize the address before use
1273 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1275 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1278 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1280 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1281 DAG.getConstant(LdOffset + Offset, MVT::i8),
1284 InFlag = getOutFlag(LoadRet);
1286 Chain = getChain(LoadRet);
1288 InVals.push_back(LoadRet);
1295 PIC16TargetLowering::LowerReturn(SDValue Chain,
1296 CallingConv::ID CallConv, bool isVarArg,
1297 const SmallVectorImpl<ISD::OutputArg> &Outs,
1298 const SmallVectorImpl<SDValue> &OutVals,
1299 DebugLoc dl, SelectionDAG &DAG) const {
1301 // Number of values to return
1302 unsigned NumRet = Outs.size();
1304 // Function returns value always on stack with the offset starting
1306 MachineFunction &MF = DAG.getMachineFunction();
1307 const Function *F = MF.getFunction();
1308 std::string FuncName = F->getName();
1310 const char *tmpName = ESNames::createESName(PAN::getFrameLabel(FuncName));
1311 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1312 SDValue BS = DAG.getConstant(1, MVT::i8);
1314 for(unsigned i=0;i<NumRet; ++i) {
1315 RetVal = OutVals[i];
1316 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1318 DAG.getConstant (i, MVT::i8));
1321 return DAG.getNode(PIC16ISD::RET, dl, MVT::Other, Chain);
1324 void PIC16TargetLowering::
1325 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1326 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1327 SelectionDAG &DAG) const {
1328 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1329 && "Don't know what to do of such callee!!");
1330 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1331 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1332 Chain = getChain(SeqStart);
1333 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1335 // Get the Lo and Hi part of code address
1336 SDValue Lo = Callee.getOperand(0);
1337 SDValue Hi = Callee.getOperand(1);
1339 SDValue Data_Lo, Data_Hi;
1340 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1341 // Subtract 2 from Address to get the Lower part of DataAddress.
1342 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1343 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1344 DAG.getConstant(2, MVT::i8));
1345 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1346 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1347 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1348 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1349 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1351 Chain = getChain(Call);
1352 OperFlag = getOutFlag(Call);
1353 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1355 Chain = getChain(SeqEnd);
1356 OperFlag = getOutFlag(SeqEnd);
1358 // Low part of Data Address
1359 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1361 // Make the second call.
1362 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1363 Chain = getChain(SeqStart);
1364 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1366 // Subtract 1 from Address to get high part of data address.
1367 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1368 DAG.getConstant(1, MVT::i8));
1369 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1370 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1371 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1373 // Use new Lo to make another CALLW
1374 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1375 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1376 Chain = getChain(Call);
1377 OperFlag = getOutFlag(Call);
1378 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1380 Chain = getChain(SeqEnd);
1381 OperFlag = getOutFlag(SeqEnd);
1382 // Hi part of Data Address
1383 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1387 PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1388 CallingConv::ID CallConv, bool isVarArg,
1390 const SmallVectorImpl<ISD::OutputArg> &Outs,
1391 const SmallVectorImpl<SDValue> &OutVals,
1392 const SmallVectorImpl<ISD::InputArg> &Ins,
1393 DebugLoc dl, SelectionDAG &DAG,
1394 SmallVectorImpl<SDValue> &InVals) const {
1395 // PIC16 target does not yet support tail call optimization.
1398 assert(Callee.getValueType() == MVT::i16 &&
1399 "Don't know how to legalize this call node!!!");
1401 // The flag to track if this is a direct or indirect call.
1402 bool IsDirectCall = true;
1403 unsigned RetVals = Ins.size();
1404 unsigned NumArgs = Outs.size();
1406 SDValue DataAddr_Lo, DataAddr_Hi;
1407 if (!isa<GlobalAddressSDNode>(Callee) &&
1408 !isa<ExternalSymbolSDNode>(Callee)) {
1409 IsDirectCall = false; // This is indirect call
1411 // If this is an indirect call then to pass the arguments
1412 // and read the return value back, we need the data address
1413 // of the function being called.
1414 // To get the data address two more calls need to be made.
1416 // Come here for indirect calls
1418 // Indirect addresses. Get the hi and lo parts of ptr.
1419 GetExpandedParts(Callee, DAG, Lo, Hi);
1420 // Connect Lo and Hi parts of the callee with the PIC16Connect
1421 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1423 // Read DataAddress only if we have to pass arguments or
1424 // read return value.
1425 if ((RetVals > 0) || (NumArgs > 0))
1426 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1429 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1431 // Start the call sequence.
1432 // Carring the Constant 0 along the CALLSEQSTART
1433 // because there is nothing else to carry.
1434 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1435 Chain = getChain(SeqStart);
1436 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1439 // For any direct call - callee will be GlobalAddressNode or
1441 SDValue ArgLabel, RetLabel;
1443 // Considering the GlobalAddressNode case here.
1444 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1445 const GlobalValue *GV = G->getGlobal();
1446 Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i8);
1447 Name = G->getGlobal()->getName();
1448 } else {// Considering the ExternalSymbol case here
1449 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1450 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1451 Name = ES->getSymbol();
1454 // Label for argument passing
1455 const char *argFrame = ESNames::createESName(PAN::getArgsLabel(Name));
1456 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1458 // Label for reading return value
1459 const char *retName = ESNames::createESName(PAN::getRetvalLabel(Name));
1460 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1463 SDValue CodeAddr_Lo = Callee.getOperand(0);
1464 SDValue CodeAddr_Hi = Callee.getOperand(1);
1466 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1467 DAG.getConstant(2, MVT::i8));*/
1469 // move Hi part in PCLATH
1470 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1471 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1475 // Pass the argument to function before making the call.
1478 CallArgs = LowerDirectCallArguments(ArgLabel, Chain, OperFlag,
1479 Outs, OutVals, dl, DAG);
1480 Chain = getChain(CallArgs);
1481 OperFlag = getOutFlag(CallArgs);
1483 CallArgs = LowerIndirectCallArguments(Chain, OperFlag, DataAddr_Lo,
1484 DataAddr_Hi, Outs, OutVals, Ins,
1486 Chain = getChain(CallArgs);
1487 OperFlag = getOutFlag(CallArgs);
1490 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1491 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1493 Chain = getChain(PICCall);
1494 OperFlag = getOutFlag(PICCall);
1497 // Carrying the Constant 0 along the CALLSEQSTART
1498 // because there is nothing else to carry.
1499 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1501 Chain = getChain(SeqEnd);
1502 OperFlag = getOutFlag(SeqEnd);
1504 // Lower the return value reading after the call.
1506 return LowerDirectCallReturn(RetLabel, Chain, OperFlag,
1507 Ins, dl, DAG, InVals);
1509 return LowerIndirectCallReturn(Chain, OperFlag, DataAddr_Lo,
1510 DataAddr_Hi, Ins, dl, DAG, InVals);
1513 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) const {
1514 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1515 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1516 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1521 // NeedToConvertToMemOp - Returns true if one of the operands of the
1522 // operation 'Op' needs to be put into memory. Also returns the
1523 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1524 // no instruction that can operation on two registers. Most insns take
1525 // one register and one memory operand (addwf) / Constant (addlw).
1526 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
1527 SelectionDAG &DAG) const {
1528 // If one of the operand is a constant, return false.
1529 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1530 Op.getOperand(1).getOpcode() == ISD::Constant)
1533 // Return false if one of the operands is already a direct
1534 // load and that operand has only one use.
1535 if (isDirectLoad(Op.getOperand(0))) {
1536 if (Op.getOperand(0).hasOneUse()) {
1537 // Legal and profitable folding check uses the NodeId of DAG nodes.
1538 // This NodeId is assigned by topological order. Therefore first
1539 // assign topological order then perform legal and profitable check.
1540 // Note:- Though this ordering is done before begining with legalization,
1541 // newly added node during legalization process have NodeId=-1 (NewNode)
1542 // therefore before performing any check proper ordering of the node is
1544 DAG.AssignTopologicalOrder();
1546 // Direct load operands are folded in binary operations. But before folding
1547 // verify if this folding is legal. Fold only if it is legal otherwise
1548 // convert this direct load to a separate memory operation.
1549 if (SelectionDAGISel::IsLegalToFold(Op.getOperand(0),
1550 Op.getNode(), Op.getNode(),
1551 CodeGenOpt::Default))
1558 // For operations that are non-cummutative there is no need to check
1559 // for right operand because folding right operand may result in
1560 // incorrect operation.
1561 if (! SelectionDAG::isCommutativeBinOp(Op.getOpcode()))
1564 if (isDirectLoad(Op.getOperand(1))) {
1565 if (Op.getOperand(1).hasOneUse()) {
1566 // Legal and profitable folding check uses the NodeId of DAG nodes.
1567 // This NodeId is assigned by topological order. Therefore first
1568 // assign topological order then perform legal and profitable check.
1569 // Note:- Though this ordering is done before begining with legalization,
1570 // newly added node during legalization process have NodeId=-1 (NewNode)
1571 // therefore before performing any check proper ordering of the node is
1573 DAG.AssignTopologicalOrder();
1575 // Direct load operands are folded in binary operations. But before folding
1576 // verify if this folding is legal. Fold only if it is legal otherwise
1577 // convert this direct load to a separate memory operation.
1578 if (SelectionDAGISel::IsLegalToFold(Op.getOperand(1),
1579 Op.getNode(), Op.getNode(),
1580 CodeGenOpt::Default))
1589 // LowerBinOp - Lower a commutative binary operation that does not
1590 // affect status flag carry.
1591 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) const {
1592 DebugLoc dl = Op.getDebugLoc();
1594 // We should have handled larger operands in type legalizer itself.
1595 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1598 if (NeedToConvertToMemOp(Op, MemOp, DAG)) {
1599 // Put one value on stack.
1600 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1602 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1610 // LowerADD - Lower all types of ADD operations including the ones
1611 // that affects carry.
1612 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
1613 // We should have handled larger operands in type legalizer itself.
1614 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1615 DebugLoc dl = Op.getDebugLoc();
1617 if (NeedToConvertToMemOp(Op, MemOp, DAG)) {
1618 // Put one value on stack.
1619 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1621 // ADDC and ADDE produce two results.
1622 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1624 // ADDE has three operands, the last one is the carry bit.
1625 if (Op.getOpcode() == ISD::ADDE)
1626 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1627 NewVal, Op.getOperand(2));
1628 // ADDC has two operands.
1629 else if (Op.getOpcode() == ISD::ADDC)
1630 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1632 // ADD it is. It produces only one result.
1634 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1641 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
1642 DebugLoc dl = Op.getDebugLoc();
1643 // We should have handled larger operands in type legalizer itself.
1644 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1646 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1648 // Since we don't have an instruction for X - c ,
1649 // we can change it to X + (-c)
1650 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1651 if (C && (Op.getOpcode() == ISD::SUB))
1653 return DAG.getNode(ISD::ADD,
1654 dl, MVT::i8, Op.getOperand(0),
1655 DAG.getConstant(0-(C->getZExtValue()), MVT::i8));
1658 if (NeedToConvertToMemOp(Op, MemOp, DAG) ||
1659 (isDirectLoad(Op.getOperand(1)) &&
1660 (!isDirectLoad(Op.getOperand(0))) &&
1661 (Op.getOperand(0).getOpcode() != ISD::Constant)))
1663 // Put first operand on stack.
1664 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1666 switch (Op.getOpcode()) {
1668 assert (0 && "Opcode unknown.");
1670 return DAG.getNode(Op.getOpcode(),
1671 dl, Tys, NewVal, Op.getOperand(1),
1675 return DAG.getNode(Op.getOpcode(),
1676 dl, Tys, NewVal, Op.getOperand(1));
1679 return DAG.getNode(Op.getOpcode(),
1680 dl, MVT::i8, NewVal, Op.getOperand(1));
1688 void PIC16TargetLowering::InitReservedFrameCount(const Function *F,
1689 SelectionDAG &DAG) const {
1690 MachineFunction &MF = DAG.getMachineFunction();
1691 PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>();
1693 unsigned NumArgs = F->arg_size();
1695 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1698 FuncInfo->setReservedFrameCount(NumArgs);
1700 FuncInfo->setReservedFrameCount(NumArgs + 1);
1703 // LowerFormalArguments - Argument values are loaded from the
1704 // <fname>.args + offset. All arguments are already broken to leaglized
1705 // types, so the offset just runs from 0 to NumArgVals - 1.
1708 PIC16TargetLowering::LowerFormalArguments(SDValue Chain,
1709 CallingConv::ID CallConv,
1711 const SmallVectorImpl<ISD::InputArg> &Ins,
1714 SmallVectorImpl<SDValue> &InVals)
1716 unsigned NumArgVals = Ins.size();
1718 // Get the callee's name to create the <fname>.args label to pass args.
1719 MachineFunction &MF = DAG.getMachineFunction();
1720 const Function *F = MF.getFunction();
1721 std::string FuncName = F->getName();
1723 // Reset the map of FI and TmpOffset
1724 ResetTmpOffsetMap(DAG);
1725 // Initialize the ReserveFrameCount
1726 InitReservedFrameCount(F, DAG);
1728 // Create the <fname>.args external symbol.
1729 const char *tmpName = ESNames::createESName(PAN::getArgsLabel(FuncName));
1730 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1732 // Load arg values from the label + offset.
1733 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1734 SDValue BS = DAG.getConstant(1, MVT::i8);
1735 for (unsigned i = 0; i < NumArgVals ; ++i) {
1736 SDValue Offset = DAG.getConstant(i, MVT::i8);
1737 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1739 Chain = getChain(PICLoad);
1740 InVals.push_back(PICLoad);
1746 // Perform DAGCombine of PIC16Load.
1747 // FIXME - Need a more elaborate comment here.
1748 SDValue PIC16TargetLowering::
1749 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1750 SelectionDAG &DAG = DCI.DAG;
1751 SDValue Chain = N->getOperand(0);
1752 if (N->hasNUsesOfValue(0, 0)) {
1753 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1758 // For all the functions with arguments some STORE nodes are generated
1759 // that store the argument on the frameindex. However in PIC16 the arguments
1760 // are passed on stack only. Therefore these STORE nodes are redundant.
1761 // To remove these STORE nodes will be removed in PerformStoreCombine
1763 // Currently this function is doint nothing and will be updated for removing
1764 // unwanted store operations
1765 SDValue PIC16TargetLowering::
1766 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1767 return SDValue(N, 0);
1769 // Storing an undef value is of no use, so remove it
1770 if (isStoringUndef(N, Chain, DAG)) {
1771 return Chain; // remove the store and return the chain
1773 //else everything is ok.
1774 return SDValue(N, 0);
1778 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1779 DAGCombinerInfo &DCI) const {
1780 switch (N->getOpcode()) {
1782 return PerformStoreCombine(N, DCI);
1783 case PIC16ISD::PIC16Load:
1784 return PerformPIC16LoadCombine(N, DCI);
1789 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1791 default: llvm_unreachable("Unknown condition code!");
1792 case ISD::SETNE: return PIC16CC::NE;
1793 case ISD::SETEQ: return PIC16CC::EQ;
1794 case ISD::SETGT: return PIC16CC::GT;
1795 case ISD::SETGE: return PIC16CC::GE;
1796 case ISD::SETLT: return PIC16CC::LT;
1797 case ISD::SETLE: return PIC16CC::LE;
1798 case ISD::SETULT: return PIC16CC::ULT;
1799 case ISD::SETULE: return PIC16CC::ULE;
1800 case ISD::SETUGE: return PIC16CC::UGE;
1801 case ISD::SETUGT: return PIC16CC::UGT;
1805 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1806 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1807 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1808 ISD::CondCode CC, unsigned &SPCC) {
1809 if (isa<ConstantSDNode>(RHS) &&
1810 cast<ConstantSDNode>(RHS)->isNullValue() &&
1812 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1813 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1814 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1815 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1816 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1817 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1818 SDValue CMPCC = LHS.getOperand(3);
1819 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1820 LHS = CMPCC.getOperand(0);
1821 RHS = CMPCC.getOperand(1);
1825 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1826 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1827 unsigned CC, SDValue &PIC16CC,
1828 SelectionDAG &DAG, DebugLoc dl) const {
1829 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1831 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1832 // i.e. a < 12 can be rewritten as 12 > a.
1833 if (RHS.getOpcode() == ISD::Constant) {
1842 CondCode = PIC16CC::GT;
1845 CondCode = PIC16CC::LT;
1848 CondCode = PIC16CC::UGT;
1851 CondCode = PIC16CC::ULT;
1854 CondCode = PIC16CC::LE;
1857 CondCode = PIC16CC::GE;
1860 CondCode = PIC16CC::UGE;
1863 CondCode = PIC16CC::ULE;
1868 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1870 // These are signed comparisons.
1871 SDValue Mask = DAG.getConstant(128, MVT::i8);
1872 if (isSignedComparison(CondCode)) {
1873 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1874 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1877 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1878 // We can use a subtract operation to set the condition codes. But
1879 // we need to put one operand in memory if required.
1880 // Nothing to do if the first operand is already a valid type (direct load
1881 // for subwf and literal for sublw) and it is used by this operation only.
1882 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1884 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1886 // else convert the first operand to mem.
1887 LHS = ConvertToMemOperand (LHS, DAG, dl);
1888 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1892 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op,
1893 SelectionDAG &DAG) const {
1894 SDValue LHS = Op.getOperand(0);
1895 SDValue RHS = Op.getOperand(1);
1896 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1897 SDValue TrueVal = Op.getOperand(2);
1898 SDValue FalseVal = Op.getOperand(3);
1899 unsigned ORIGCC = ~0;
1900 DebugLoc dl = Op.getDebugLoc();
1902 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1903 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1905 // A setcc: lhs, rhs, cc is expanded by llvm to
1906 // select_cc: result of setcc, 0, 1, 0, setne
1907 // We can think of it as:
1908 // select_cc: lhs, rhs, 1, 0, cc
1909 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1910 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1913 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1915 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1916 FalseVal, PIC16CC, Cmp.getValue(1));
1920 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1921 MachineBasicBlock *BB) const {
1922 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1923 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1924 DebugLoc dl = MI->getDebugLoc();
1926 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1927 // control-flow pattern. The incoming instruction knows the destination vreg
1928 // to set, the condition code register to branch on, the true/false values to
1929 // select between, and a branch opcode to use.
1930 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1931 MachineFunction::iterator It = BB;
1938 // fallthrough --> copy0MBB
1939 MachineBasicBlock *thisMBB = BB;
1940 MachineFunction *F = BB->getParent();
1941 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1942 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1943 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1944 F->insert(It, copy0MBB);
1945 F->insert(It, sinkMBB);
1947 // Transfer the remainder of BB and its successor edges to sinkMBB.
1948 sinkMBB->splice(sinkMBB->begin(), BB,
1949 llvm::next(MachineBasicBlock::iterator(MI)),
1951 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1953 // Next, add the true and fallthrough blocks as its successors.
1954 BB->addSuccessor(copy0MBB);
1955 BB->addSuccessor(sinkMBB);
1958 // %FalseValue = ...
1959 // # fallthrough to sinkMBB
1962 // Update machine-CFG edges
1963 BB->addSuccessor(sinkMBB);
1966 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1969 BuildMI(*BB, BB->begin(), dl,
1970 TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1971 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1972 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1974 MI->eraseFromParent(); // The pseudo instruction is gone now.
1979 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1980 SDValue Chain = Op.getOperand(0);
1981 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1982 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1983 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1984 SDValue Dest = Op.getOperand(4); // BB to jump to
1985 unsigned ORIGCC = ~0;
1986 DebugLoc dl = Op.getDebugLoc();
1988 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1989 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1990 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1991 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1993 // Get the Compare insn and condition code.
1995 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1997 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,