1 //===-- PIC16ISelLowering.cpp - PIC16 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pic16-lower"
17 #include "PIC16ISelLowering.h"
18 #include "PIC16TargetMachine.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/Support/Debug.h"
36 const char *PIC16TargetLowering:: getTargetNodeName(unsigned Opcode) const
40 case PIC16ISD::Hi : return "PIC16ISD::Hi";
41 case PIC16ISD::Lo : return "PIC16ISD::Lo";
42 case PIC16ISD::Package : return "PIC16ISD::Package";
43 case PIC16ISD::Wrapper : return "PIC16ISD::Wrapper";
44 case PIC16ISD::SetBank : return "PIC16ISD::SetBank";
45 case PIC16ISD::SetPage : return "PIC16ISD::SetPage";
46 case PIC16ISD::Branch : return "PIC16ISD::Branch";
47 case PIC16ISD::Cmp : return "PIC16ISD::Cmp";
48 case PIC16ISD::BTFSS : return "PIC16ISD::BTFSS";
49 case PIC16ISD::BTFSC : return "PIC16ISD::BTFSC";
50 case PIC16ISD::XORCC : return "PIC16ISD::XORCC";
51 case PIC16ISD::SUBCC : return "PIC16ISD::SUBCC";
52 default : return NULL;
57 PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM)
59 // PIC16 does not have i1 type, so use i8 for
60 // setcc operations results (slt, sgt, ...).
61 // setSetCCResultType(MVT::i8);
62 // setSetCCResultContents(ZeroOrOneSetCCResult);
64 // Set up the register classes
65 addRegisterClass(MVT::i8, PIC16::CPURegsRegisterClass);
66 addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass);
69 // Load extented operations for i1 types must be promoted
70 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
71 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
72 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
74 // Store operations for i1 types must be promoted
75 // setStoreXAction(MVT::i1, Promote);
76 // setStoreXAction(MVT::i8, Legal);
77 // setStoreXAction(MVT::i16, Custom);
78 // setStoreXAction(MVT::i32, Expand);
80 // setOperationAction(ISD::BUILD_PAIR, MVT::i32, Expand);
81 // setOperationAction(ISD::BUILD_PAIR, MVT::i16, Expand);
83 setOperationAction(ISD::ADD, MVT::i1, Promote);
84 setOperationAction(ISD::ADD, MVT::i8, Legal);
85 setOperationAction(ISD::ADD, MVT::i16, Custom);
86 setOperationAction(ISD::ADD, MVT::i32, Expand);
87 setOperationAction(ISD::ADD, MVT::i64, Expand);
89 setOperationAction(ISD::SUB, MVT::i1, Promote);
90 setOperationAction(ISD::SUB, MVT::i8, Legal);
91 setOperationAction(ISD::SUB, MVT::i16, Custom);
92 setOperationAction(ISD::SUB, MVT::i32, Expand);
93 setOperationAction(ISD::SUB, MVT::i64, Expand);
95 setOperationAction(ISD::ADDC, MVT::i1, Promote);
96 setOperationAction(ISD::ADDC, MVT::i8, Legal);
97 setOperationAction(ISD::ADDC, MVT::i16, Custom);
98 setOperationAction(ISD::ADDC, MVT::i32, Expand);
99 setOperationAction(ISD::ADDC, MVT::i64, Expand);
101 setOperationAction(ISD::ADDE, MVT::i1, Promote);
102 setOperationAction(ISD::ADDE, MVT::i8, Legal);
103 setOperationAction(ISD::ADDE, MVT::i16, Custom);
104 setOperationAction(ISD::ADDE, MVT::i32, Expand);
105 setOperationAction(ISD::ADDE, MVT::i64, Expand);
107 setOperationAction(ISD::SUBC, MVT::i1, Promote);
108 setOperationAction(ISD::SUBC, MVT::i8, Legal);
109 setOperationAction(ISD::SUBC, MVT::i16, Custom);
110 setOperationAction(ISD::SUBC, MVT::i32, Expand);
111 setOperationAction(ISD::SUBC, MVT::i64, Expand);
113 setOperationAction(ISD::SUBE, MVT::i1, Promote);
114 setOperationAction(ISD::SUBE, MVT::i8, Legal);
115 setOperationAction(ISD::SUBE, MVT::i16, Custom);
116 setOperationAction(ISD::SUBE, MVT::i32, Expand);
117 setOperationAction(ISD::SUBE, MVT::i64, Expand);
119 // PIC16 does not have these NodeTypes below.
120 setOperationAction(ISD::SETCC, MVT::i1, Expand);
121 setOperationAction(ISD::SETCC, MVT::i8, Expand);
122 setOperationAction(ISD::SETCC, MVT::Other, Expand);
123 setOperationAction(ISD::SELECT_CC, MVT::i1, Custom);
124 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
126 setOperationAction(ISD::BRCOND, MVT::i1, Expand);
127 setOperationAction(ISD::BRCOND, MVT::i8, Expand);
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i1, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
135 // Do we really need to Custom lower the GA ??
136 // setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
137 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
138 setOperationAction(ISD::RET, MVT::Other, Custom);
140 // PIC16 not supported intrinsics.
141 // setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
142 // setOperationAction(ISD::MEMSET, MVT::Other, Expand);
143 // setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
145 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
146 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
147 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
148 setOperationAction(ISD::ROTL , MVT::i32, Expand);
149 setOperationAction(ISD::ROTR , MVT::i32, Expand);
150 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
152 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
153 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
154 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
156 // We don't have line number support yet.
157 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
158 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
159 setOperationAction(ISD::LABEL, MVT::Other, Expand);
161 // Use the default for now
162 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
163 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
165 setOperationAction(ISD::LOAD, MVT::i1, Promote);
166 setOperationAction(ISD::LOAD, MVT::i8, Legal);
167 // setOperationAction(ISD::LOAD, MVT::i16, Expand);
168 // setOperationAction(ISD::LOAD, MVT::i32, Expand);
170 setTargetDAGCombine(ISD::LOAD);
171 setTargetDAGCombine(ISD::STORE);
172 setTargetDAGCombine(ISD::ADDE);
173 setTargetDAGCombine(ISD::ADDC);
174 setTargetDAGCombine(ISD::ADD);
175 setTargetDAGCombine(ISD::SUBE);
176 setTargetDAGCombine(ISD::SUBC);
177 setTargetDAGCombine(ISD::SUB);
179 // We must find a way to get rid of Package nodes in the map
180 // setTargetDAGCombine(PIC16ISD::Package);
182 // getValueTypeActions().setTypeAction((MVT::ValueType)MVT::i16, Expand);
184 setStackPointerRegisterToSaveRestore(PIC16::STKPTR);
185 computeRegisterProperties();
189 SDOperand PIC16TargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG)
191 SDVTList VTList16 = DAG.getVTList(MVT::i16, MVT::i16, MVT::Other);
192 switch (Op.getOpcode())
195 cout << "reduce store\n";
197 case ISD::FORMAL_ARGUMENTS:
198 cout<<"==== lowering formal args\n";
199 return LowerFORMAL_ARGUMENTS(Op, DAG);
200 case ISD::GlobalAddress:
201 cout<<"==== lowering GA\n";
202 return LowerGlobalAddress(Op, DAG);
204 cout<<"==== lowering ret\n";
205 return LowerRET(Op, DAG);
206 case ISD::FrameIndex:
207 cout<<"==== lowering frame index\n";
208 return LowerFrameIndex(Op, DAG);
210 cout <<"==== lowering adde\n";
216 cout << "==== lowering BR_CC\n";
217 return LowerBR_CC(Op, DAG);
223 //===----------------------------------------------------------------------===//
224 // Lower helper functions
225 //===----------------------------------------------------------------------===//
229 PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG)
231 MVT::ValueType VT = Op.getValueType();
232 SDOperand Chain = Op.getOperand(0);
233 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
234 SDOperand LHS = Op.getOperand(2);
235 SDOperand RHS = Op.getOperand(3);
236 SDOperand JumpVal = Op.getOperand(4);
239 unsigned branchOpcode;
240 SDOperand branchOperand;
242 SDOperand StatusReg = DAG.getRegister(PIC16::STATUSREG,MVT::i8);
243 SDOperand CPUReg = DAG.getRegister(PIC16::WREG,MVT::i8);
247 assert(0 && "This condition code is not handled yet!!");
252 cmpOpcode = PIC16ISD::XORCC;
253 branchOpcode = PIC16ISD::BTFSS;
254 branchOperand = DAG.getConstant(2,MVT::i8);
260 cmpOpcode = PIC16ISD::XORCC;
261 branchOpcode = PIC16ISD::BTFSC;
262 branchOperand = DAG.getConstant(2,MVT::i8);
267 assert(0 && "Greater Than condition code is not handled yet!!");
273 cmpOpcode = PIC16ISD::SUBCC;
274 branchOpcode = PIC16ISD::BTFSS;
275 branchOperand = DAG.getConstant(1, MVT::i8);
281 cmpOpcode = PIC16ISD::SUBCC;
282 branchOpcode = PIC16ISD::BTFSC;
283 branchOperand = DAG.getConstant(1,MVT::i8);
288 assert(0 && "Less Than Equal condition code is not handled yet!!");
293 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
294 SDOperand CmpValue = DAG.getNode(cmpOpcode, VTList, LHS, RHS).getValue(1);
295 // SDOperand CCOper = DAG.getConstant(CC,MVT::i8);
296 // Result = DAG.getNode(branchOpcode,VT, Chain, JumpVal, CCOper, StatusReg,
298 Result = DAG.getNode(branchOpcode, VT, Chain, JumpVal, branchOperand,
299 StatusReg, CmpValue);
302 // return SDOperand();
306 //===----------------------------------------------------------------------===//
307 // Misc Lower Operation implementation
308 //===----------------------------------------------------------------------===//
309 // Create a constant pool entry for global value and wrap it in a wrapper node.
311 PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
313 MVT::ValueType PtrVT = getPointerTy();
314 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
315 GlobalValue *GV = GSDN->getGlobal();
317 //for now only do the ram.
318 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
319 SDOperand CPBank = DAG.getNode(PIC16ISD::SetBank, MVT::i8, CPAddr);
320 CPAddr = DAG.getNode(PIC16ISD::Wrapper, MVT::i8, CPAddr,CPBank);
326 PIC16TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG)
328 switch(Op.getNumOperands())
331 assert(0 && "Do not know how to return this many arguments!");
334 return SDOperand(); // ret void is legal
339 PIC16TargetLowering::LowerFrameIndex(SDOperand N, SelectionDAG &DAG)
341 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
342 return DAG.getTargetFrameIndex(FIN->getIndex(), MVT::i32);
349 PIC16TargetLowering::LowerLOAD(SDNode *N,
351 DAGCombinerInfo &DCI) const
354 SDOperand TF; //TokenFactor
355 SDOperand OutChains[2];
356 SDOperand Chain = N->getOperand(0);
357 SDOperand Src = N->getOperand(1);
361 // If this load is directly stored, replace the load value with the stored
363 // TODO: Handle store large -> read small portion.
364 // TODO: Handle TRUNCSTORE/LOADEXT
365 LoadSDNode *LD = cast<LoadSDNode>(N);
366 SDOperand Ptr = LD->getBasePtr();
367 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
368 if (ISD::isNON_TRUNCStore(Chain.Val)) {
369 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
370 if (PrevST->getBasePtr() == Ptr &&
371 PrevST->getValue().getValueType() == N->getValueType(0))
372 return DCI.CombineTo(N, Chain.getOperand(1), Chain);
376 if (N->getValueType(0) != MVT::i16)
379 SDOperand toWorklist;
380 Outs[0] = DAG.getLoad(MVT::i8, Chain, Src, NULL, 0);
381 toWorklist = DAG.getNode(ISD::ADD, MVT::i16, Src,
382 DAG.getConstant(1, MVT::i16));
383 Outs[1] = DAG.getLoad(MVT::i8, Chain, toWorklist, NULL, 0);
384 // Add to worklist may not be needed.
385 // It is meant to merge sequences of add with constant into one.
386 DCI.AddToWorklist(toWorklist.Val);
388 // Create the tokenfactors and carry it on to the build_pair node
389 OutChains[0] = Outs[0].getValue(1);
390 OutChains[1] = Outs[1].getValue(1);
391 TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &OutChains[0], 2);
393 VTList = DAG.getVTList(MVT::i16, MVT::Flag);
394 retVal = DAG.getNode (PIC16ISD::Package, VTList, &Outs[0], 2);
396 DCI.CombineTo (N, retVal, TF);
402 PIC16TargetLowering::LowerADDSUB(SDNode *N, SelectionDAG &DAG,
403 DAGCombinerInfo &DCI) const
405 bool changed = false;
407 SDOperand LoOps[3], HiOps[3];
408 SDOperand OutOps[3]; //[0]:left, [1]:right, [2]:carry
415 InOp[0] = N->getOperand(0);
416 InOp[1] = N->getOperand(1);
418 switch (N->getOpcode())
421 if (InOp[0].getOpcode() == ISD::Constant &&
422 InOp[1].getOpcode() == ISD::Constant) {
423 ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
424 ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
425 return DAG.getConstant(CST0->getValue() + CST1->getValue(), MVT::i16);
434 if (InOp[0].getOpcode() == ISD::Constant &&
435 InOp[1].getOpcode() == ISD::Constant) {
436 ConstantSDNode *CST0 = dyn_cast<ConstantSDNode>(InOp[0]);
437 ConstantSDNode *CST1 = dyn_cast<ConstantSDNode>(InOp[1]);
438 return DAG.getConstant(CST0->getValue() - CST1->getValue(), MVT::i16);
448 assert ((N->getValueType(0) == MVT::i16)
449 && "expecting an MVT::i16 node for lowering");
450 assert ((N->getOperand(0).getValueType() == MVT::i16)
451 && (N->getOperand(1).getValueType() == MVT::i16)
452 && "both inputs to addx/subx:i16 must be i16");
454 for (i = 0; i < 2; i++) {
455 if (InOp[i].getOpcode() == ISD::GlobalAddress) {
456 //we don't want to lower subs/adds with global address (at least not yet)
459 else if (InOp[i].getOpcode() == ISD::Constant) {
461 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(InOp[i]);
462 LoOps[i] = DAG.getConstant(CST->getValue() & 0xFF, MVT::i8);
463 HiOps[i] = DAG.getConstant(CST->getValue() >> 8, MVT::i8);
465 else if (InOp[i].getOpcode() == PIC16ISD::Package) {
466 LoOps[i] = InOp[i].getOperand(0);
467 HiOps[i] = InOp[i].getOperand(1);
469 else if (InOp[i].getOpcode() == ISD::LOAD) {
471 // LowerLOAD returns a Package node or it may combine and return
473 SDOperand lowered = LowerLOAD(InOp[i].Val, DAG, DCI);
475 // So If LowerLOAD returns something other than Package,
476 // then just call ADD again
477 if (lowered.getOpcode() != PIC16ISD::Package)
478 return LowerADDSUB(N, DAG, DCI);
480 LoOps[i] = lowered.getOperand(0);
481 HiOps[i] = lowered.getOperand(1);
483 else if ((InOp[i].getOpcode() == ISD::ADD) ||
484 (InOp[i].getOpcode() == ISD::ADDE) ||
485 (InOp[i].getOpcode() == ISD::ADDC) ||
486 (InOp[i].getOpcode() == ISD::SUB) ||
487 (InOp[i].getOpcode() == ISD::SUBE) ||
488 (InOp[i].getOpcode() == ISD::SUBC)) {
490 //must call LowerADDSUB recursively here....
491 //LowerADDSUB returns a Package node
492 SDOperand lowered = LowerADDSUB(InOp[i].Val, DAG, DCI);
494 LoOps[i] = lowered.getOperand(0);
495 HiOps[i] = lowered.getOperand(1);
497 else if (InOp[i].getOpcode() == ISD::SIGN_EXTEND) {
498 //FIXME: I am just zero extending. for now.
500 LoOps[i] = InOp[i].getOperand(0);
501 HiOps[i] = DAG.getConstant(0, MVT::i8);
504 DAG.setGraphColor(N, "blue");
506 assert (0 && "not implemented yet");
510 assert (changed && "nothing changed while lowering SUBx/ADDx");
512 VTList = DAG.getVTList(MVT::i8, MVT::Flag);
513 if (N->getOpcode() == ASE) {
514 //we must take in the existing carry
515 //if this node is part of an existing subx/addx sequence
516 LoOps[2] = N->getOperand(2).getValue(1);
517 as1 = DAG.getNode (ASE, VTList, LoOps, 3);
520 as1 = DAG.getNode (ASC, VTList, LoOps, 2);
522 HiOps[2] = as1.getValue(1);
523 as2 = DAG.getNode (ASE, VTList, HiOps, 3);
524 //we must build a pair that also provides the carry from sube/adde
527 OutOps[2] = as2.getValue(1);
528 //breaking an original i16 so lets make the Package also an i16
529 if (N->getOpcode() == ASE) {
530 VTList = DAG.getVTList(MVT::i16, MVT::Flag);
531 retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 3);
532 DCI.CombineTo (N, retVal, OutOps[2]);
534 else if (N->getOpcode() == ASC) {
535 VTList = DAG.getVTList(MVT::i16, MVT::Flag);
536 retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 2);
537 DCI.CombineTo (N, retVal, OutOps[2]);
539 else if (N->getOpcode() == AS) {
540 VTList = DAG.getVTList(MVT::i16);
541 retVal = DAG.getNode (PIC16ISD::Package, VTList, OutOps, 2);
542 DCI.CombineTo (N, retVal);
549 //===----------------------------------------------------------------------===//
550 // Calling Convention Implementation
552 // The lower operations present on calling convention works on this order:
553 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
554 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
555 // LowerRET (virt regs --> phys regs)
556 // LowerCALL (phys regs --> virt regs)
558 //===----------------------------------------------------------------------===//
560 #include "PIC16GenCallingConv.inc"
562 //===----------------------------------------------------------------------===//
563 // CALL Calling Convention Implementation
564 //===----------------------------------------------------------------------===//
567 //===----------------------------------------------------------------------===//
568 // FORMAL_ARGUMENTS Calling Convention Implementation
569 //===----------------------------------------------------------------------===//
570 SDOperand PIC16TargetLowering::
571 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
573 SmallVector<SDOperand, 8> ArgValues;
574 SDOperand Root = Op.getOperand(0);
576 // Return the new list of results.
577 // Just copy right now.
578 ArgValues.push_back(Root);
580 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), &ArgValues[0],
581 ArgValues.size()).getValue(Op.ResNo);
585 //===----------------------------------------------------------------------===//
586 // Return Value Calling Convention Implementation
587 //===----------------------------------------------------------------------===//
589 //===----------------------------------------------------------------------===//
590 // PIC16 Inline Assembly Support
591 //===----------------------------------------------------------------------===//
593 //===----------------------------------------------------------------------===//
594 // Target Optimization Hooks
595 //===----------------------------------------------------------------------===//
597 SDOperand PIC16TargetLowering::PerformDAGCombine(SDNode *N,
598 DAGCombinerInfo &DCI) const
602 SelectionDAG &DAG = DCI.DAG;
604 switch (N->getOpcode())
607 case PIC16ISD::Package :
608 cout <<"==== combining PIC16ISD::Package\n";
612 if ((N->getOperand(0).getOpcode() == ISD::GlobalAddress) ||
613 (N->getOperand(0).getOpcode() == ISD::FrameIndex)) {
614 //do not touch pointer adds
621 if (N->getValueType(0) == MVT::i16) {
622 SDOperand retVal = LowerADDSUB(N, DAG,DCI);
623 // LowerADDSUB has already combined the result,
624 // so we just return nothing to avoid assertion failure from llvm
625 // if N has been deleted already
628 else if (N->getValueType(0) == MVT::i8) {
630 for (int i=0; i<2; i++) {
631 if (N->getOperand (i).getOpcode() == PIC16ISD::Package) {
633 "don't want to have PIC16ISD::Package as intput to add:i8");
640 SDOperand Chain = N->getOperand(0);
641 SDOperand Src = N->getOperand(1);
642 SDOperand Dest = N->getOperand(2);
643 unsigned int DstOff = 0;
648 // if source operand is expected to be extended to
649 // some higher type then - remove this extension
650 // SDNode and do the extension manually
651 if ((Src.getOpcode() == ISD::ANY_EXTEND) ||
652 (Src.getOpcode() == ISD::SIGN_EXTEND) ||
653 (Src.getOpcode() == ISD::ZERO_EXTEND)) {
654 Src = Src.Val->getOperand(0);
655 Stores[0] = DAG.getStore(Chain, Src, Dest, NULL,0);
659 switch(Src.getValueType())
674 if (isa<GlobalAddressSDNode>(Dest) && isa<LoadSDNode>(Src) &&
675 (Src.getValueType() != MVT::i8)) {
676 //create direct addressing a = b
677 Chain = Src.getOperand(0);
678 for (i=0; i<NUM_STORES; i++) {
679 SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Src.getOperand(1),
680 DAG.getConstant(DstOff, MVT::i16));
681 SDOperand LDN = DAG.getLoad(MVT::i8, Chain, ADN, NULL, 0);
682 SDOperand DSTADDR = DAG.getNode(ISD::ADD, MVT::i16, Dest,
683 DAG.getConstant(DstOff, MVT::i16));
684 Stores[i] = DAG.getStore(Chain, LDN, DSTADDR, NULL, 0);
689 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
692 else if (isa<GlobalAddressSDNode>(Dest) && isa<ConstantSDNode>(Src)
693 && (Src.getValueType() != MVT::i8))
695 //create direct addressing a = CONST
696 CST = dyn_cast<ConstantSDNode>(Src);
697 for (i = 0; i < NUM_STORES; i++) {
698 SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
699 SDOperand ADN = DAG.getNode(ISD::ADD, MVT::i16, Dest,
700 DAG.getConstant(DstOff, MVT::i16));
701 Stores[i] = DAG.getStore(Chain, CNST, ADN, NULL, 0);
706 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
709 else if (isa<LoadSDNode>(Dest) && isa<ConstantSDNode>(Src)
710 && (Src.getValueType() != MVT::i8)) {
711 //create indirect addressing
712 CST = dyn_cast<ConstantSDNode>(Src);
713 Chain = Dest.getOperand(0);
715 Load = DAG.getLoad(MVT::i16, Chain,Dest.getOperand(1), NULL, 0);
716 Chain = Load.getValue(1);
717 for (i=0; i<NUM_STORES; i++) {
718 SDOperand CNST = DAG.getConstant(CST->getValue() >> i*8, MVT::i8);
719 Stores[i] = DAG.getStore(Chain, CNST, Load, NULL, 0);
724 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], i);
727 else if (isa<LoadSDNode>(Dest) && isa<GlobalAddressSDNode>(Src)) {
728 // GlobalAddressSDNode *GAD = dyn_cast<GlobalAddressSDNode>(Src);
731 else if (Src.getOpcode() == PIC16ISD::Package) {
732 StoreSDNode *st = dyn_cast<StoreSDNode>(N);
733 SDOperand toWorkList, retVal;
734 Chain = N->getOperand(0);
736 if (st->isTruncatingStore()) {
737 retVal = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
740 toWorkList = DAG.getNode(ISD::ADD, MVT::i16, Dest,
741 DAG.getConstant(1, MVT::i16));
742 Stores[1] = DAG.getStore(Chain, Src.getOperand(0), Dest, NULL, 0);
743 Stores[0] = DAG.getStore(Chain, Src.getOperand(1), toWorkList, NULL, 0);
745 // We want to merge sequence of add with constant to one add and a
746 // constant, so add the ADD node to worklist to have llvm do that
748 DCI.AddToWorklist(toWorkList.Val);
750 // We don't need the Package so add to worklist so llvm deletes it
751 DCI.AddToWorklist(Src.Val);
752 retVal = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 2);
757 else if (Src.getOpcode() == ISD::TRUNCATE) {
760 // DAG.setGraphColor(N, "blue");
762 // assert (0 && "input to store not implemented yet");
769 SDOperand Ptr = N->getOperand(1);
770 if (Ptr.getOpcode() == PIC16ISD::Package) {
771 // DAG.setGraphColor(N, "blue");
773 // Here we must make so that:
774 // Ptr.getOperand(0) --> fsrl
775 // Ptr.getOperand(1) --> fsrh
776 assert (0 && "not implemented yet");
778 //return SDOperand();
786 //===----------------------------------------------------------------------===//
788 //===----------------------------------------------------------------------===//
789 const SDOperand *PIC16TargetLowering::
790 findLoadi8(const SDOperand &Src, SelectionDAG &DAG) const
793 if ((Src.getOpcode() == ISD::LOAD) && (Src.getValueType() == MVT::i8))
795 for (i=0; i<Src.getNumOperands(); i++) {
796 const SDOperand *retVal = findLoadi8(Src.getOperand(i),DAG);
797 if (retVal) return retVal;