2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
16 #include "PIC16ISelLowering.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 // PIC16TargetLowering Constructor.
33 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
34 : TargetLowering(TM), TmpSize(0) {
36 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
38 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
40 setShiftAmountType(MVT::i8);
41 setShiftAmountFlavor(Extend);
43 // SRA library call names
44 setPIC16LibcallName(PIC16ISD::SRA_I8, "__intrinsics.sra.i8");
45 setLibcallName(RTLIB::SRA_I16, "__intrinsics.sra.i16");
46 setLibcallName(RTLIB::SRA_I32, "__intrinsics.sra.i32");
48 // SHL library call names
49 setPIC16LibcallName(PIC16ISD::SLL_I8, "__intrinsics.sll.i8");
50 setLibcallName(RTLIB::SHL_I16, "__intrinsics.sll.i16");
51 setLibcallName(RTLIB::SHL_I32, "__intrinsics.sll.i32");
53 // SRL library call names
54 setPIC16LibcallName(PIC16ISD::SRL_I8, "__intrinsics.srl.i8");
55 setLibcallName(RTLIB::SRL_I16, "__intrinsics.srl.i16");
56 setLibcallName(RTLIB::SRL_I32, "__intrinsics.srl.i32");
58 // MUL Library call names
59 setPIC16LibcallName(PIC16ISD::MUL_I8, "__intrinsics.mul.i8");
60 setLibcallName(RTLIB::MUL_I16, "__intrinsics.mul.i16");
61 setLibcallName(RTLIB::MUL_I32, "__intrinsics.mul.i32");
63 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
64 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
66 setOperationAction(ISD::LOAD, MVT::i8, Legal);
67 setOperationAction(ISD::LOAD, MVT::i16, Custom);
68 setOperationAction(ISD::LOAD, MVT::i32, Custom);
70 setOperationAction(ISD::STORE, MVT::i8, Legal);
71 setOperationAction(ISD::STORE, MVT::i16, Custom);
72 setOperationAction(ISD::STORE, MVT::i32, Custom);
74 setOperationAction(ISD::ADDE, MVT::i8, Custom);
75 setOperationAction(ISD::ADDC, MVT::i8, Custom);
76 setOperationAction(ISD::SUBE, MVT::i8, Custom);
77 setOperationAction(ISD::SUBC, MVT::i8, Custom);
78 setOperationAction(ISD::ADD, MVT::i8, Custom);
79 setOperationAction(ISD::ADD, MVT::i16, Custom);
81 setOperationAction(ISD::OR, MVT::i8, Custom);
82 setOperationAction(ISD::AND, MVT::i8, Custom);
83 setOperationAction(ISD::XOR, MVT::i8, Custom);
85 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
86 setOperationAction(ISD::CALL, MVT::i16, Custom);
87 setOperationAction(ISD::RET, MVT::Other, Custom);
89 setOperationAction(ISD::MUL, MVT::i8, Custom);
90 setOperationAction(ISD::MUL, MVT::i16, Expand);
91 setOperationAction(ISD::MUL, MVT::i32, Expand);
93 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
95 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
96 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
97 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
98 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
99 setOperationAction(ISD::MULHU, MVT::i8, Expand);
100 setOperationAction(ISD::MULHU, MVT::i16, Expand);
101 setOperationAction(ISD::MULHU, MVT::i32, Expand);
102 setOperationAction(ISD::MULHS, MVT::i8, Expand);
103 setOperationAction(ISD::MULHS, MVT::i16, Expand);
104 setOperationAction(ISD::MULHS, MVT::i32, Expand);
106 setOperationAction(ISD::SRA, MVT::i8, Custom);
107 setOperationAction(ISD::SRA, MVT::i16, Expand);
108 setOperationAction(ISD::SRA, MVT::i32, Expand);
109 setOperationAction(ISD::SHL, MVT::i8, Custom);
110 setOperationAction(ISD::SHL, MVT::i16, Expand);
111 setOperationAction(ISD::SHL, MVT::i32, Expand);
112 setOperationAction(ISD::SRL, MVT::i8, Custom);
113 setOperationAction(ISD::SRL, MVT::i16, Expand);
114 setOperationAction(ISD::SRL, MVT::i32, Expand);
116 // PIC16 does not support shift parts
117 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
118 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
119 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
120 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
121 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
122 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
124 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
125 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
128 // PIC16 does not have a SETCC, expand it to SELECT_CC.
129 setOperationAction(ISD::SETCC, MVT::i8, Expand);
130 setOperationAction(ISD::SELECT, MVT::i8, Expand);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BRIND, MVT::Other, Expand);
134 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
135 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
137 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
138 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
140 // Now deduce the information based on the above mentioned
142 computeRegisterProperties();
145 // getOutFlag - Extract the flag result if the Op has it.
146 static SDValue getOutFlag(SDValue &Op) {
147 // Flag is the last value of the node.
148 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
150 assert (Flag.getValueType() == MVT::Flag
151 && "Node does not have an out Flag");
155 // Get the TmpOffset for FrameIndex
156 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
157 std::map<unsigned, unsigned>::iterator
158 MapIt = FiTmpOffsetMap.find(FI);
159 if (MapIt != FiTmpOffsetMap.end())
160 return MapIt->second;
162 // This FI (FrameIndex) is not yet mapped, so map it
163 FiTmpOffsetMap[FI] = TmpSize;
165 return FiTmpOffsetMap[FI];
168 // To extract chain value from the SDValue Nodes
169 // This function will help to maintain the chain extracting
170 // code at one place. In case of any change in future it will
171 // help maintain the code.
172 static SDValue getChain(SDValue &Op) {
173 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
175 // If the last value returned in Flag then the chain is
176 // second last value returned.
177 if (Chain.getValueType() == MVT::Flag)
178 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
180 // All nodes may not produce a chain. Therefore following assert
181 // verifies that the node is returning a chain only.
182 assert (Chain.getValueType() == MVT::Other
183 && "Node does not have a chain");
188 /// PopulateResults - Helper function to LowerOperation.
189 /// If a node wants to return multiple results after lowering,
190 /// it stuffs them into an array of SDValue called Results.
192 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
193 if (N.getOpcode() == ISD::MERGE_VALUES) {
194 int NumResults = N.getNumOperands();
195 for( int i = 0; i < NumResults; i++)
196 Results.push_back(N.getOperand(i));
199 Results.push_back(N);
202 MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
206 /// The type legalizer framework of generating legalizer can generate libcalls
207 /// only when the operand/result types are illegal.
208 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
209 /// For example an arithmetic right shift. These functions are used to lower
210 /// such operations that generate libcall for legal types.
213 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
215 PIC16LibcallNames[Call] = Name;
219 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
220 return PIC16LibcallNames[Call];
224 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
225 MVT RetVT, const SDValue *Ops,
226 unsigned NumOps, bool isSigned,
227 SelectionDAG &DAG, DebugLoc dl) {
229 TargetLowering::ArgListTy Args;
230 Args.reserve(NumOps);
232 TargetLowering::ArgListEntry Entry;
233 for (unsigned i = 0; i != NumOps; ++i) {
235 Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
236 Entry.isSExt = isSigned;
237 Entry.isZExt = !isSigned;
238 Args.push_back(Entry);
240 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
242 const Type *RetTy = RetVT.getTypeForMVT();
243 std::pair<SDValue,SDValue> CallInfo =
244 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
245 false, CallingConv::C, false, Callee, Args, DAG, dl);
247 return CallInfo.first;
250 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
252 default: return NULL;
253 case PIC16ISD::Lo: return "PIC16ISD::Lo";
254 case PIC16ISD::Hi: return "PIC16ISD::Hi";
255 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
256 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
257 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
258 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
259 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
260 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
261 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
262 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
263 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
264 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
265 case PIC16ISD::BCF: return "PIC16ISD::BCF";
266 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
267 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
268 case PIC16ISD::RLF: return "PIC16ISD::RLF";
269 case PIC16ISD::RRF: return "PIC16ISD::RRF";
270 case PIC16ISD::CALL: return "PIC16ISD::CALL";
271 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
272 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
273 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
274 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
275 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
279 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
280 SmallVectorImpl<SDValue>&Results,
283 switch (N->getOpcode()) {
284 case ISD::GlobalAddress:
285 Results.push_back(ExpandGlobalAddress(N, DAG));
287 case ISD::ExternalSymbol:
288 Results.push_back(ExpandExternalSymbol(N, DAG));
291 Results.push_back(ExpandStore(N, DAG));
294 PopulateResults(ExpandLoad(N, DAG), Results);
297 // Results.push_back(ExpandAdd(N, DAG));
299 case ISD::FrameIndex:
300 Results.push_back(ExpandFrameIndex(N, DAG));
303 assert (0 && "not implemented");
308 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
310 // Currently handling FrameIndex of size MVT::i16 only
311 // One example of this scenario is when return value is written on
314 if (N->getValueType(0) != MVT::i16)
317 // Expand the FrameIndex into ExternalSymbol and a Constant node
318 // The constant will represent the frame index number
319 // Get the current function frame
320 MachineFunction &MF = DAG.getMachineFunction();
321 const Function *Func = MF.getFunction();
322 const std::string Name = Func->getName();
324 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
325 // FIXME there isn't really debug info here
326 DebugLoc dl = FR->getDebugLoc();
327 int Index = FR->getIndex();
330 FI[0] = DAG.getTargetFrameIndex(Index, MVT::i8);
331 FI[1] = DAG.getTargetFrameIndex(Index + 1, MVT::i8);
332 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), FI[0], FI[1]);
336 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
337 StoreSDNode *St = cast<StoreSDNode>(N);
338 SDValue Chain = St->getChain();
339 SDValue Src = St->getValue();
340 SDValue Ptr = St->getBasePtr();
341 MVT ValueType = Src.getValueType();
342 unsigned StoreOffset = 0;
343 DebugLoc dl = N->getDebugLoc();
345 SDValue PtrLo, PtrHi;
346 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
348 if (ValueType == MVT::i8) {
349 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
351 DAG.getConstant (0 + StoreOffset, MVT::i8));
353 else if (ValueType == MVT::i16) {
354 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
355 SDValue SrcLo, SrcHi;
356 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
357 SDValue ChainLo = Chain, ChainHi = Chain;
358 if (Chain.getOpcode() == ISD::TokenFactor) {
359 ChainLo = Chain.getOperand(0);
360 ChainHi = Chain.getOperand(1);
362 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
365 DAG.getConstant (0 + StoreOffset, MVT::i8));
367 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
369 DAG.getConstant (1 + StoreOffset, MVT::i8));
371 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
374 else if (ValueType == MVT::i32) {
375 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
376 SDValue SrcLo, SrcHi;
377 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
379 // Get the expanded parts of each of SrcLo and SrcHi.
380 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
381 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
382 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
384 SDValue ChainLo = Chain, ChainHi = Chain;
385 if (Chain.getOpcode() == ISD::TokenFactor) {
386 ChainLo = Chain.getOperand(0);
387 ChainHi = Chain.getOperand(1);
389 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
391 if (ChainLo.getOpcode() == ISD::TokenFactor) {
392 ChainLo1 = ChainLo.getOperand(0);
393 ChainLo2 = ChainLo.getOperand(1);
395 if (ChainHi.getOpcode() == ISD::TokenFactor) {
396 ChainHi1 = ChainHi.getOperand(0);
397 ChainHi2 = ChainHi.getOperand(1);
399 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
401 SrcLo1, PtrLo, PtrHi,
402 DAG.getConstant (0 + StoreOffset, MVT::i8));
404 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
405 SrcLo2, PtrLo, PtrHi,
406 DAG.getConstant (1 + StoreOffset, MVT::i8));
408 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
409 SrcHi1, PtrLo, PtrHi,
410 DAG.getConstant (2 + StoreOffset, MVT::i8));
412 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
413 SrcHi2, PtrLo, PtrHi,
414 DAG.getConstant (3 + StoreOffset, MVT::i8));
416 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
417 getChain(Store1), getChain(Store2));
418 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
419 getChain(Store3), getChain(Store4));
420 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
424 assert (0 && "value type not supported");
429 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
431 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
432 // FIXME there isn't really debug info here
433 DebugLoc dl = ES->getDebugLoc();
435 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
437 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES);
438 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES);
440 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
443 // ExpandGlobalAddress -
444 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
445 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
446 // FIXME there isn't really debug info here
447 DebugLoc dl = G->getDebugLoc();
449 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
452 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA);
453 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA);
455 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
458 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
459 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
461 if (Op.getOpcode() == ISD::BUILD_PAIR) {
462 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
468 // Return true if DirectAddress is in ROM_SPACE
469 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
471 // RomAddress is a GlobalAddress in ROM_SPACE_
472 // If the Op is not a GlobalAddress return NULL without checking
474 if (!isDirectAddress(Op))
477 // Its a GlobalAddress.
478 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
479 SDValue TGA = Op.getOperand(0).getOperand(0);
480 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
481 const Type *ValueType = GSDN->getGlobal()->getType();
483 if (!isa<PointerType>(ValueType)) {
484 assert(0 && "TGA must be of a PointerType");
487 int AddrSpace = dyn_cast<PointerType>(ValueType)->getAddressSpace();
488 if (AddrSpace == PIC16ISD::ROM_SPACE)
491 // Any other address space return it false
496 // GetExpandedParts - This function is on the similiar lines as
497 // the GetExpandedInteger in type legalizer is. This returns expanded
498 // parts of Op in Lo and Hi.
500 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
501 SDValue &Lo, SDValue &Hi) {
502 SDNode *N = Op.getNode();
503 DebugLoc dl = N->getDebugLoc();
504 MVT NewVT = getTypeToTransformTo(N->getValueType(0));
506 // Extract the lo component.
507 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
508 DAG.getConstant(0, MVT::i8));
510 // extract the hi component
511 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
512 DAG.getConstant(1, MVT::i8));
515 // Legalize FrameIndex into ExternalSymbol and offset.
517 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
518 SDValue &ES, int &Offset) {
520 MachineFunction &MF = DAG.getMachineFunction();
521 const Function *Func = MF.getFunction();
522 MachineFrameInfo *MFI = MF.getFrameInfo();
523 const std::string Name = Func->getName();
525 char *tmpName = new char [strlen(Name.c_str()) + 8];
526 sprintf(tmpName, "%s.frame", Name.c_str());
527 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
528 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
530 // FrameIndices are not stack offsets. But they represent the request
531 // for space on stack. That space requested may be more than one byte.
532 // Therefore, to calculate the stack offset that a FrameIndex aligns
533 // with, we need to traverse all the FrameIndices available earlier in
534 // the list and add their requested size.
535 unsigned FIndex = FR->getIndex();
537 for (unsigned i=0; i<FIndex ; ++i) {
538 Offset += MFI->getObjectSize(i);
544 // This function legalizes the PIC16 Addresses. If the Pointer is
545 // -- Direct address variable residing
546 // --> then a Banksel for that variable will be created.
548 // --> then it will be treated as an indirect address.
549 // -- Indirect address
550 // --> then the address will be loaded into FSR
551 // -- ADD with constant operand
552 // --> then constant operand of ADD will be returned as Offset
553 // and non-constant operand of ADD will be treated as pointer.
554 // Returns the high and lo part of the address, and the offset(in case of ADD).
556 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
557 SDValue &Lo, SDValue &Hi,
558 unsigned &Offset, DebugLoc dl) {
560 // Offset, by default, should be 0
563 // If the pointer is ADD with constant,
564 // return the constant value as the offset
565 if (Ptr.getOpcode() == ISD::ADD) {
566 SDValue OperLeft = Ptr.getOperand(0);
567 SDValue OperRight = Ptr.getOperand(1);
568 if (OperLeft.getOpcode() == ISD::Constant) {
569 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
571 } else if (OperRight.getOpcode() == ISD::Constant) {
572 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
577 // If the pointer is Type i8 and an external symbol
578 // then treat it as direct address.
579 // One example for such case is storing and loading
580 // from function frame during a call
581 if (Ptr.getValueType() == MVT::i8) {
582 switch (Ptr.getOpcode()) {
583 case ISD::TargetExternalSymbol:
585 Hi = DAG.getConstant(1, MVT::i8);
590 if (Ptr.getOpcode() == ISD::BUILD_PAIR &&
591 Ptr.getOperand(0).getOpcode() == ISD::TargetFrameIndex) {
594 LegalizeFrameIndex(Ptr.getOperand(0), DAG, Lo, FrameOffset);
595 Hi = DAG.getConstant(1, MVT::i8);
596 Offset += FrameOffset;
600 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
601 // Direct addressing case for RAM variables. The Hi part is constant
602 // and the Lo part is the TGA itself.
603 Lo = Ptr.getOperand(0).getOperand(0);
605 // For direct addresses Hi is a constant. Value 1 for the constant
606 // signifies that banksel needs to generated for it. Value 0 for
607 // the constant signifies that banksel does not need to be generated
608 // for it. Mark it as 1 now and optimize later.
609 Hi = DAG.getConstant(1, MVT::i8);
613 // Indirect addresses. Get the hi and lo parts of ptr.
614 GetExpandedParts(Ptr, DAG, Lo, Hi);
616 // Put the hi and lo parts into FSR.
617 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
618 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
623 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
624 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
625 SDValue Chain = LD->getChain();
626 SDValue Ptr = LD->getBasePtr();
627 DebugLoc dl = LD->getDebugLoc();
629 SDValue Load, Offset;
632 SDValue PtrLo, PtrHi;
635 // Legalize direct/indirect addresses. This will give the lo and hi parts
636 // of the address and the offset.
637 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
639 // Load from the pointer (direct address or FSR)
640 VT = N->getValueType(0);
641 unsigned NumLoads = VT.getSizeInBits() / 8;
642 std::vector<SDValue> PICLoads;
644 MVT MemVT = LD->getMemoryVT();
645 if(ISD::isNON_EXTLoad(N)) {
646 for (iter=0; iter<NumLoads ; ++iter) {
647 // Add the pointer offset if any
648 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
649 Tys = DAG.getVTList(MVT::i8, MVT::Other);
650 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
652 PICLoads.push_back(Load);
655 // If it is extended load then use PIC16Load for Memory Bytes
656 // and for all extended bytes perform action based on type of
657 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
660 // For extended loads this is the memory value type
661 // i.e. without any extension
662 MVT MemVT = LD->getMemoryVT();
663 unsigned MemBytes = MemVT.getSizeInBits() / 8;
664 unsigned ExtdBytes = VT.getSizeInBits() / 8;
665 Offset = DAG.getConstant(LoadOffset, MVT::i8);
667 Tys = DAG.getVTList(MVT::i8, MVT::Other);
668 // For MemBytes generate PIC16Load with proper offset
669 for (iter=0; iter<MemBytes; ++iter) {
670 // Add the pointer offset if any
671 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
672 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
674 PICLoads.push_back(Load);
677 // For SignExtendedLoad
678 if (ISD::isSEXTLoad(N)) {
679 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
681 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
682 DAG.getConstant(7, MVT::i8));
683 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
684 PICLoads.push_back(SRA);
686 } else if (ISD::isZEXTLoad(N)) {
687 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
688 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
689 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
690 PICLoads.push_back(ConstZero);
697 // Operand of Load is illegal -- Load itself is legal
700 else if (VT == MVT::i16) {
701 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
702 if (MemVT == MVT::i8)
703 Chain = getChain(PICLoads[0]);
705 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
706 getChain(PICLoads[0]), getChain(PICLoads[1]));
707 } else if (VT == MVT::i32) {
709 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
710 PICLoads[0], PICLoads[1]);
711 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
712 PICLoads[2], PICLoads[3]);
713 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
714 if (MemVT == MVT::i8)
715 Chain = getChain(PICLoads[0]);
716 else if (MemVT == MVT::i16)
717 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
718 getChain(PICLoads[0]), getChain(PICLoads[1]));
721 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
722 getChain(PICLoads[0]), getChain(PICLoads[1]));
723 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
724 getChain(PICLoads[2]), getChain(PICLoads[3]));
725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
726 Chains[0], Chains[1]);
729 Tys = DAG.getVTList(VT, MVT::Other);
730 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
733 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
734 // We should have handled larger operands in type legalizer itself.
735 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
737 SDNode *N = Op.getNode();
738 SDValue Value = N->getOperand(0);
739 SDValue Amt = N->getOperand(1);
740 PIC16ISD::PIC16Libcall CallCode;
741 switch (N->getOpcode()) {
743 CallCode = PIC16ISD::SRA_I8;
746 CallCode = PIC16ISD::SLL_I8;
749 CallCode = PIC16ISD::SRL_I8;
752 assert ( 0 && "This shift is not implemented yet.");
755 SmallVector<SDValue, 2> Ops(2);
758 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
759 true, DAG, N->getDebugLoc());
764 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
765 SmallVectorImpl<SDValue>&Results,
767 SDValue Op = SDValue(N, 0);
770 switch (Op.getOpcode()) {
771 case ISD::FORMAL_ARGUMENTS:
772 Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
774 Res = ExpandLoad(Op.getNode(), DAG); break;
776 Res = LowerCALL(Op, DAG); break;
778 // All other operations are handled in LowerOperation.
779 Res = LowerOperation(Op, DAG);
781 Results.push_back(Res);
788 unsigned NumValues = N->getNumValues();
789 for (i = 0; i < NumValues ; i++) {
790 Results.push_back(SDValue(N, i));
794 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
795 switch (Op.getOpcode()) {
796 case ISD::FORMAL_ARGUMENTS:
797 return LowerFORMAL_ARGUMENTS(Op, DAG);
801 return LowerADD(Op, DAG);
805 return LowerSUB(Op, DAG);
807 return ExpandLoad(Op.getNode(), DAG);
809 return ExpandStore(Op.getNode(), DAG);
813 return LowerShift(Op, DAG);
817 return LowerBinOp(Op, DAG);
819 return LowerCALL(Op, DAG);
821 return LowerRET(Op, DAG);
823 return LowerBR_CC(Op, DAG);
825 return LowerSELECT_CC(Op, DAG);
830 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
833 assert (Op.getValueType() == MVT::i8
834 && "illegal value type to store on stack.");
836 MachineFunction &MF = DAG.getMachineFunction();
837 const Function *Func = MF.getFunction();
838 const std::string FuncName = Func->getName();
840 char *tmpName = new char [strlen(FuncName.c_str()) + 8];
842 // Put the value on stack.
843 // Get a stack slot index and convert to es.
844 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
845 sprintf(tmpName, "%s.tmp", FuncName.c_str());
846 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
848 // Store the value to ES.
849 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
852 DAG.getConstant (1, MVT::i8), // Banksel.
853 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
856 // Load the value from ES.
857 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
858 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
859 ES, DAG.getConstant (1, MVT::i8),
860 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
863 return Load.getValue(0);
866 SDValue PIC16TargetLowering::
867 LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag,
868 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
870 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
871 unsigned NumOps = TheCall->getNumArgs();
872 DebugLoc dl = TheCall->getDebugLoc();
874 // If call has no arguments then do nothing and return.
878 std::vector<SDValue> Ops;
879 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
880 SDValue Arg, StoreRet;
882 // For PIC16 ABI the arguments come after the return value.
883 unsigned RetVals = TheCall->getNumRetVals();
884 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
886 Arg = TheCall->getArg(i);
888 Ops.push_back(Chain);
890 Ops.push_back(DataAddr_Lo);
891 Ops.push_back(DataAddr_Hi);
892 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
893 Ops.push_back(InFlag);
895 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
897 Chain = getChain(StoreRet);
898 InFlag = getOutFlag(StoreRet);
904 SDValue PIC16TargetLowering::
905 LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue FrameAddress,
906 SDValue InFlag, SelectionDAG &DAG) {
907 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
908 unsigned NumOps = TheCall->getNumArgs();
909 DebugLoc dl = TheCall->getDebugLoc();
911 SDValue Arg, StoreAt;
916 // If call has no arguments then do nothing and return.
920 // FIXME: This portion of code currently assumes only
921 // primitive types being passed as arguments.
923 // Legalize the address before use
924 SDValue PtrLo, PtrHi;
925 unsigned AddressOffset;
927 LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset, dl);
930 std::vector<SDValue> Ops;
931 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
932 for (unsigned i=ArgCount, Offset = 0; i<NumOps; i++) {
934 Arg = TheCall->getArg(i);
936 StoreOffset = (Offset + AddressOffset);
938 // Store the argument on frame
941 Ops.push_back(Chain);
943 Ops.push_back(PtrLo);
944 Ops.push_back(PtrHi);
945 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
946 Ops.push_back(InFlag);
948 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
950 Chain = getChain(StoreRet);
951 InFlag = getOutFlag(StoreRet);
953 // Update the frame offset to be used for next argument
954 ArgVT = Arg.getValueType();
955 Size = ArgVT.getSizeInBits();
956 Size = Size/8; // Calculate size in bytes
957 Offset += Size; // Increase the frame offset
962 SDValue PIC16TargetLowering::
963 LowerIndirectCallReturn (SDValue Op, SDValue Chain, SDValue InFlag,
964 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
966 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
967 DebugLoc dl = TheCall->getDebugLoc();
968 unsigned RetVals = TheCall->getNumRetVals();
970 // If call does not have anything to return
971 // then do nothing and go back.
975 // Call has something to return
976 std::vector<SDValue> ResultVals;
979 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
980 for(unsigned i=0;i<RetVals;i++) {
981 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
982 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
984 InFlag = getOutFlag(LoadRet);
985 Chain = getChain(LoadRet);
986 ResultVals.push_back(LoadRet);
988 ResultVals.push_back(Chain);
989 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
993 SDValue PIC16TargetLowering::
994 LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue FrameAddress,
995 SDValue InFlag, SelectionDAG &DAG) {
996 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
997 DebugLoc dl = TheCall->getDebugLoc();
998 // Currently handling primitive types only. They will come in
1000 unsigned RetVals = TheCall->getNumRetVals();
1002 std::vector<SDValue> ResultVals;
1004 // Return immediately if the return type is void
1008 // Call has something to return
1010 // Legalize the address before use
1013 LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset, dl);
1015 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1018 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1020 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1021 DAG.getConstant(LdOffset + Offset, MVT::i8),
1024 InFlag = getOutFlag(LoadRet);
1026 Chain = getChain(LoadRet);
1028 ResultVals.push_back(LoadRet);
1031 // To return use MERGE_VALUES
1032 ResultVals.push_back(Chain);
1033 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1037 SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1038 SDValue Chain = Op.getOperand(0);
1039 DebugLoc dl = Op.getDebugLoc();
1041 if (Op.getNumOperands() == 1) // return void
1044 // return should have odd number of operands
1045 if ((Op.getNumOperands() % 2) == 0 ) {
1046 assert(0 && "Do not know how to return this many arguments!");
1050 // Number of values to return
1051 unsigned NumRet = (Op.getNumOperands() / 2);
1053 // Function returns value always on stack with the offset starting
1055 MachineFunction &MF = DAG.getMachineFunction();
1056 const Function *F = MF.getFunction();
1057 std::string FuncName = F->getName();
1059 char *tmpName = new char [strlen(FuncName.c_str()) + 8];
1060 sprintf(tmpName, "%s.frame", FuncName.c_str());
1061 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1062 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1063 SDValue BS = DAG.getConstant(1, MVT::i8);
1065 for(unsigned i=0;i<NumRet; ++i) {
1066 RetVal = Op.getNode()->getOperand(2*i + 1);
1067 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1069 DAG.getConstant (i, MVT::i8));
1072 return DAG.getNode(ISD::RET, dl, MVT::Other, Chain);
1075 // CALL node may have some operands non-legal to PIC16. Generate new CALL
1076 // node with all the operands legal.
1077 // Currently only Callee operand of the CALL node is non-legal. This function
1078 // legalizes the Callee operand and uses all other operands as are to generate
1081 SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) {
1082 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1083 SDValue Chain = TheCall->getChain();
1084 SDValue Callee = TheCall->getCallee();
1085 DebugLoc dl = TheCall->getDebugLoc();
1088 assert(Callee.getValueType() == MVT::i16 &&
1089 "Don't know how to legalize this call node!!!");
1090 assert(Callee.getOpcode() == ISD::BUILD_PAIR &&
1091 "Don't know how to legalize this call node!!!");
1093 if (isDirectAddress(Callee)) {
1094 // Come here for direct calls
1095 Callee = Callee.getOperand(0).getOperand(0);
1097 // Come here for indirect calls
1099 // Indirect addresses. Get the hi and lo parts of ptr.
1100 GetExpandedParts(Callee, DAG, Lo, Hi);
1101 // Connect Lo and Hi parts of the callee with the PIC16Connect
1102 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1104 std::vector<SDValue> Ops;
1105 Ops.push_back(Chain);
1106 Ops.push_back(Callee);
1108 // Add the call arguments and their flags
1109 unsigned NumArgs = TheCall->getNumArgs();
1110 for(i=0;i<NumArgs;i++) {
1111 Ops.push_back(TheCall->getArg(i));
1112 Ops.push_back(TheCall->getArgFlagsVal(i));
1114 std::vector<MVT> NodeTys;
1115 unsigned NumRets = TheCall->getNumRetVals();
1116 for(i=0;i<NumRets;i++)
1117 NodeTys.push_back(TheCall->getRetValType(i));
1119 // Return a Chain as well
1120 NodeTys.push_back(MVT::Other);
1122 SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
1123 // Generate new call with all the operands legal
1124 return DAG.getCall(TheCall->getCallingConv(), dl,
1125 TheCall->isVarArg(), TheCall->isTailCall(),
1126 TheCall->isInreg(), VTs, &Ops[0], Ops.size());
1129 void PIC16TargetLowering::
1130 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1131 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1132 SelectionDAG &DAG) {
1133 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1134 && "Don't know what to do of such callee!!");
1135 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1136 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1137 Chain = getChain(SeqStart);
1138 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1140 // Get the Lo and Hi part of code address
1141 SDValue Lo = Callee.getOperand(0);
1142 SDValue Hi = Callee.getOperand(1);
1144 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1145 Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Hi);
1146 // Use the Lo part as is and make CALLW
1147 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1148 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1150 Chain = getChain(Call);
1151 OperFlag = getOutFlag(Call);
1152 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1154 Chain = getChain(SeqEnd);
1155 OperFlag = getOutFlag(SeqEnd);
1157 // Low part of Data Address
1158 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1160 // Make the second call.
1161 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1162 Chain = getChain(SeqStart);
1163 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1165 // Add 1 to Lo part for the second code word.
1166 Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, Lo, DAG.getConstant(1, MVT::i8));
1167 // Use new Lo to make another CALLW
1168 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1169 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1170 Chain = getChain(Call);
1171 OperFlag = getOutFlag(Call);
1172 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1174 Chain = getChain(SeqEnd);
1175 OperFlag = getOutFlag(SeqEnd);
1176 // Hi part of Data Address
1177 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1181 SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1182 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1183 SDValue Chain = TheCall->getChain();
1184 SDValue Callee = TheCall->getCallee();
1185 DebugLoc dl = TheCall->getDebugLoc();
1186 if (Callee.getValueType() == MVT::i16 &&
1187 Callee.getOpcode() == ISD::BUILD_PAIR) {
1188 // Control should come here only from TypeLegalizer for lowering
1190 // Legalize the non-legal arguments of call and return the
1191 // new call with legal arguments.
1192 return LegalizeCALL(Op, DAG);
1194 // Control should come here from Legalize DAG.
1195 // Here all the operands of CALL node should be legal.
1197 // If this is an indirect call then to pass the arguments
1198 // and read the return value back, we need the data address
1199 // of the function being called.
1200 // To get the data address two more calls need to be made.
1202 // The flag to track if this is a direct or indirect call.
1203 bool IsDirectCall = true;
1204 unsigned RetVals = TheCall->getNumRetVals();
1205 unsigned NumArgs = TheCall->getNumArgs();
1207 SDValue DataAddr_Lo, DataAddr_Hi;
1208 if (Callee.getOpcode() == PIC16ISD::PIC16Connect) {
1209 IsDirectCall = false; // This is indirect call
1210 // Read DataAddress only if we have to pass arguments or
1211 // read return value.
1212 if ((RetVals > 0) || (NumArgs > 0))
1213 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1216 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1218 // Start the call sequence.
1219 // Carring the Constant 0 along the CALLSEQSTART
1220 // because there is nothing else to carry.
1221 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1222 Chain = getChain(SeqStart);
1223 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1226 // For any direct call - callee will be GlobalAddressNode or
1228 SDValue ArgLabel, RetLabel;
1230 // Considering the GlobalAddressNode case here.
1231 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1232 GlobalValue *GV = G->getGlobal();
1233 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1234 Name = G->getGlobal()->getName();
1235 } else {// Considering the ExternalSymbol case here
1236 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1237 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1238 Name = ES->getSymbol();
1241 // Label for argument passing
1242 char *argFrame = new char [strlen(Name.c_str()) + 8];
1243 sprintf(argFrame, "%s.args", Name.c_str());
1244 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1246 // Label for reading return value
1247 char *retName = new char [strlen(Name.c_str()) + 8];
1248 sprintf(retName, "%s.retval", Name.c_str());
1249 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1252 SDValue CodeAddr_Lo = Callee.getOperand(0);
1253 SDValue CodeAddr_Hi = Callee.getOperand(1);
1255 CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1256 DAG.getConstant(2, MVT::i8));
1258 // move Hi part in PCLATH
1259 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1260 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1264 // Pass the argument to function before making the call.
1267 CallArgs = LowerDirectCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
1268 Chain = getChain(CallArgs);
1269 OperFlag = getOutFlag(CallArgs);
1271 CallArgs = LowerIndirectCallArguments(Op, Chain, OperFlag, DataAddr_Lo,
1273 Chain = getChain(CallArgs);
1274 OperFlag = getOutFlag(CallArgs);
1277 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1278 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1280 Chain = getChain(PICCall);
1281 OperFlag = getOutFlag(PICCall);
1284 // Carrying the Constant 0 along the CALLSEQSTART
1285 // because there is nothing else to carry.
1286 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1288 Chain = getChain(SeqEnd);
1289 OperFlag = getOutFlag(SeqEnd);
1291 // Lower the return value reading after the call.
1293 return LowerDirectCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
1295 return LowerIndirectCallReturn(Op, Chain, OperFlag, DataAddr_Lo,
1299 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1300 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1301 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1302 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1307 // NeedToConvertToMemOp - Returns true if one of the operands of the
1308 // operation 'Op' needs to be put into memory. Also returns the
1309 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1310 // no instruction that can operation on two registers. Most insns take
1311 // one register and one memory operand (addwf) / Constant (addlw).
1312 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1313 // If one of the operand is a constant, return false.
1314 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1315 Op.getOperand(1).getOpcode() == ISD::Constant)
1318 // Return false if one of the operands is already a direct
1319 // load and that operand has only one use.
1320 if (isDirectLoad(Op.getOperand(0))) {
1321 if (Op.getOperand(0).hasOneUse())
1326 if (isDirectLoad(Op.getOperand(1))) {
1327 if (Op.getOperand(1).hasOneUse())
1335 // LowerBinOp - Lower a commutative binary operation that does not
1336 // affect status flag carry.
1337 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1338 DebugLoc dl = Op.getDebugLoc();
1340 // We should have handled larger operands in type legalizer itself.
1341 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1344 if (NeedToConvertToMemOp(Op, MemOp)) {
1345 // Put one value on stack.
1346 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1348 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1356 // LowerADD - Lower all types of ADD operations including the ones
1357 // that affects carry.
1358 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1359 // We should have handled larger operands in type legalizer itself.
1360 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1361 DebugLoc dl = Op.getDebugLoc();
1363 if (NeedToConvertToMemOp(Op, MemOp)) {
1364 // Put one value on stack.
1365 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1367 // ADDC and ADDE produces two results.
1368 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1370 // ADDE has three operands, the last one is a flag.
1371 if (Op.getOpcode() == ISD::ADDE)
1372 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1373 NewVal, Op.getOperand(2));
1374 // ADDC has two operands.
1375 else if (Op.getOpcode() == ISD::ADDC)
1376 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1378 // ADD it is. It produces only one result.
1380 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1383 else if (Op.getOpcode() == ISD::ADD)
1389 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1390 DebugLoc dl = Op.getDebugLoc();
1391 // We should have handled larger operands in type legalizer itself.
1392 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1394 // Nothing to do if the first operand is already a direct load and it has
1396 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1399 // Put first operand on stack.
1400 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1402 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1403 if (Op.getOpcode() == ISD::SUBE)
1404 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1407 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1410 // LowerFORMAL_ARGUMENTS - Argument values are loaded from the
1411 // <fname>.args + offset. All arguments are already broken to leaglized
1412 // types, so the offset just runs from 0 to NumArgVals - 1.
1414 SDValue PIC16TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1415 SelectionDAG &DAG) {
1416 SmallVector<SDValue, 8> ArgValues;
1417 unsigned NumArgVals = Op.getNode()->getNumValues() - 1;
1418 DebugLoc dl = Op.getDebugLoc();
1419 SDValue Chain = Op.getOperand(0); // Formal arguments' chain
1422 // Reset the map of FI and TmpOffset
1423 ResetTmpOffsetMap();
1424 // Get the callee's name to create the <fname>.args label to pass args.
1425 MachineFunction &MF = DAG.getMachineFunction();
1426 const Function *F = MF.getFunction();
1427 std::string FuncName = F->getName();
1429 // Create the <fname>.args external symbol.
1430 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
1431 sprintf(tmpName, "%s.args", FuncName.c_str());
1432 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1434 // Load arg values from the label + offset.
1435 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1436 SDValue BS = DAG.getConstant(1, MVT::i8);
1437 for (unsigned i = 0; i < NumArgVals ; ++i) {
1438 SDValue Offset = DAG.getConstant(i, MVT::i8);
1439 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1441 Chain = getChain(PICLoad);
1442 ArgValues.push_back(PICLoad);
1445 // Return a MERGE_VALUE node.
1446 ArgValues.push_back(Op.getOperand(0));
1447 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1448 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1451 // Perform DAGCombine of PIC16Load.
1452 // FIXME - Need a more elaborate comment here.
1453 SDValue PIC16TargetLowering::
1454 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1455 SelectionDAG &DAG = DCI.DAG;
1456 SDValue Chain = N->getOperand(0);
1457 if (N->hasNUsesOfValue(0, 0)) {
1458 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1463 // For all the functions with arguments some STORE nodes are generated
1464 // that store the argument on the frameindex. However in PIC16 the arguments
1465 // are passed on stack only. Therefore these STORE nodes are redundant.
1466 // To remove these STORE nodes will be removed in PerformStoreCombine
1468 // Currently this function is doint nothing and will be updated for removing
1469 // unwanted store operations
1470 SDValue PIC16TargetLowering::
1471 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1472 return SDValue(N, 0);
1474 // Storing an undef value is of no use, so remove it
1475 if (isStoringUndef(N, Chain, DAG)) {
1476 return Chain; // remove the store and return the chain
1478 //else everything is ok.
1479 return SDValue(N, 0);
1483 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1484 DAGCombinerInfo &DCI) const {
1485 switch (N->getOpcode()) {
1487 return PerformStoreCombine(N, DCI);
1488 case PIC16ISD::PIC16Load:
1489 return PerformPIC16LoadCombine(N, DCI);
1494 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1496 default: assert(0 && "Unknown condition code!");
1497 case ISD::SETNE: return PIC16CC::NE;
1498 case ISD::SETEQ: return PIC16CC::EQ;
1499 case ISD::SETGT: return PIC16CC::GT;
1500 case ISD::SETGE: return PIC16CC::GE;
1501 case ISD::SETLT: return PIC16CC::LT;
1502 case ISD::SETLE: return PIC16CC::LE;
1503 case ISD::SETULT: return PIC16CC::ULT;
1504 case ISD::SETULE: return PIC16CC::LE;
1505 case ISD::SETUGE: return PIC16CC::GE;
1506 case ISD::SETUGT: return PIC16CC::UGT;
1510 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1511 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1512 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1513 ISD::CondCode CC, unsigned &SPCC) {
1514 if (isa<ConstantSDNode>(RHS) &&
1515 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1517 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1518 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1519 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1520 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1521 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1522 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1523 SDValue CMPCC = LHS.getOperand(3);
1524 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1525 LHS = CMPCC.getOperand(0);
1526 RHS = CMPCC.getOperand(1);
1530 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1531 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1532 unsigned CC, SDValue &PIC16CC,
1533 SelectionDAG &DAG, DebugLoc dl) {
1534 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1536 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1537 // i.e. a < 12 can be rewritten as 12 > a.
1538 if (RHS.getOpcode() == ISD::Constant) {
1547 CondCode = PIC16CC::GT;
1550 CondCode = PIC16CC::LT;
1553 CondCode = PIC16CC::UGT;
1556 CondCode = PIC16CC::ULT;
1559 CondCode = PIC16CC::LE;
1562 CondCode = PIC16CC::GE;
1565 CondCode = PIC16CC::UGE;
1568 CondCode = PIC16CC::ULE;
1573 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1575 // These are signed comparisons.
1576 SDValue Mask = DAG.getConstant(128, MVT::i8);
1577 if (isSignedComparison(CondCode)) {
1578 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1579 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1582 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1583 // We can use a subtract operation to set the condition codes. But
1584 // we need to put one operand in memory if required.
1585 // Nothing to do if the first operand is already a valid type (direct load
1586 // for subwf and literal for sublw) and it is used by this operation only.
1587 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1589 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1591 // else convert the first operand to mem.
1592 LHS = ConvertToMemOperand (LHS, DAG, dl);
1593 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1597 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1598 SDValue LHS = Op.getOperand(0);
1599 SDValue RHS = Op.getOperand(1);
1600 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1601 SDValue TrueVal = Op.getOperand(2);
1602 SDValue FalseVal = Op.getOperand(3);
1603 unsigned ORIGCC = ~0;
1604 DebugLoc dl = Op.getDebugLoc();
1606 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1607 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1609 // A setcc: lhs, rhs, cc is expanded by llvm to
1610 // select_cc: result of setcc, 0, 1, 0, setne
1611 // We can think of it as:
1612 // select_cc: lhs, rhs, 1, 0, cc
1613 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1614 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1617 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1619 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1620 FalseVal, PIC16CC, Cmp.getValue(1));
1624 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1625 MachineBasicBlock *BB) const {
1626 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1627 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1628 DebugLoc dl = MI->getDebugLoc();
1630 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1631 // control-flow pattern. The incoming instruction knows the destination vreg
1632 // to set, the condition code register to branch on, the true/false values to
1633 // select between, and a branch opcode to use.
1634 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1635 MachineFunction::iterator It = BB;
1642 // fallthrough --> copy0MBB
1643 MachineBasicBlock *thisMBB = BB;
1644 MachineFunction *F = BB->getParent();
1645 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1646 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1647 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1648 F->insert(It, copy0MBB);
1649 F->insert(It, sinkMBB);
1651 // Update machine-CFG edges by transferring all successors of the current
1652 // block to the new block which will contain the Phi node for the select.
1653 sinkMBB->transferSuccessors(BB);
1654 // Next, add the true and fallthrough blocks as its successors.
1655 BB->addSuccessor(copy0MBB);
1656 BB->addSuccessor(sinkMBB);
1659 // %FalseValue = ...
1660 // # fallthrough to sinkMBB
1663 // Update machine-CFG edges
1664 BB->addSuccessor(sinkMBB);
1667 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1670 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1671 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1672 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1674 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1679 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1680 SDValue Chain = Op.getOperand(0);
1681 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1682 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1683 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1684 SDValue Dest = Op.getOperand(4); // BB to jump to
1685 unsigned ORIGCC = ~0;
1686 DebugLoc dl = Op.getDebugLoc();
1688 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1689 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1690 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1691 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1693 // Get the Compare insn and condition code.
1695 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1697 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,