2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
15 #include "PIC16ISelLowering.h"
16 #include "PIC16TargetObjectFile.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
31 static const char *getIntrinsicName(unsigned opcode) {
34 default: llvm_unreachable("do not know intrinsic name");
35 // Arithmetic Right shift for integer types.
36 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
37 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
38 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
40 // Left shift for integer types.
41 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
42 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
43 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
45 // Logical Right Shift for integer types.
46 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
47 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
48 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
50 // Multiply for integer types.
51 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
52 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
53 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
55 // Signed division for integers.
56 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
57 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
59 // Unsigned division for integers.
60 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
61 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
63 // Signed Modulas for integers.
64 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
65 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
67 // Unsigned Modulas for integers.
68 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
69 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
71 //////////////////////
72 // LIBCALLS FOR FLOATS
73 //////////////////////
75 // Float to signed integrals
76 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
77 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
78 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
80 // Signed integrals to float. char and int are first sign extended to i32
81 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
82 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
84 // Float to Unsigned conversions.
85 // Signed conversion can be used for unsigned conversion as well.
86 // In signed and unsigned versions only the interpretation of the
87 // MSB is different. Bit representation remains the same.
88 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
89 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
90 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
92 // Unsigned to Float conversions. char and int are first zero extended
93 // before being converted to float.
94 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
96 // Floating point add, sub, mul, div.
97 case RTLIB::ADD_F32: Basename = "add.f32"; break;
98 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
99 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
100 case RTLIB::DIV_F32: Basename = "div.f32"; break;
102 // Floating point comparison
103 case RTLIB::O_F32: Basename = "unordered.f32"; break;
104 case RTLIB::UO_F32: Basename = "unordered.f32"; break;
105 case RTLIB::OLE_F32: Basename = "le.f32"; break;
106 case RTLIB::OGE_F32: Basename = "ge.f32"; break;
107 case RTLIB::OLT_F32: Basename = "lt.f32"; break;
108 case RTLIB::OGT_F32: Basename = "gt.f32"; break;
109 case RTLIB::OEQ_F32: Basename = "eq.f32"; break;
110 case RTLIB::UNE_F32: Basename = "neq.f32"; break;
113 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
114 std::string tagname = PAN::getTagName(PAN::LIBCALL);
115 std::string Fullname = prefix + tagname + Basename;
117 // The name has to live through program life.
118 return createESName(Fullname);
121 // getStdLibCallName - Get the name for the standard library function.
122 static const char *getStdLibCallName(unsigned opcode) {
123 std::string BaseName;
125 case RTLIB::COS_F32: BaseName = "cos";
127 case RTLIB::SIN_F32: BaseName = "sin";
129 case RTLIB::MEMCPY: BaseName = "memcpy";
131 case RTLIB::MEMSET: BaseName = "memset";
133 case RTLIB::MEMMOVE: BaseName = "memmove";
135 default: llvm_unreachable("do not know std lib call name");
137 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
138 std::string LibCallName = prefix + BaseName;
140 // The name has to live through program life.
141 return createESName(LibCallName);
144 // PIC16TargetLowering Constructor.
145 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
146 : TargetLowering(TM, new PIC16TargetObjectFile()), TmpSize(0) {
148 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
150 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
152 setShiftAmountType(MVT::i8);
154 // Std lib call names
155 setLibcallName(RTLIB::COS_F32, getStdLibCallName(RTLIB::COS_F32));
156 setLibcallName(RTLIB::SIN_F32, getStdLibCallName(RTLIB::SIN_F32));
157 setLibcallName(RTLIB::MEMCPY, getStdLibCallName(RTLIB::MEMCPY));
158 setLibcallName(RTLIB::MEMSET, getStdLibCallName(RTLIB::MEMSET));
159 setLibcallName(RTLIB::MEMMOVE, getStdLibCallName(RTLIB::MEMMOVE));
161 // SRA library call names
162 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
163 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
164 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
166 // SHL library call names
167 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
168 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
169 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
171 // SRL library call names
172 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
173 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
174 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
176 // MUL Library call names
177 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
178 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
179 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
181 // Signed division lib call names
182 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
183 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
185 // Unsigned division lib call names
186 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
187 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
189 // Signed remainder lib call names
190 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
191 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
193 // Unsigned remainder lib call names
194 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
195 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
197 // Floating point to signed int conversions.
198 setLibcallName(RTLIB::FPTOSINT_F32_I8,
199 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
200 setLibcallName(RTLIB::FPTOSINT_F32_I16,
201 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
202 setLibcallName(RTLIB::FPTOSINT_F32_I32,
203 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
205 // Signed int to floats.
206 setLibcallName(RTLIB::SINTTOFP_I32_F32,
207 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
209 // Floating points to unsigned ints.
210 setLibcallName(RTLIB::FPTOUINT_F32_I8,
211 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
212 setLibcallName(RTLIB::FPTOUINT_F32_I16,
213 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
214 setLibcallName(RTLIB::FPTOUINT_F32_I32,
215 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
217 // Unsigned int to floats.
218 setLibcallName(RTLIB::UINTTOFP_I32_F32,
219 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
221 // Floating point add, sub, mul ,div.
222 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
223 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
224 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
225 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
227 // Floationg point comparison
228 setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32));
229 setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32));
230 setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32));
231 setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32));
232 setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32));
233 setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32));
234 setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32));
236 // Return value comparisons of floating point calls.
237 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
238 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
239 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
240 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
241 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
242 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
243 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
244 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
246 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
247 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
249 setOperationAction(ISD::LOAD, MVT::i8, Legal);
250 setOperationAction(ISD::LOAD, MVT::i16, Custom);
251 setOperationAction(ISD::LOAD, MVT::i32, Custom);
253 setOperationAction(ISD::STORE, MVT::i8, Legal);
254 setOperationAction(ISD::STORE, MVT::i16, Custom);
255 setOperationAction(ISD::STORE, MVT::i32, Custom);
257 setOperationAction(ISD::ADDE, MVT::i8, Custom);
258 setOperationAction(ISD::ADDC, MVT::i8, Custom);
259 setOperationAction(ISD::SUBE, MVT::i8, Custom);
260 setOperationAction(ISD::SUBC, MVT::i8, Custom);
261 setOperationAction(ISD::SUB, MVT::i8, Custom);
262 setOperationAction(ISD::ADD, MVT::i8, Custom);
263 setOperationAction(ISD::ADD, MVT::i16, Custom);
265 setOperationAction(ISD::OR, MVT::i8, Custom);
266 setOperationAction(ISD::AND, MVT::i8, Custom);
267 setOperationAction(ISD::XOR, MVT::i8, Custom);
269 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
270 setOperationAction(ISD::CALL, MVT::i16, Custom);
271 setOperationAction(ISD::RET, MVT::Other, Custom);
273 setOperationAction(ISD::MUL, MVT::i8, Custom);
275 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
276 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
277 setOperationAction(ISD::MULHU, MVT::i8, Expand);
278 setOperationAction(ISD::MULHS, MVT::i8, Expand);
280 setOperationAction(ISD::SRA, MVT::i8, Custom);
281 setOperationAction(ISD::SHL, MVT::i8, Custom);
282 setOperationAction(ISD::SRL, MVT::i8, Custom);
284 setOperationAction(ISD::ROTL, MVT::i8, Expand);
285 setOperationAction(ISD::ROTR, MVT::i8, Expand);
287 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
289 // PIC16 does not support shift parts
290 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
291 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
292 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
295 // PIC16 does not have a SETCC, expand it to SELECT_CC.
296 setOperationAction(ISD::SETCC, MVT::i8, Expand);
297 setOperationAction(ISD::SELECT, MVT::i8, Expand);
298 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
299 setOperationAction(ISD::BRIND, MVT::Other, Expand);
301 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
302 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
304 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
305 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
307 // Now deduce the information based on the above mentioned
309 computeRegisterProperties();
312 // getOutFlag - Extract the flag result if the Op has it.
313 static SDValue getOutFlag(SDValue &Op) {
314 // Flag is the last value of the node.
315 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
317 assert (Flag.getValueType() == MVT::Flag
318 && "Node does not have an out Flag");
322 // Get the TmpOffset for FrameIndex
323 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
324 std::map<unsigned, unsigned>::iterator
325 MapIt = FiTmpOffsetMap.find(FI);
326 if (MapIt != FiTmpOffsetMap.end())
327 return MapIt->second;
329 // This FI (FrameIndex) is not yet mapped, so map it
330 FiTmpOffsetMap[FI] = TmpSize;
332 return FiTmpOffsetMap[FI];
335 // To extract chain value from the SDValue Nodes
336 // This function will help to maintain the chain extracting
337 // code at one place. In case of any change in future it will
338 // help maintain the code.
339 static SDValue getChain(SDValue &Op) {
340 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
342 // If the last value returned in Flag then the chain is
343 // second last value returned.
344 if (Chain.getValueType() == MVT::Flag)
345 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
347 // All nodes may not produce a chain. Therefore following assert
348 // verifies that the node is returning a chain only.
349 assert (Chain.getValueType() == MVT::Other
350 && "Node does not have a chain");
355 /// PopulateResults - Helper function to LowerOperation.
356 /// If a node wants to return multiple results after lowering,
357 /// it stuffs them into an array of SDValue called Results.
359 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
360 if (N.getOpcode() == ISD::MERGE_VALUES) {
361 int NumResults = N.getNumOperands();
362 for( int i = 0; i < NumResults; i++)
363 Results.push_back(N.getOperand(i));
366 Results.push_back(N);
369 MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
373 /// The type legalizer framework of generating legalizer can generate libcalls
374 /// only when the operand/result types are illegal.
375 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
376 /// For example an arithmetic right shift. These functions are used to lower
377 /// such operations that generate libcall for legal types.
380 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
382 PIC16LibcallNames[Call] = Name;
386 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
387 return PIC16LibcallNames[Call];
391 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
392 MVT RetVT, const SDValue *Ops,
393 unsigned NumOps, bool isSigned,
394 SelectionDAG &DAG, DebugLoc dl) {
396 TargetLowering::ArgListTy Args;
397 Args.reserve(NumOps);
399 TargetLowering::ArgListEntry Entry;
400 for (unsigned i = 0; i != NumOps; ++i) {
402 Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
403 Entry.isSExt = isSigned;
404 Entry.isZExt = !isSigned;
405 Args.push_back(Entry);
407 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
409 const Type *RetTy = RetVT.getTypeForMVT();
410 std::pair<SDValue,SDValue> CallInfo =
411 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
412 false, 0, CallingConv::C, false, Callee, Args, DAG, dl);
414 return CallInfo.first;
417 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
419 default: return NULL;
420 case PIC16ISD::Lo: return "PIC16ISD::Lo";
421 case PIC16ISD::Hi: return "PIC16ISD::Hi";
422 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
423 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
424 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
425 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
426 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
427 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
428 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
429 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
430 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
431 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
432 case PIC16ISD::BCF: return "PIC16ISD::BCF";
433 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
434 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
435 case PIC16ISD::RLF: return "PIC16ISD::RLF";
436 case PIC16ISD::RRF: return "PIC16ISD::RRF";
437 case PIC16ISD::CALL: return "PIC16ISD::CALL";
438 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
439 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
440 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
441 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
442 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
446 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
447 SmallVectorImpl<SDValue>&Results,
450 switch (N->getOpcode()) {
451 case ISD::GlobalAddress:
452 Results.push_back(ExpandGlobalAddress(N, DAG));
454 case ISD::ExternalSymbol:
455 Results.push_back(ExpandExternalSymbol(N, DAG));
458 Results.push_back(ExpandStore(N, DAG));
461 PopulateResults(ExpandLoad(N, DAG), Results);
464 // Results.push_back(ExpandAdd(N, DAG));
466 case ISD::FrameIndex:
467 Results.push_back(ExpandFrameIndex(N, DAG));
470 assert (0 && "not implemented");
475 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
477 // Currently handling FrameIndex of size MVT::i16 only
478 // One example of this scenario is when return value is written on
481 if (N->getValueType(0) != MVT::i16)
484 // Expand the FrameIndex into ExternalSymbol and a Constant node
485 // The constant will represent the frame index number
486 // Get the current function frame
487 MachineFunction &MF = DAG.getMachineFunction();
488 const Function *Func = MF.getFunction();
489 const std::string Name = Func->getName();
491 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
492 // FIXME there isn't really debug info here
493 DebugLoc dl = FR->getDebugLoc();
495 // Expand FrameIndex like GlobalAddress and ExternalSymbol
496 // Also use Offset field for lo and hi parts. The default
501 SDValue FI = SDValue(N,0);
502 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
503 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
504 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
505 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
506 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
510 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
511 StoreSDNode *St = cast<StoreSDNode>(N);
512 SDValue Chain = St->getChain();
513 SDValue Src = St->getValue();
514 SDValue Ptr = St->getBasePtr();
515 MVT ValueType = Src.getValueType();
516 unsigned StoreOffset = 0;
517 DebugLoc dl = N->getDebugLoc();
519 SDValue PtrLo, PtrHi;
520 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
522 if (ValueType == MVT::i8) {
523 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
525 DAG.getConstant (0 + StoreOffset, MVT::i8));
527 else if (ValueType == MVT::i16) {
528 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
529 SDValue SrcLo, SrcHi;
530 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
531 SDValue ChainLo = Chain, ChainHi = Chain;
532 if (Chain.getOpcode() == ISD::TokenFactor) {
533 ChainLo = Chain.getOperand(0);
534 ChainHi = Chain.getOperand(1);
536 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
539 DAG.getConstant (0 + StoreOffset, MVT::i8));
541 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
543 DAG.getConstant (1 + StoreOffset, MVT::i8));
545 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
548 else if (ValueType == MVT::i32) {
549 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
550 SDValue SrcLo, SrcHi;
551 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
553 // Get the expanded parts of each of SrcLo and SrcHi.
554 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
555 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
556 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
558 SDValue ChainLo = Chain, ChainHi = Chain;
559 if (Chain.getOpcode() == ISD::TokenFactor) {
560 ChainLo = Chain.getOperand(0);
561 ChainHi = Chain.getOperand(1);
563 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
565 if (ChainLo.getOpcode() == ISD::TokenFactor) {
566 ChainLo1 = ChainLo.getOperand(0);
567 ChainLo2 = ChainLo.getOperand(1);
569 if (ChainHi.getOpcode() == ISD::TokenFactor) {
570 ChainHi1 = ChainHi.getOperand(0);
571 ChainHi2 = ChainHi.getOperand(1);
573 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
575 SrcLo1, PtrLo, PtrHi,
576 DAG.getConstant (0 + StoreOffset, MVT::i8));
578 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
579 SrcLo2, PtrLo, PtrHi,
580 DAG.getConstant (1 + StoreOffset, MVT::i8));
582 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
583 SrcHi1, PtrLo, PtrHi,
584 DAG.getConstant (2 + StoreOffset, MVT::i8));
586 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
587 SrcHi2, PtrLo, PtrHi,
588 DAG.getConstant (3 + StoreOffset, MVT::i8));
590 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
591 getChain(Store1), getChain(Store2));
592 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
593 getChain(Store3), getChain(Store4));
594 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
598 assert (0 && "value type not supported");
603 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
605 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
606 // FIXME there isn't really debug info here
607 DebugLoc dl = ES->getDebugLoc();
609 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
610 SDValue Offset = DAG.getConstant(0, MVT::i8);
611 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
612 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
614 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
617 // ExpandGlobalAddress -
618 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
619 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
620 // FIXME there isn't really debug info here
621 DebugLoc dl = G->getDebugLoc();
623 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
626 SDValue Offset = DAG.getConstant(0, MVT::i8);
627 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
628 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
630 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
633 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
634 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
636 if (Op.getOpcode() == ISD::BUILD_PAIR) {
637 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
643 // Return true if DirectAddress is in ROM_SPACE
644 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
646 // RomAddress is a GlobalAddress in ROM_SPACE_
647 // If the Op is not a GlobalAddress return NULL without checking
649 if (!isDirectAddress(Op))
652 // Its a GlobalAddress.
653 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
654 SDValue TGA = Op.getOperand(0).getOperand(0);
655 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
657 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
660 // Any other address space return it false
665 // GetExpandedParts - This function is on the similiar lines as
666 // the GetExpandedInteger in type legalizer is. This returns expanded
667 // parts of Op in Lo and Hi.
669 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
670 SDValue &Lo, SDValue &Hi) {
671 SDNode *N = Op.getNode();
672 DebugLoc dl = N->getDebugLoc();
673 MVT NewVT = getTypeToTransformTo(N->getValueType(0));
675 // Extract the lo component.
676 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
677 DAG.getConstant(0, MVT::i8));
679 // extract the hi component
680 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
681 DAG.getConstant(1, MVT::i8));
684 // Legalize FrameIndex into ExternalSymbol and offset.
686 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
687 SDValue &ES, int &Offset) {
689 MachineFunction &MF = DAG.getMachineFunction();
690 const Function *Func = MF.getFunction();
691 MachineFrameInfo *MFI = MF.getFrameInfo();
692 const std::string Name = Func->getName();
694 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
696 // FrameIndices are not stack offsets. But they represent the request
697 // for space on stack. That space requested may be more than one byte.
698 // Therefore, to calculate the stack offset that a FrameIndex aligns
699 // with, we need to traverse all the FrameIndices available earlier in
700 // the list and add their requested size.
701 unsigned FIndex = FR->getIndex();
703 if (FIndex < ReservedFrameCount) {
704 tmpName = createESName(PAN::getFrameLabel(Name));
705 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
707 for (unsigned i=0; i<FIndex ; ++i) {
708 Offset += MFI->getObjectSize(i);
711 // FrameIndex has been made for some temporary storage
712 tmpName = createESName(PAN::getTempdataLabel(Name));
713 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
714 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
720 // This function legalizes the PIC16 Addresses. If the Pointer is
721 // -- Direct address variable residing
722 // --> then a Banksel for that variable will be created.
724 // --> then it will be treated as an indirect address.
725 // -- Indirect address
726 // --> then the address will be loaded into FSR
727 // -- ADD with constant operand
728 // --> then constant operand of ADD will be returned as Offset
729 // and non-constant operand of ADD will be treated as pointer.
730 // Returns the high and lo part of the address, and the offset(in case of ADD).
732 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
733 SDValue &Lo, SDValue &Hi,
734 unsigned &Offset, DebugLoc dl) {
736 // Offset, by default, should be 0
739 // If the pointer is ADD with constant,
740 // return the constant value as the offset
741 if (Ptr.getOpcode() == ISD::ADD) {
742 SDValue OperLeft = Ptr.getOperand(0);
743 SDValue OperRight = Ptr.getOperand(1);
744 if ((OperLeft.getOpcode() == ISD::Constant) &&
745 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
746 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
748 } else if ((OperRight.getOpcode() == ISD::Constant) &&
749 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
750 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
755 // If the pointer is Type i8 and an external symbol
756 // then treat it as direct address.
757 // One example for such case is storing and loading
758 // from function frame during a call
759 if (Ptr.getValueType() == MVT::i8) {
760 switch (Ptr.getOpcode()) {
761 case ISD::TargetExternalSymbol:
763 Hi = DAG.getConstant(1, MVT::i8);
768 // Expansion of FrameIndex has Lo/Hi parts
769 if (isDirectAddress(Ptr)) {
770 SDValue TFI = Ptr.getOperand(0).getOperand(0);
772 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
773 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
774 Hi = DAG.getConstant(1, MVT::i8);
775 Offset += FrameOffset;
777 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
778 // FrameIndex has already been expanded.
779 // Now just make use of its expansion
781 Hi = DAG.getConstant(1, MVT::i8);
782 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
783 assert (FOffset.getOpcode() == ISD::Constant &&
784 "Invalid operand of PIC16ISD::Lo");
785 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
790 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
791 // Direct addressing case for RAM variables. The Hi part is constant
792 // and the Lo part is the TGA itself.
793 Lo = Ptr.getOperand(0).getOperand(0);
795 // For direct addresses Hi is a constant. Value 1 for the constant
796 // signifies that banksel needs to generated for it. Value 0 for
797 // the constant signifies that banksel does not need to be generated
798 // for it. Mark it as 1 now and optimize later.
799 Hi = DAG.getConstant(1, MVT::i8);
803 // Indirect addresses. Get the hi and lo parts of ptr.
804 GetExpandedParts(Ptr, DAG, Lo, Hi);
806 // Put the hi and lo parts into FSR.
807 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
808 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
813 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
814 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
815 SDValue Chain = LD->getChain();
816 SDValue Ptr = LD->getBasePtr();
817 DebugLoc dl = LD->getDebugLoc();
819 SDValue Load, Offset;
822 SDValue PtrLo, PtrHi;
825 // Legalize direct/indirect addresses. This will give the lo and hi parts
826 // of the address and the offset.
827 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
829 // Load from the pointer (direct address or FSR)
830 VT = N->getValueType(0);
831 unsigned NumLoads = VT.getSizeInBits() / 8;
832 std::vector<SDValue> PICLoads;
834 MVT MemVT = LD->getMemoryVT();
835 if(ISD::isNON_EXTLoad(N)) {
836 for (iter=0; iter<NumLoads ; ++iter) {
837 // Add the pointer offset if any
838 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
839 Tys = DAG.getVTList(MVT::i8, MVT::Other);
840 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
842 PICLoads.push_back(Load);
845 // If it is extended load then use PIC16Load for Memory Bytes
846 // and for all extended bytes perform action based on type of
847 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
850 // For extended loads this is the memory value type
851 // i.e. without any extension
852 MVT MemVT = LD->getMemoryVT();
853 unsigned MemBytes = MemVT.getSizeInBits() / 8;
854 // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
856 if (MemBytes == 0) MemBytes = 1;
858 unsigned ExtdBytes = VT.getSizeInBits() / 8;
859 Offset = DAG.getConstant(LoadOffset, MVT::i8);
861 Tys = DAG.getVTList(MVT::i8, MVT::Other);
862 // For MemBytes generate PIC16Load with proper offset
863 for (iter=0; iter < MemBytes; ++iter) {
864 // Add the pointer offset if any
865 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
866 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
868 PICLoads.push_back(Load);
871 // For SignExtendedLoad
872 if (ISD::isSEXTLoad(N)) {
873 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
875 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
876 DAG.getConstant(7, MVT::i8));
877 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
878 PICLoads.push_back(SRA);
880 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
881 //} else if (ISD::isZEXTLoad(N)) {
882 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
883 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
884 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
885 PICLoads.push_back(ConstZero);
892 // Operand of Load is illegal -- Load itself is legal
895 else if (VT == MVT::i16) {
896 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
897 if (MemVT == MVT::i8)
898 Chain = getChain(PICLoads[0]);
900 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
901 getChain(PICLoads[0]), getChain(PICLoads[1]));
902 } else if (VT == MVT::i32) {
904 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
905 PICLoads[0], PICLoads[1]);
906 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
907 PICLoads[2], PICLoads[3]);
908 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
909 if (MemVT == MVT::i8)
910 Chain = getChain(PICLoads[0]);
911 else if (MemVT == MVT::i16)
912 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
913 getChain(PICLoads[0]), getChain(PICLoads[1]));
916 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
917 getChain(PICLoads[0]), getChain(PICLoads[1]));
918 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
919 getChain(PICLoads[2]), getChain(PICLoads[3]));
920 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
921 Chains[0], Chains[1]);
924 Tys = DAG.getVTList(VT, MVT::Other);
925 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
928 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
929 // We should have handled larger operands in type legalizer itself.
930 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
932 SDNode *N = Op.getNode();
933 SDValue Value = N->getOperand(0);
934 SDValue Amt = N->getOperand(1);
935 PIC16ISD::PIC16Libcall CallCode;
936 switch (N->getOpcode()) {
938 CallCode = PIC16ISD::SRA_I8;
941 CallCode = PIC16ISD::SLL_I8;
944 CallCode = PIC16ISD::SRL_I8;
947 assert ( 0 && "This shift is not implemented yet.");
950 SmallVector<SDValue, 2> Ops(2);
953 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
954 true, DAG, N->getDebugLoc());
958 SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
959 // We should have handled larger operands in type legalizer itself.
960 assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
962 SDNode *N = Op.getNode();
963 SmallVector<SDValue, 2> Ops(2);
964 Ops[0] = N->getOperand(0);
965 Ops[1] = N->getOperand(1);
966 SDValue Call = MakePIC16Libcall(PIC16ISD::MUL_I8, N->getValueType(0),
967 &Ops[0], 2, true, DAG, N->getDebugLoc());
972 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
973 SmallVectorImpl<SDValue>&Results,
975 SDValue Op = SDValue(N, 0);
978 switch (Op.getOpcode()) {
979 case ISD::FORMAL_ARGUMENTS:
980 Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
982 Res = ExpandLoad(Op.getNode(), DAG); break;
984 Res = LowerCALL(Op, DAG); break;
986 // All other operations are handled in LowerOperation.
987 Res = LowerOperation(Op, DAG);
989 Results.push_back(Res);
996 unsigned NumValues = N->getNumValues();
997 for (i = 0; i < NumValues ; i++) {
998 Results.push_back(SDValue(N, i));
1002 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1003 switch (Op.getOpcode()) {
1004 case ISD::FORMAL_ARGUMENTS:
1005 return LowerFORMAL_ARGUMENTS(Op, DAG);
1009 return LowerADD(Op, DAG);
1013 return LowerSUB(Op, DAG);
1015 return ExpandLoad(Op.getNode(), DAG);
1017 return ExpandStore(Op.getNode(), DAG);
1019 return LowerMUL(Op, DAG);
1023 return LowerShift(Op, DAG);
1027 return LowerBinOp(Op, DAG);
1029 return LowerCALL(Op, DAG);
1031 return LowerRET(Op, DAG);
1033 return LowerBR_CC(Op, DAG);
1034 case ISD::SELECT_CC:
1035 return LowerSELECT_CC(Op, DAG);
1040 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
1043 assert (Op.getValueType() == MVT::i8
1044 && "illegal value type to store on stack.");
1046 MachineFunction &MF = DAG.getMachineFunction();
1047 const Function *Func = MF.getFunction();
1048 const std::string FuncName = Func->getName();
1051 // Put the value on stack.
1052 // Get a stack slot index and convert to es.
1053 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
1054 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
1055 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1057 // Store the value to ES.
1058 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1061 DAG.getConstant (1, MVT::i8), // Banksel.
1062 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1065 // Load the value from ES.
1066 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1067 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1068 ES, DAG.getConstant (1, MVT::i8),
1069 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1072 return Load.getValue(0);
1075 SDValue PIC16TargetLowering::
1076 LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag,
1077 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1078 SelectionDAG &DAG) {
1079 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1080 unsigned NumOps = TheCall->getNumArgs();
1081 DebugLoc dl = TheCall->getDebugLoc();
1083 // If call has no arguments then do nothing and return.
1087 std::vector<SDValue> Ops;
1088 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1089 SDValue Arg, StoreRet;
1091 // For PIC16 ABI the arguments come after the return value.
1092 unsigned RetVals = TheCall->getNumRetVals();
1093 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1094 // Get the arguments
1095 Arg = TheCall->getArg(i);
1098 Ops.push_back(Chain);
1100 Ops.push_back(DataAddr_Lo);
1101 Ops.push_back(DataAddr_Hi);
1102 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1103 Ops.push_back(InFlag);
1105 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1107 Chain = getChain(StoreRet);
1108 InFlag = getOutFlag(StoreRet);
1114 SDValue PIC16TargetLowering::
1115 LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue ArgLabel,
1116 SDValue InFlag, SelectionDAG &DAG) {
1117 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1118 unsigned NumOps = TheCall->getNumArgs();
1119 DebugLoc dl = TheCall->getDebugLoc();
1121 SDValue Arg, StoreAt;
1124 unsigned ArgCount=0;
1126 // If call has no arguments then do nothing and return.
1130 // FIXME: This portion of code currently assumes only
1131 // primitive types being passed as arguments.
1133 // Legalize the address before use
1134 SDValue PtrLo, PtrHi;
1135 unsigned AddressOffset;
1136 int StoreOffset = 0;
1137 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1140 std::vector<SDValue> Ops;
1141 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1142 for (unsigned i=ArgCount, Offset = 0; i<NumOps; i++) {
1144 Arg = TheCall->getArg(i);
1145 StoreOffset = (Offset + AddressOffset);
1147 // Store the argument on frame
1150 Ops.push_back(Chain);
1152 Ops.push_back(PtrLo);
1153 Ops.push_back(PtrHi);
1154 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1155 Ops.push_back(InFlag);
1157 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1159 Chain = getChain(StoreRet);
1160 InFlag = getOutFlag(StoreRet);
1162 // Update the frame offset to be used for next argument
1163 ArgVT = Arg.getValueType();
1164 Size = ArgVT.getSizeInBits();
1165 Size = Size/8; // Calculate size in bytes
1166 Offset += Size; // Increase the frame offset
1171 SDValue PIC16TargetLowering::
1172 LowerIndirectCallReturn (SDValue Op, SDValue Chain, SDValue InFlag,
1173 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1174 SelectionDAG &DAG) {
1175 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1176 DebugLoc dl = TheCall->getDebugLoc();
1177 unsigned RetVals = TheCall->getNumRetVals();
1179 // If call does not have anything to return
1180 // then do nothing and go back.
1184 // Call has something to return
1185 std::vector<SDValue> ResultVals;
1188 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1189 for(unsigned i=0;i<RetVals;i++) {
1190 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1191 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1193 InFlag = getOutFlag(LoadRet);
1194 Chain = getChain(LoadRet);
1195 ResultVals.push_back(LoadRet);
1197 ResultVals.push_back(Chain);
1198 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1202 SDValue PIC16TargetLowering::
1203 LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue RetLabel,
1204 SDValue InFlag, SelectionDAG &DAG) {
1205 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1206 DebugLoc dl = TheCall->getDebugLoc();
1207 // Currently handling primitive types only. They will come in
1209 unsigned RetVals = TheCall->getNumRetVals();
1211 std::vector<SDValue> ResultVals;
1213 // Return immediately if the return type is void
1217 // Call has something to return
1219 // Legalize the address before use
1222 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1224 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1227 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1229 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1230 DAG.getConstant(LdOffset + Offset, MVT::i8),
1233 InFlag = getOutFlag(LoadRet);
1235 Chain = getChain(LoadRet);
1237 ResultVals.push_back(LoadRet);
1240 // To return use MERGE_VALUES
1241 ResultVals.push_back(Chain);
1242 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1246 SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1247 SDValue Chain = Op.getOperand(0);
1248 DebugLoc dl = Op.getDebugLoc();
1250 if (Op.getNumOperands() == 1) // return void
1253 // return should have odd number of operands
1254 if ((Op.getNumOperands() % 2) == 0 ) {
1255 llvm_unreachable("Do not know how to return this many arguments!");
1258 // Number of values to return
1259 unsigned NumRet = (Op.getNumOperands() / 2);
1261 // Function returns value always on stack with the offset starting
1263 MachineFunction &MF = DAG.getMachineFunction();
1264 const Function *F = MF.getFunction();
1265 std::string FuncName = F->getName();
1267 const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
1268 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1269 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1270 SDValue BS = DAG.getConstant(1, MVT::i8);
1272 for(unsigned i=0;i<NumRet; ++i) {
1273 RetVal = Op.getNode()->getOperand(2*i + 1);
1274 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1276 DAG.getConstant (i, MVT::i8));
1279 return DAG.getNode(ISD::RET, dl, MVT::Other, Chain);
1282 // CALL node may have some operands non-legal to PIC16. Generate new CALL
1283 // node with all the operands legal.
1284 // Currently only Callee operand of the CALL node is non-legal. This function
1285 // legalizes the Callee operand and uses all other operands as are to generate
1288 SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) {
1289 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1290 SDValue Chain = TheCall->getChain();
1291 SDValue Callee = TheCall->getCallee();
1292 DebugLoc dl = TheCall->getDebugLoc();
1295 assert(Callee.getValueType() == MVT::i16 &&
1296 "Don't know how to legalize this call node!!!");
1297 assert(Callee.getOpcode() == ISD::BUILD_PAIR &&
1298 "Don't know how to legalize this call node!!!");
1300 if (isDirectAddress(Callee)) {
1301 // Come here for direct calls
1302 Callee = Callee.getOperand(0).getOperand(0);
1304 // Come here for indirect calls
1306 // Indirect addresses. Get the hi and lo parts of ptr.
1307 GetExpandedParts(Callee, DAG, Lo, Hi);
1308 // Connect Lo and Hi parts of the callee with the PIC16Connect
1309 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1311 std::vector<SDValue> Ops;
1312 Ops.push_back(Chain);
1313 Ops.push_back(Callee);
1315 // Add the call arguments and their flags
1316 unsigned NumArgs = TheCall->getNumArgs();
1317 for(i=0;i<NumArgs;i++) {
1318 Ops.push_back(TheCall->getArg(i));
1319 Ops.push_back(TheCall->getArgFlagsVal(i));
1321 std::vector<MVT> NodeTys;
1322 unsigned NumRets = TheCall->getNumRetVals();
1323 for(i=0;i<NumRets;i++)
1324 NodeTys.push_back(TheCall->getRetValType(i));
1326 // Return a Chain as well
1327 NodeTys.push_back(MVT::Other);
1329 SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
1330 // Generate new call with all the operands legal
1331 return DAG.getCall(TheCall->getCallingConv(), dl,
1332 TheCall->isVarArg(), TheCall->isTailCall(),
1333 TheCall->isInreg(), VTs, &Ops[0], Ops.size(),
1334 TheCall->getNumFixedArgs());
1337 void PIC16TargetLowering::
1338 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1339 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1340 SelectionDAG &DAG) {
1341 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1342 && "Don't know what to do of such callee!!");
1343 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1344 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1345 Chain = getChain(SeqStart);
1346 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1348 // Get the Lo and Hi part of code address
1349 SDValue Lo = Callee.getOperand(0);
1350 SDValue Hi = Callee.getOperand(1);
1352 SDValue Data_Lo, Data_Hi;
1353 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1354 // Subtract 2 from Address to get the Lower part of DataAddress.
1355 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1356 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1357 DAG.getConstant(2, MVT::i8));
1358 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1359 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1360 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1361 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1362 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1364 Chain = getChain(Call);
1365 OperFlag = getOutFlag(Call);
1366 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1368 Chain = getChain(SeqEnd);
1369 OperFlag = getOutFlag(SeqEnd);
1371 // Low part of Data Address
1372 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1374 // Make the second call.
1375 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1376 Chain = getChain(SeqStart);
1377 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1379 // Subtract 1 from Address to get high part of data address.
1380 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1381 DAG.getConstant(1, MVT::i8));
1382 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1383 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1384 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1386 // Use new Lo to make another CALLW
1387 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1388 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1389 Chain = getChain(Call);
1390 OperFlag = getOutFlag(Call);
1391 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1393 Chain = getChain(SeqEnd);
1394 OperFlag = getOutFlag(SeqEnd);
1395 // Hi part of Data Address
1396 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1400 SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1401 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1402 SDValue Chain = TheCall->getChain();
1403 SDValue Callee = TheCall->getCallee();
1404 DebugLoc dl = TheCall->getDebugLoc();
1405 if (Callee.getValueType() == MVT::i16 &&
1406 Callee.getOpcode() == ISD::BUILD_PAIR) {
1407 // Control should come here only from TypeLegalizer for lowering
1409 // Legalize the non-legal arguments of call and return the
1410 // new call with legal arguments.
1411 return LegalizeCALL(Op, DAG);
1413 // Control should come here from Legalize DAG.
1414 // Here all the operands of CALL node should be legal.
1416 // If this is an indirect call then to pass the arguments
1417 // and read the return value back, we need the data address
1418 // of the function being called.
1419 // To get the data address two more calls need to be made.
1421 // The flag to track if this is a direct or indirect call.
1422 bool IsDirectCall = true;
1423 unsigned RetVals = TheCall->getNumRetVals();
1424 unsigned NumArgs = TheCall->getNumArgs();
1426 SDValue DataAddr_Lo, DataAddr_Hi;
1427 if (Callee.getOpcode() == PIC16ISD::PIC16Connect) {
1428 IsDirectCall = false; // This is indirect call
1429 // Read DataAddress only if we have to pass arguments or
1430 // read return value.
1431 if ((RetVals > 0) || (NumArgs > 0))
1432 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1435 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1437 // Start the call sequence.
1438 // Carring the Constant 0 along the CALLSEQSTART
1439 // because there is nothing else to carry.
1440 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1441 Chain = getChain(SeqStart);
1442 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1445 // For any direct call - callee will be GlobalAddressNode or
1447 SDValue ArgLabel, RetLabel;
1449 // Considering the GlobalAddressNode case here.
1450 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1451 GlobalValue *GV = G->getGlobal();
1452 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1453 Name = G->getGlobal()->getName();
1454 } else {// Considering the ExternalSymbol case here
1455 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1456 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1457 Name = ES->getSymbol();
1460 // Label for argument passing
1461 const char *argFrame = createESName(PAN::getArgsLabel(Name));
1462 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1464 // Label for reading return value
1465 const char *retName = createESName(PAN::getRetvalLabel(Name));
1466 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1469 SDValue CodeAddr_Lo = Callee.getOperand(0);
1470 SDValue CodeAddr_Hi = Callee.getOperand(1);
1472 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1473 DAG.getConstant(2, MVT::i8));*/
1475 // move Hi part in PCLATH
1476 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1477 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1481 // Pass the argument to function before making the call.
1484 CallArgs = LowerDirectCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
1485 Chain = getChain(CallArgs);
1486 OperFlag = getOutFlag(CallArgs);
1488 CallArgs = LowerIndirectCallArguments(Op, Chain, OperFlag, DataAddr_Lo,
1490 Chain = getChain(CallArgs);
1491 OperFlag = getOutFlag(CallArgs);
1494 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1495 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1497 Chain = getChain(PICCall);
1498 OperFlag = getOutFlag(PICCall);
1501 // Carrying the Constant 0 along the CALLSEQSTART
1502 // because there is nothing else to carry.
1503 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1505 Chain = getChain(SeqEnd);
1506 OperFlag = getOutFlag(SeqEnd);
1508 // Lower the return value reading after the call.
1510 return LowerDirectCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
1512 return LowerIndirectCallReturn(Op, Chain, OperFlag, DataAddr_Lo,
1516 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1517 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1518 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1519 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1524 // NeedToConvertToMemOp - Returns true if one of the operands of the
1525 // operation 'Op' needs to be put into memory. Also returns the
1526 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1527 // no instruction that can operation on two registers. Most insns take
1528 // one register and one memory operand (addwf) / Constant (addlw).
1529 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1530 // If one of the operand is a constant, return false.
1531 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1532 Op.getOperand(1).getOpcode() == ISD::Constant)
1535 // Return false if one of the operands is already a direct
1536 // load and that operand has only one use.
1537 if (isDirectLoad(Op.getOperand(0))) {
1538 if (Op.getOperand(0).hasOneUse())
1543 if (isDirectLoad(Op.getOperand(1))) {
1544 if (Op.getOperand(1).hasOneUse())
1552 // LowerBinOp - Lower a commutative binary operation that does not
1553 // affect status flag carry.
1554 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1555 DebugLoc dl = Op.getDebugLoc();
1557 // We should have handled larger operands in type legalizer itself.
1558 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1561 if (NeedToConvertToMemOp(Op, MemOp)) {
1562 // Put one value on stack.
1563 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1565 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1573 // LowerADD - Lower all types of ADD operations including the ones
1574 // that affects carry.
1575 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1576 // We should have handled larger operands in type legalizer itself.
1577 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1578 DebugLoc dl = Op.getDebugLoc();
1580 if (NeedToConvertToMemOp(Op, MemOp)) {
1581 // Put one value on stack.
1582 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1584 // ADDC and ADDE produce two results.
1585 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1587 // ADDE has three operands, the last one is the carry bit.
1588 if (Op.getOpcode() == ISD::ADDE)
1589 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1590 NewVal, Op.getOperand(2));
1591 // ADDC has two operands.
1592 else if (Op.getOpcode() == ISD::ADDC)
1593 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1595 // ADD it is. It produces only one result.
1597 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1604 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1605 DebugLoc dl = Op.getDebugLoc();
1606 // We should have handled larger operands in type legalizer itself.
1607 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1609 // Nothing to do if the first operand is already a direct load and it has
1611 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1614 // Put first operand on stack.
1615 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1617 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1618 switch (Op.getOpcode()) {
1620 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1624 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1627 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1));
1630 assert (0 && "Opcode unknown.");
1634 void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
1635 unsigned NumArgs = F->arg_size();
1637 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1640 ReservedFrameCount = NumArgs;
1642 ReservedFrameCount = NumArgs + 1;
1645 // LowerFORMAL_ARGUMENTS - Argument values are loaded from the
1646 // <fname>.args + offset. All arguments are already broken to leaglized
1647 // types, so the offset just runs from 0 to NumArgVals - 1.
1649 SDValue PIC16TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1650 SelectionDAG &DAG) {
1651 SmallVector<SDValue, 8> ArgValues;
1652 unsigned NumArgVals = Op.getNode()->getNumValues() - 1;
1653 DebugLoc dl = Op.getDebugLoc();
1654 SDValue Chain = Op.getOperand(0); // Formal arguments' chain
1657 // Get the callee's name to create the <fname>.args label to pass args.
1658 MachineFunction &MF = DAG.getMachineFunction();
1659 const Function *F = MF.getFunction();
1660 std::string FuncName = F->getName();
1662 // Reset the map of FI and TmpOffset
1663 ResetTmpOffsetMap();
1664 // Initialize the ReserveFrameCount
1665 InitReservedFrameCount(F);
1667 // Create the <fname>.args external symbol.
1668 const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
1669 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1671 // Load arg values from the label + offset.
1672 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1673 SDValue BS = DAG.getConstant(1, MVT::i8);
1674 for (unsigned i = 0; i < NumArgVals ; ++i) {
1675 SDValue Offset = DAG.getConstant(i, MVT::i8);
1676 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1678 Chain = getChain(PICLoad);
1679 ArgValues.push_back(PICLoad);
1682 // Return a MERGE_VALUE node.
1683 ArgValues.push_back(Op.getOperand(0));
1684 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1685 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1688 // Perform DAGCombine of PIC16Load.
1689 // FIXME - Need a more elaborate comment here.
1690 SDValue PIC16TargetLowering::
1691 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1692 SelectionDAG &DAG = DCI.DAG;
1693 SDValue Chain = N->getOperand(0);
1694 if (N->hasNUsesOfValue(0, 0)) {
1695 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1700 // For all the functions with arguments some STORE nodes are generated
1701 // that store the argument on the frameindex. However in PIC16 the arguments
1702 // are passed on stack only. Therefore these STORE nodes are redundant.
1703 // To remove these STORE nodes will be removed in PerformStoreCombine
1705 // Currently this function is doint nothing and will be updated for removing
1706 // unwanted store operations
1707 SDValue PIC16TargetLowering::
1708 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1709 return SDValue(N, 0);
1711 // Storing an undef value is of no use, so remove it
1712 if (isStoringUndef(N, Chain, DAG)) {
1713 return Chain; // remove the store and return the chain
1715 //else everything is ok.
1716 return SDValue(N, 0);
1720 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1721 DAGCombinerInfo &DCI) const {
1722 switch (N->getOpcode()) {
1724 return PerformStoreCombine(N, DCI);
1725 case PIC16ISD::PIC16Load:
1726 return PerformPIC16LoadCombine(N, DCI);
1731 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1733 default: llvm_unreachable("Unknown condition code!");
1734 case ISD::SETNE: return PIC16CC::NE;
1735 case ISD::SETEQ: return PIC16CC::EQ;
1736 case ISD::SETGT: return PIC16CC::GT;
1737 case ISD::SETGE: return PIC16CC::GE;
1738 case ISD::SETLT: return PIC16CC::LT;
1739 case ISD::SETLE: return PIC16CC::LE;
1740 case ISD::SETULT: return PIC16CC::ULT;
1741 case ISD::SETULE: return PIC16CC::ULE;
1742 case ISD::SETUGE: return PIC16CC::UGE;
1743 case ISD::SETUGT: return PIC16CC::UGT;
1747 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1748 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1749 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1750 ISD::CondCode CC, unsigned &SPCC) {
1751 if (isa<ConstantSDNode>(RHS) &&
1752 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1754 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1755 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1756 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1757 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1758 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1759 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1760 SDValue CMPCC = LHS.getOperand(3);
1761 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1762 LHS = CMPCC.getOperand(0);
1763 RHS = CMPCC.getOperand(1);
1767 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1768 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1769 unsigned CC, SDValue &PIC16CC,
1770 SelectionDAG &DAG, DebugLoc dl) {
1771 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1773 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1774 // i.e. a < 12 can be rewritten as 12 > a.
1775 if (RHS.getOpcode() == ISD::Constant) {
1784 CondCode = PIC16CC::GT;
1787 CondCode = PIC16CC::LT;
1790 CondCode = PIC16CC::UGT;
1793 CondCode = PIC16CC::ULT;
1796 CondCode = PIC16CC::LE;
1799 CondCode = PIC16CC::GE;
1802 CondCode = PIC16CC::UGE;
1805 CondCode = PIC16CC::ULE;
1810 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1812 // These are signed comparisons.
1813 SDValue Mask = DAG.getConstant(128, MVT::i8);
1814 if (isSignedComparison(CondCode)) {
1815 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1816 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1819 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1820 // We can use a subtract operation to set the condition codes. But
1821 // we need to put one operand in memory if required.
1822 // Nothing to do if the first operand is already a valid type (direct load
1823 // for subwf and literal for sublw) and it is used by this operation only.
1824 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1826 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1828 // else convert the first operand to mem.
1829 LHS = ConvertToMemOperand (LHS, DAG, dl);
1830 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1834 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1835 SDValue LHS = Op.getOperand(0);
1836 SDValue RHS = Op.getOperand(1);
1837 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1838 SDValue TrueVal = Op.getOperand(2);
1839 SDValue FalseVal = Op.getOperand(3);
1840 unsigned ORIGCC = ~0;
1841 DebugLoc dl = Op.getDebugLoc();
1843 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1844 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1846 // A setcc: lhs, rhs, cc is expanded by llvm to
1847 // select_cc: result of setcc, 0, 1, 0, setne
1848 // We can think of it as:
1849 // select_cc: lhs, rhs, 1, 0, cc
1850 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1851 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1854 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1856 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1857 FalseVal, PIC16CC, Cmp.getValue(1));
1861 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1862 MachineBasicBlock *BB) const {
1863 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1864 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1865 DebugLoc dl = MI->getDebugLoc();
1867 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1868 // control-flow pattern. The incoming instruction knows the destination vreg
1869 // to set, the condition code register to branch on, the true/false values to
1870 // select between, and a branch opcode to use.
1871 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1872 MachineFunction::iterator It = BB;
1879 // fallthrough --> copy0MBB
1880 MachineBasicBlock *thisMBB = BB;
1881 MachineFunction *F = BB->getParent();
1882 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1883 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1884 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1885 F->insert(It, copy0MBB);
1886 F->insert(It, sinkMBB);
1888 // Update machine-CFG edges by transferring all successors of the current
1889 // block to the new block which will contain the Phi node for the select.
1890 sinkMBB->transferSuccessors(BB);
1891 // Next, add the true and fallthrough blocks as its successors.
1892 BB->addSuccessor(copy0MBB);
1893 BB->addSuccessor(sinkMBB);
1896 // %FalseValue = ...
1897 // # fallthrough to sinkMBB
1900 // Update machine-CFG edges
1901 BB->addSuccessor(sinkMBB);
1904 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1907 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1908 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1909 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1911 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1916 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1917 SDValue Chain = Op.getOperand(0);
1918 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1919 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1920 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1921 SDValue Dest = Op.getOperand(4); // BB to jump to
1922 unsigned ORIGCC = ~0;
1923 DebugLoc dl = Op.getDebugLoc();
1925 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1926 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1927 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1928 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1930 // Get the Compare insn and condition code.
1932 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1934 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,