2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
16 #include "PIC16ISelLowering.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 static const char *getIntrinsicName(unsigned opcode) {
33 default: assert (0 && "do not know intrinsic name");
34 // Arithmetic Right shift for integer types.
35 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
36 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
37 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
39 // Left shift for integer types.
40 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
41 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
42 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
44 // Logical Right Shift for integer types.
45 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
46 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
47 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
49 // Multiply for integer types.
50 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
51 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
52 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
54 // Signed division for integers.
55 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
56 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
58 // Unsigned division for integers.
59 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
60 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
62 // Signed Modulas for integers.
63 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
64 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
66 // Unsigned Modulas for integers.
67 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
68 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
70 //////////////////////
71 // LIBCALLS FOR FLOATS
72 //////////////////////
74 // Float to signed integrals
75 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
76 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
77 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
79 // Signed integrals to float. char and int are first sign extended to i32
80 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
81 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
83 // Float to Unsigned conversions.
84 // Signed conversion can be used for unsigned conversion as well.
85 // In signed and unsigned versions only the interpretation of the
86 // MSB is different. Bit representation remains the same.
87 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
88 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
89 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
91 // Unsigned to Float conversions. char and int are first zero extended
92 // before being converted to float.
93 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
95 // Floating point add, sub, mul, div.
96 case RTLIB::ADD_F32: Basename = "add.f32"; break;
97 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
98 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
99 case RTLIB::DIV_F32: Basename = "div.f32"; break;
102 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
103 std::string tagname = PAN::getTagName(PAN::LIBCALL);
104 std::string Fullname = prefix + tagname + Basename;
106 // The name has to live through program life.
107 char *tmp = new char[Fullname.size() + 1];
108 strcpy (tmp, Fullname.c_str());
113 // PIC16TargetLowering Constructor.
114 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
115 : TargetLowering(TM), TmpSize(0) {
117 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
119 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
121 setShiftAmountType(MVT::i8);
122 setShiftAmountFlavor(Extend);
124 // SRA library call names
125 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
126 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
127 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
129 // SHL library call names
130 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
131 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
132 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
134 // SRL library call names
135 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
136 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
137 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
139 // MUL Library call names
140 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
141 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
142 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
144 // Signed division lib call names
145 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
146 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
148 // Unsigned division lib call names
149 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
150 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
152 // Signed remainder lib call names
153 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
154 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
156 // Unsigned remainder lib call names
157 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
158 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
160 // Floating point to signed int conversions.
161 setLibcallName(RTLIB::FPTOSINT_F32_I8,
162 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
163 setLibcallName(RTLIB::FPTOSINT_F32_I16,
164 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
165 setLibcallName(RTLIB::FPTOSINT_F32_I32,
166 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
168 // Signed int to floats.
169 setLibcallName(RTLIB::SINTTOFP_I32_F32,
170 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
172 // Floating points to unsigned ints.
173 setLibcallName(RTLIB::FPTOUINT_F32_I8,
174 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
175 setLibcallName(RTLIB::FPTOUINT_F32_I16,
176 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
177 setLibcallName(RTLIB::FPTOUINT_F32_I32,
178 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
180 // Unsigned int to floats.
181 setLibcallName(RTLIB::UINTTOFP_I32_F32,
182 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
184 // Floating point add, sub, mul ,div.
185 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
186 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
187 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
188 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
190 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
191 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
193 setOperationAction(ISD::LOAD, MVT::i8, Legal);
194 setOperationAction(ISD::LOAD, MVT::i16, Custom);
195 setOperationAction(ISD::LOAD, MVT::i32, Custom);
197 setOperationAction(ISD::STORE, MVT::i8, Legal);
198 setOperationAction(ISD::STORE, MVT::i16, Custom);
199 setOperationAction(ISD::STORE, MVT::i32, Custom);
201 setOperationAction(ISD::ADDE, MVT::i8, Custom);
202 setOperationAction(ISD::ADDC, MVT::i8, Custom);
203 setOperationAction(ISD::SUBE, MVT::i8, Custom);
204 setOperationAction(ISD::SUBC, MVT::i8, Custom);
205 setOperationAction(ISD::SUB, MVT::i8, Custom);
206 setOperationAction(ISD::ADD, MVT::i8, Custom);
207 setOperationAction(ISD::ADD, MVT::i16, Custom);
209 setOperationAction(ISD::OR, MVT::i8, Custom);
210 setOperationAction(ISD::AND, MVT::i8, Custom);
211 setOperationAction(ISD::XOR, MVT::i8, Custom);
213 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
214 setOperationAction(ISD::CALL, MVT::i16, Custom);
215 setOperationAction(ISD::RET, MVT::Other, Custom);
217 setOperationAction(ISD::MUL, MVT::i8, Custom);
218 setOperationAction(ISD::MUL, MVT::i16, Expand);
219 setOperationAction(ISD::MUL, MVT::i32, Expand);
221 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
222 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
223 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
224 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
225 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
226 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
227 setOperationAction(ISD::MULHU, MVT::i8, Expand);
228 setOperationAction(ISD::MULHU, MVT::i16, Expand);
229 setOperationAction(ISD::MULHU, MVT::i32, Expand);
230 setOperationAction(ISD::MULHS, MVT::i8, Expand);
231 setOperationAction(ISD::MULHS, MVT::i16, Expand);
232 setOperationAction(ISD::MULHS, MVT::i32, Expand);
234 setOperationAction(ISD::SRA, MVT::i8, Custom);
235 setOperationAction(ISD::SRA, MVT::i16, Expand);
236 setOperationAction(ISD::SRA, MVT::i32, Expand);
237 setOperationAction(ISD::SHL, MVT::i8, Custom);
238 setOperationAction(ISD::SHL, MVT::i16, Expand);
239 setOperationAction(ISD::SHL, MVT::i32, Expand);
240 setOperationAction(ISD::SRL, MVT::i8, Custom);
241 setOperationAction(ISD::SRL, MVT::i16, Expand);
242 setOperationAction(ISD::SRL, MVT::i32, Expand);
244 // PIC16 does not support shift parts
245 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
246 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
247 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
248 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
249 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
250 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
251 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
252 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
253 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
256 // PIC16 does not have a SETCC, expand it to SELECT_CC.
257 setOperationAction(ISD::SETCC, MVT::i8, Expand);
258 setOperationAction(ISD::SELECT, MVT::i8, Expand);
259 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
260 setOperationAction(ISD::BRIND, MVT::Other, Expand);
262 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
263 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
265 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
266 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
268 // Now deduce the information based on the above mentioned
270 computeRegisterProperties();
273 // getOutFlag - Extract the flag result if the Op has it.
274 static SDValue getOutFlag(SDValue &Op) {
275 // Flag is the last value of the node.
276 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
278 assert (Flag.getValueType() == MVT::Flag
279 && "Node does not have an out Flag");
283 // Get the TmpOffset for FrameIndex
284 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
285 std::map<unsigned, unsigned>::iterator
286 MapIt = FiTmpOffsetMap.find(FI);
287 if (MapIt != FiTmpOffsetMap.end())
288 return MapIt->second;
290 // This FI (FrameIndex) is not yet mapped, so map it
291 FiTmpOffsetMap[FI] = TmpSize;
293 return FiTmpOffsetMap[FI];
296 // To extract chain value from the SDValue Nodes
297 // This function will help to maintain the chain extracting
298 // code at one place. In case of any change in future it will
299 // help maintain the code.
300 static SDValue getChain(SDValue &Op) {
301 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
303 // If the last value returned in Flag then the chain is
304 // second last value returned.
305 if (Chain.getValueType() == MVT::Flag)
306 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
308 // All nodes may not produce a chain. Therefore following assert
309 // verifies that the node is returning a chain only.
310 assert (Chain.getValueType() == MVT::Other
311 && "Node does not have a chain");
316 /// PopulateResults - Helper function to LowerOperation.
317 /// If a node wants to return multiple results after lowering,
318 /// it stuffs them into an array of SDValue called Results.
320 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
321 if (N.getOpcode() == ISD::MERGE_VALUES) {
322 int NumResults = N.getNumOperands();
323 for( int i = 0; i < NumResults; i++)
324 Results.push_back(N.getOperand(i));
327 Results.push_back(N);
330 MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
334 /// The type legalizer framework of generating legalizer can generate libcalls
335 /// only when the operand/result types are illegal.
336 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
337 /// For example an arithmetic right shift. These functions are used to lower
338 /// such operations that generate libcall for legal types.
341 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
343 PIC16LibcallNames[Call] = Name;
347 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
348 return PIC16LibcallNames[Call];
352 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
353 MVT RetVT, const SDValue *Ops,
354 unsigned NumOps, bool isSigned,
355 SelectionDAG &DAG, DebugLoc dl) {
357 TargetLowering::ArgListTy Args;
358 Args.reserve(NumOps);
360 TargetLowering::ArgListEntry Entry;
361 for (unsigned i = 0; i != NumOps; ++i) {
363 Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
364 Entry.isSExt = isSigned;
365 Entry.isZExt = !isSigned;
366 Args.push_back(Entry);
368 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
370 const Type *RetTy = RetVT.getTypeForMVT();
371 std::pair<SDValue,SDValue> CallInfo =
372 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
373 false, CallingConv::C, false, Callee, Args, DAG, dl);
375 return CallInfo.first;
378 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
380 default: return NULL;
381 case PIC16ISD::Lo: return "PIC16ISD::Lo";
382 case PIC16ISD::Hi: return "PIC16ISD::Hi";
383 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
384 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
385 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
386 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
387 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
388 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
389 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
390 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
391 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
392 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
393 case PIC16ISD::BCF: return "PIC16ISD::BCF";
394 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
395 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
396 case PIC16ISD::RLF: return "PIC16ISD::RLF";
397 case PIC16ISD::RRF: return "PIC16ISD::RRF";
398 case PIC16ISD::CALL: return "PIC16ISD::CALL";
399 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
400 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
401 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
402 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
403 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
407 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
408 SmallVectorImpl<SDValue>&Results,
411 switch (N->getOpcode()) {
412 case ISD::GlobalAddress:
413 Results.push_back(ExpandGlobalAddress(N, DAG));
415 case ISD::ExternalSymbol:
416 Results.push_back(ExpandExternalSymbol(N, DAG));
419 Results.push_back(ExpandStore(N, DAG));
422 PopulateResults(ExpandLoad(N, DAG), Results);
425 // Results.push_back(ExpandAdd(N, DAG));
427 case ISD::FrameIndex:
428 Results.push_back(ExpandFrameIndex(N, DAG));
431 assert (0 && "not implemented");
436 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
438 // Currently handling FrameIndex of size MVT::i16 only
439 // One example of this scenario is when return value is written on
442 if (N->getValueType(0) != MVT::i16)
445 // Expand the FrameIndex into ExternalSymbol and a Constant node
446 // The constant will represent the frame index number
447 // Get the current function frame
448 MachineFunction &MF = DAG.getMachineFunction();
449 const Function *Func = MF.getFunction();
450 const std::string Name = Func->getName();
452 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
453 // FIXME there isn't really debug info here
454 DebugLoc dl = FR->getDebugLoc();
456 // Expand FrameIndex like GlobalAddress and ExternalSymbol
457 // Also use Offset field for lo and hi parts. The default
462 SDValue FI = SDValue(N,0);
463 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
464 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
465 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
466 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
467 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
471 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
472 StoreSDNode *St = cast<StoreSDNode>(N);
473 SDValue Chain = St->getChain();
474 SDValue Src = St->getValue();
475 SDValue Ptr = St->getBasePtr();
476 MVT ValueType = Src.getValueType();
477 unsigned StoreOffset = 0;
478 DebugLoc dl = N->getDebugLoc();
480 SDValue PtrLo, PtrHi;
481 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
483 if (ValueType == MVT::i8) {
484 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
486 DAG.getConstant (0 + StoreOffset, MVT::i8));
488 else if (ValueType == MVT::i16) {
489 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
490 SDValue SrcLo, SrcHi;
491 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
492 SDValue ChainLo = Chain, ChainHi = Chain;
493 if (Chain.getOpcode() == ISD::TokenFactor) {
494 ChainLo = Chain.getOperand(0);
495 ChainHi = Chain.getOperand(1);
497 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
500 DAG.getConstant (0 + StoreOffset, MVT::i8));
502 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
504 DAG.getConstant (1 + StoreOffset, MVT::i8));
506 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
509 else if (ValueType == MVT::i32) {
510 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
511 SDValue SrcLo, SrcHi;
512 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
514 // Get the expanded parts of each of SrcLo and SrcHi.
515 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
516 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
517 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
519 SDValue ChainLo = Chain, ChainHi = Chain;
520 if (Chain.getOpcode() == ISD::TokenFactor) {
521 ChainLo = Chain.getOperand(0);
522 ChainHi = Chain.getOperand(1);
524 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
526 if (ChainLo.getOpcode() == ISD::TokenFactor) {
527 ChainLo1 = ChainLo.getOperand(0);
528 ChainLo2 = ChainLo.getOperand(1);
530 if (ChainHi.getOpcode() == ISD::TokenFactor) {
531 ChainHi1 = ChainHi.getOperand(0);
532 ChainHi2 = ChainHi.getOperand(1);
534 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
536 SrcLo1, PtrLo, PtrHi,
537 DAG.getConstant (0 + StoreOffset, MVT::i8));
539 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
540 SrcLo2, PtrLo, PtrHi,
541 DAG.getConstant (1 + StoreOffset, MVT::i8));
543 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
544 SrcHi1, PtrLo, PtrHi,
545 DAG.getConstant (2 + StoreOffset, MVT::i8));
547 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
548 SrcHi2, PtrLo, PtrHi,
549 DAG.getConstant (3 + StoreOffset, MVT::i8));
551 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
552 getChain(Store1), getChain(Store2));
553 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
554 getChain(Store3), getChain(Store4));
555 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
559 assert (0 && "value type not supported");
564 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
566 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
567 // FIXME there isn't really debug info here
568 DebugLoc dl = ES->getDebugLoc();
570 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
571 SDValue Offset = DAG.getConstant(0, MVT::i8);
572 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
573 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
575 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
578 // ExpandGlobalAddress -
579 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
580 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
581 // FIXME there isn't really debug info here
582 DebugLoc dl = G->getDebugLoc();
584 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
587 SDValue Offset = DAG.getConstant(0, MVT::i8);
588 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
589 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
591 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
594 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
595 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
597 if (Op.getOpcode() == ISD::BUILD_PAIR) {
598 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
604 // Return true if DirectAddress is in ROM_SPACE
605 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
607 // RomAddress is a GlobalAddress in ROM_SPACE_
608 // If the Op is not a GlobalAddress return NULL without checking
610 if (!isDirectAddress(Op))
613 // Its a GlobalAddress.
614 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
615 SDValue TGA = Op.getOperand(0).getOperand(0);
616 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
618 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
621 // Any other address space return it false
626 // GetExpandedParts - This function is on the similiar lines as
627 // the GetExpandedInteger in type legalizer is. This returns expanded
628 // parts of Op in Lo and Hi.
630 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
631 SDValue &Lo, SDValue &Hi) {
632 SDNode *N = Op.getNode();
633 DebugLoc dl = N->getDebugLoc();
634 MVT NewVT = getTypeToTransformTo(N->getValueType(0));
636 // Extract the lo component.
637 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
638 DAG.getConstant(0, MVT::i8));
640 // extract the hi component
641 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
642 DAG.getConstant(1, MVT::i8));
645 // Legalize FrameIndex into ExternalSymbol and offset.
647 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
648 SDValue &ES, int &Offset) {
650 MachineFunction &MF = DAG.getMachineFunction();
651 const Function *Func = MF.getFunction();
652 MachineFrameInfo *MFI = MF.getFrameInfo();
653 const std::string Name = Func->getName();
655 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
657 // FrameIndices are not stack offsets. But they represent the request
658 // for space on stack. That space requested may be more than one byte.
659 // Therefore, to calculate the stack offset that a FrameIndex aligns
660 // with, we need to traverse all the FrameIndices available earlier in
661 // the list and add their requested size.
662 unsigned FIndex = FR->getIndex();
664 if (FIndex < ReservedFrameCount) {
665 tmpName = createESName(PAN::getFrameLabel(Name));
666 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
668 for (unsigned i=0; i<FIndex ; ++i) {
669 Offset += MFI->getObjectSize(i);
672 // FrameIndex has been made for some temporary storage
673 tmpName = createESName(PAN::getTempdataLabel(Name));
674 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
675 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
681 // This function legalizes the PIC16 Addresses. If the Pointer is
682 // -- Direct address variable residing
683 // --> then a Banksel for that variable will be created.
685 // --> then it will be treated as an indirect address.
686 // -- Indirect address
687 // --> then the address will be loaded into FSR
688 // -- ADD with constant operand
689 // --> then constant operand of ADD will be returned as Offset
690 // and non-constant operand of ADD will be treated as pointer.
691 // Returns the high and lo part of the address, and the offset(in case of ADD).
693 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
694 SDValue &Lo, SDValue &Hi,
695 unsigned &Offset, DebugLoc dl) {
697 // Offset, by default, should be 0
700 // If the pointer is ADD with constant,
701 // return the constant value as the offset
702 if (Ptr.getOpcode() == ISD::ADD) {
703 SDValue OperLeft = Ptr.getOperand(0);
704 SDValue OperRight = Ptr.getOperand(1);
705 if ((OperLeft.getOpcode() == ISD::Constant) &&
706 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
707 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
709 } else if ((OperRight.getOpcode() == ISD::Constant) &&
710 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
711 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
716 // If the pointer is Type i8 and an external symbol
717 // then treat it as direct address.
718 // One example for such case is storing and loading
719 // from function frame during a call
720 if (Ptr.getValueType() == MVT::i8) {
721 switch (Ptr.getOpcode()) {
722 case ISD::TargetExternalSymbol:
724 Hi = DAG.getConstant(1, MVT::i8);
729 // Expansion of FrameIndex has Lo/Hi parts
730 if (isDirectAddress(Ptr)) {
731 SDValue TFI = Ptr.getOperand(0).getOperand(0);
733 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
734 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
735 Hi = DAG.getConstant(1, MVT::i8);
736 Offset += FrameOffset;
738 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
739 // FrameIndex has already been expanded.
740 // Now just make use of its expansion
742 Hi = DAG.getConstant(1, MVT::i8);
743 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
744 assert (FOffset.getOpcode() == ISD::Constant &&
745 "Invalid operand of PIC16ISD::Lo");
746 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
751 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
752 // Direct addressing case for RAM variables. The Hi part is constant
753 // and the Lo part is the TGA itself.
754 Lo = Ptr.getOperand(0).getOperand(0);
756 // For direct addresses Hi is a constant. Value 1 for the constant
757 // signifies that banksel needs to generated for it. Value 0 for
758 // the constant signifies that banksel does not need to be generated
759 // for it. Mark it as 1 now and optimize later.
760 Hi = DAG.getConstant(1, MVT::i8);
764 // Indirect addresses. Get the hi and lo parts of ptr.
765 GetExpandedParts(Ptr, DAG, Lo, Hi);
767 // Put the hi and lo parts into FSR.
768 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
769 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
774 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
775 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
776 SDValue Chain = LD->getChain();
777 SDValue Ptr = LD->getBasePtr();
778 DebugLoc dl = LD->getDebugLoc();
780 SDValue Load, Offset;
783 SDValue PtrLo, PtrHi;
786 // Legalize direct/indirect addresses. This will give the lo and hi parts
787 // of the address and the offset.
788 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
790 // Load from the pointer (direct address or FSR)
791 VT = N->getValueType(0);
792 unsigned NumLoads = VT.getSizeInBits() / 8;
793 std::vector<SDValue> PICLoads;
795 MVT MemVT = LD->getMemoryVT();
796 if(ISD::isNON_EXTLoad(N)) {
797 for (iter=0; iter<NumLoads ; ++iter) {
798 // Add the pointer offset if any
799 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
800 Tys = DAG.getVTList(MVT::i8, MVT::Other);
801 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
803 PICLoads.push_back(Load);
806 // If it is extended load then use PIC16Load for Memory Bytes
807 // and for all extended bytes perform action based on type of
808 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
811 // For extended loads this is the memory value type
812 // i.e. without any extension
813 MVT MemVT = LD->getMemoryVT();
814 unsigned MemBytes = MemVT.getSizeInBits() / 8;
815 unsigned ExtdBytes = VT.getSizeInBits() / 8;
816 Offset = DAG.getConstant(LoadOffset, MVT::i8);
818 Tys = DAG.getVTList(MVT::i8, MVT::Other);
819 // For MemBytes generate PIC16Load with proper offset
820 for (iter=0; iter<MemBytes; ++iter) {
821 // Add the pointer offset if any
822 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
823 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
825 PICLoads.push_back(Load);
828 // For SignExtendedLoad
829 if (ISD::isSEXTLoad(N)) {
830 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
832 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
833 DAG.getConstant(7, MVT::i8));
834 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
835 PICLoads.push_back(SRA);
837 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
838 //} else if (ISD::isZEXTLoad(N)) {
839 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
840 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
841 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
842 PICLoads.push_back(ConstZero);
849 // Operand of Load is illegal -- Load itself is legal
852 else if (VT == MVT::i16) {
853 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
854 if (MemVT == MVT::i8)
855 Chain = getChain(PICLoads[0]);
857 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
858 getChain(PICLoads[0]), getChain(PICLoads[1]));
859 } else if (VT == MVT::i32) {
861 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
862 PICLoads[0], PICLoads[1]);
863 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
864 PICLoads[2], PICLoads[3]);
865 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
866 if (MemVT == MVT::i8)
867 Chain = getChain(PICLoads[0]);
868 else if (MemVT == MVT::i16)
869 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
870 getChain(PICLoads[0]), getChain(PICLoads[1]));
873 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
874 getChain(PICLoads[0]), getChain(PICLoads[1]));
875 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
876 getChain(PICLoads[2]), getChain(PICLoads[3]));
877 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
878 Chains[0], Chains[1]);
881 Tys = DAG.getVTList(VT, MVT::Other);
882 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
885 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
886 // We should have handled larger operands in type legalizer itself.
887 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
889 SDNode *N = Op.getNode();
890 SDValue Value = N->getOperand(0);
891 SDValue Amt = N->getOperand(1);
892 PIC16ISD::PIC16Libcall CallCode;
893 switch (N->getOpcode()) {
895 CallCode = PIC16ISD::SRA_I8;
898 CallCode = PIC16ISD::SLL_I8;
901 CallCode = PIC16ISD::SRL_I8;
904 assert ( 0 && "This shift is not implemented yet.");
907 SmallVector<SDValue, 2> Ops(2);
910 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
911 true, DAG, N->getDebugLoc());
916 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
917 SmallVectorImpl<SDValue>&Results,
919 SDValue Op = SDValue(N, 0);
922 switch (Op.getOpcode()) {
923 case ISD::FORMAL_ARGUMENTS:
924 Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
926 Res = ExpandLoad(Op.getNode(), DAG); break;
928 Res = LowerCALL(Op, DAG); break;
930 // All other operations are handled in LowerOperation.
931 Res = LowerOperation(Op, DAG);
933 Results.push_back(Res);
940 unsigned NumValues = N->getNumValues();
941 for (i = 0; i < NumValues ; i++) {
942 Results.push_back(SDValue(N, i));
946 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
947 switch (Op.getOpcode()) {
948 case ISD::FORMAL_ARGUMENTS:
949 return LowerFORMAL_ARGUMENTS(Op, DAG);
953 return LowerADD(Op, DAG);
957 return LowerSUB(Op, DAG);
959 return ExpandLoad(Op.getNode(), DAG);
961 return ExpandStore(Op.getNode(), DAG);
965 return LowerShift(Op, DAG);
969 return LowerBinOp(Op, DAG);
971 return LowerCALL(Op, DAG);
973 return LowerRET(Op, DAG);
975 return LowerBR_CC(Op, DAG);
977 return LowerSELECT_CC(Op, DAG);
982 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
985 assert (Op.getValueType() == MVT::i8
986 && "illegal value type to store on stack.");
988 MachineFunction &MF = DAG.getMachineFunction();
989 const Function *Func = MF.getFunction();
990 const std::string FuncName = Func->getName();
993 // Put the value on stack.
994 // Get a stack slot index and convert to es.
995 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
996 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
997 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
999 // Store the value to ES.
1000 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1003 DAG.getConstant (1, MVT::i8), // Banksel.
1004 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1007 // Load the value from ES.
1008 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1009 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1010 ES, DAG.getConstant (1, MVT::i8),
1011 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1014 return Load.getValue(0);
1017 SDValue PIC16TargetLowering::
1018 LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag,
1019 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1020 SelectionDAG &DAG) {
1021 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1022 unsigned NumOps = TheCall->getNumArgs();
1023 DebugLoc dl = TheCall->getDebugLoc();
1025 // If call has no arguments then do nothing and return.
1029 std::vector<SDValue> Ops;
1030 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1031 SDValue Arg, StoreRet;
1033 // For PIC16 ABI the arguments come after the return value.
1034 unsigned RetVals = TheCall->getNumRetVals();
1035 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1036 // Get the arguments
1037 Arg = TheCall->getArg(i);
1040 Ops.push_back(Chain);
1042 Ops.push_back(DataAddr_Lo);
1043 Ops.push_back(DataAddr_Hi);
1044 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1045 Ops.push_back(InFlag);
1047 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1049 Chain = getChain(StoreRet);
1050 InFlag = getOutFlag(StoreRet);
1056 SDValue PIC16TargetLowering::
1057 LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue ArgLabel,
1058 SDValue InFlag, SelectionDAG &DAG) {
1059 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1060 unsigned NumOps = TheCall->getNumArgs();
1061 DebugLoc dl = TheCall->getDebugLoc();
1063 SDValue Arg, StoreAt;
1066 unsigned ArgCount=0;
1068 // If call has no arguments then do nothing and return.
1072 // FIXME: This portion of code currently assumes only
1073 // primitive types being passed as arguments.
1075 // Legalize the address before use
1076 SDValue PtrLo, PtrHi;
1077 unsigned AddressOffset;
1078 int StoreOffset = 0;
1079 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1082 std::vector<SDValue> Ops;
1083 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1084 for (unsigned i=ArgCount, Offset = 0; i<NumOps; i++) {
1086 Arg = TheCall->getArg(i);
1087 StoreOffset = (Offset + AddressOffset);
1089 // Store the argument on frame
1092 Ops.push_back(Chain);
1094 Ops.push_back(PtrLo);
1095 Ops.push_back(PtrHi);
1096 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1097 Ops.push_back(InFlag);
1099 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1101 Chain = getChain(StoreRet);
1102 InFlag = getOutFlag(StoreRet);
1104 // Update the frame offset to be used for next argument
1105 ArgVT = Arg.getValueType();
1106 Size = ArgVT.getSizeInBits();
1107 Size = Size/8; // Calculate size in bytes
1108 Offset += Size; // Increase the frame offset
1113 SDValue PIC16TargetLowering::
1114 LowerIndirectCallReturn (SDValue Op, SDValue Chain, SDValue InFlag,
1115 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1116 SelectionDAG &DAG) {
1117 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1118 DebugLoc dl = TheCall->getDebugLoc();
1119 unsigned RetVals = TheCall->getNumRetVals();
1121 // If call does not have anything to return
1122 // then do nothing and go back.
1126 // Call has something to return
1127 std::vector<SDValue> ResultVals;
1130 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1131 for(unsigned i=0;i<RetVals;i++) {
1132 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1133 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1135 InFlag = getOutFlag(LoadRet);
1136 Chain = getChain(LoadRet);
1137 ResultVals.push_back(LoadRet);
1139 ResultVals.push_back(Chain);
1140 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1144 SDValue PIC16TargetLowering::
1145 LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue RetLabel,
1146 SDValue InFlag, SelectionDAG &DAG) {
1147 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1148 DebugLoc dl = TheCall->getDebugLoc();
1149 // Currently handling primitive types only. They will come in
1151 unsigned RetVals = TheCall->getNumRetVals();
1153 std::vector<SDValue> ResultVals;
1155 // Return immediately if the return type is void
1159 // Call has something to return
1161 // Legalize the address before use
1164 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1166 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1169 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1171 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1172 DAG.getConstant(LdOffset + Offset, MVT::i8),
1175 InFlag = getOutFlag(LoadRet);
1177 Chain = getChain(LoadRet);
1179 ResultVals.push_back(LoadRet);
1182 // To return use MERGE_VALUES
1183 ResultVals.push_back(Chain);
1184 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1188 SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1189 SDValue Chain = Op.getOperand(0);
1190 DebugLoc dl = Op.getDebugLoc();
1192 if (Op.getNumOperands() == 1) // return void
1195 // return should have odd number of operands
1196 if ((Op.getNumOperands() % 2) == 0 ) {
1197 assert(0 && "Do not know how to return this many arguments!");
1201 // Number of values to return
1202 unsigned NumRet = (Op.getNumOperands() / 2);
1204 // Function returns value always on stack with the offset starting
1206 MachineFunction &MF = DAG.getMachineFunction();
1207 const Function *F = MF.getFunction();
1208 std::string FuncName = F->getName();
1210 const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
1211 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1212 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1213 SDValue BS = DAG.getConstant(1, MVT::i8);
1215 for(unsigned i=0;i<NumRet; ++i) {
1216 RetVal = Op.getNode()->getOperand(2*i + 1);
1217 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1219 DAG.getConstant (i, MVT::i8));
1222 return DAG.getNode(ISD::RET, dl, MVT::Other, Chain);
1225 // CALL node may have some operands non-legal to PIC16. Generate new CALL
1226 // node with all the operands legal.
1227 // Currently only Callee operand of the CALL node is non-legal. This function
1228 // legalizes the Callee operand and uses all other operands as are to generate
1231 SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) {
1232 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1233 SDValue Chain = TheCall->getChain();
1234 SDValue Callee = TheCall->getCallee();
1235 DebugLoc dl = TheCall->getDebugLoc();
1238 assert(Callee.getValueType() == MVT::i16 &&
1239 "Don't know how to legalize this call node!!!");
1240 assert(Callee.getOpcode() == ISD::BUILD_PAIR &&
1241 "Don't know how to legalize this call node!!!");
1243 if (isDirectAddress(Callee)) {
1244 // Come here for direct calls
1245 Callee = Callee.getOperand(0).getOperand(0);
1247 // Come here for indirect calls
1249 // Indirect addresses. Get the hi and lo parts of ptr.
1250 GetExpandedParts(Callee, DAG, Lo, Hi);
1251 // Connect Lo and Hi parts of the callee with the PIC16Connect
1252 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1254 std::vector<SDValue> Ops;
1255 Ops.push_back(Chain);
1256 Ops.push_back(Callee);
1258 // Add the call arguments and their flags
1259 unsigned NumArgs = TheCall->getNumArgs();
1260 for(i=0;i<NumArgs;i++) {
1261 Ops.push_back(TheCall->getArg(i));
1262 Ops.push_back(TheCall->getArgFlagsVal(i));
1264 std::vector<MVT> NodeTys;
1265 unsigned NumRets = TheCall->getNumRetVals();
1266 for(i=0;i<NumRets;i++)
1267 NodeTys.push_back(TheCall->getRetValType(i));
1269 // Return a Chain as well
1270 NodeTys.push_back(MVT::Other);
1272 SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
1273 // Generate new call with all the operands legal
1274 return DAG.getCall(TheCall->getCallingConv(), dl,
1275 TheCall->isVarArg(), TheCall->isTailCall(),
1276 TheCall->isInreg(), VTs, &Ops[0], Ops.size());
1279 void PIC16TargetLowering::
1280 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1281 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1282 SelectionDAG &DAG) {
1283 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1284 && "Don't know what to do of such callee!!");
1285 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1286 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1287 Chain = getChain(SeqStart);
1288 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1290 // Get the Lo and Hi part of code address
1291 SDValue Lo = Callee.getOperand(0);
1292 SDValue Hi = Callee.getOperand(1);
1294 SDValue Data_Lo, Data_Hi;
1295 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1296 // Subtract 2 from Address to get the Lower part of DataAddress.
1297 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1298 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1299 DAG.getConstant(2, MVT::i8));
1300 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1301 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1302 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1303 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1304 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1306 Chain = getChain(Call);
1307 OperFlag = getOutFlag(Call);
1308 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1310 Chain = getChain(SeqEnd);
1311 OperFlag = getOutFlag(SeqEnd);
1313 // Low part of Data Address
1314 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1316 // Make the second call.
1317 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1318 Chain = getChain(SeqStart);
1319 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1321 // Subtract 1 from Address to get high part of data address.
1322 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1323 DAG.getConstant(1, MVT::i8));
1324 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1325 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1326 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1328 // Use new Lo to make another CALLW
1329 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1330 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1331 Chain = getChain(Call);
1332 OperFlag = getOutFlag(Call);
1333 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1335 Chain = getChain(SeqEnd);
1336 OperFlag = getOutFlag(SeqEnd);
1337 // Hi part of Data Address
1338 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1342 SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1343 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1344 SDValue Chain = TheCall->getChain();
1345 SDValue Callee = TheCall->getCallee();
1346 DebugLoc dl = TheCall->getDebugLoc();
1347 if (Callee.getValueType() == MVT::i16 &&
1348 Callee.getOpcode() == ISD::BUILD_PAIR) {
1349 // Control should come here only from TypeLegalizer for lowering
1351 // Legalize the non-legal arguments of call and return the
1352 // new call with legal arguments.
1353 return LegalizeCALL(Op, DAG);
1355 // Control should come here from Legalize DAG.
1356 // Here all the operands of CALL node should be legal.
1358 // If this is an indirect call then to pass the arguments
1359 // and read the return value back, we need the data address
1360 // of the function being called.
1361 // To get the data address two more calls need to be made.
1363 // The flag to track if this is a direct or indirect call.
1364 bool IsDirectCall = true;
1365 unsigned RetVals = TheCall->getNumRetVals();
1366 unsigned NumArgs = TheCall->getNumArgs();
1368 SDValue DataAddr_Lo, DataAddr_Hi;
1369 if (Callee.getOpcode() == PIC16ISD::PIC16Connect) {
1370 IsDirectCall = false; // This is indirect call
1371 // Read DataAddress only if we have to pass arguments or
1372 // read return value.
1373 if ((RetVals > 0) || (NumArgs > 0))
1374 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1377 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1379 // Start the call sequence.
1380 // Carring the Constant 0 along the CALLSEQSTART
1381 // because there is nothing else to carry.
1382 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1383 Chain = getChain(SeqStart);
1384 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1387 // For any direct call - callee will be GlobalAddressNode or
1389 SDValue ArgLabel, RetLabel;
1391 // Considering the GlobalAddressNode case here.
1392 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1393 GlobalValue *GV = G->getGlobal();
1394 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1395 Name = G->getGlobal()->getName();
1396 } else {// Considering the ExternalSymbol case here
1397 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1398 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1399 Name = ES->getSymbol();
1402 // Label for argument passing
1403 const char *argFrame = createESName(PAN::getArgsLabel(Name));
1404 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1406 // Label for reading return value
1407 const char *retName = createESName(PAN::getRetvalLabel(Name));
1408 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1411 SDValue CodeAddr_Lo = Callee.getOperand(0);
1412 SDValue CodeAddr_Hi = Callee.getOperand(1);
1414 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1415 DAG.getConstant(2, MVT::i8));*/
1417 // move Hi part in PCLATH
1418 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1419 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1423 // Pass the argument to function before making the call.
1426 CallArgs = LowerDirectCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
1427 Chain = getChain(CallArgs);
1428 OperFlag = getOutFlag(CallArgs);
1430 CallArgs = LowerIndirectCallArguments(Op, Chain, OperFlag, DataAddr_Lo,
1432 Chain = getChain(CallArgs);
1433 OperFlag = getOutFlag(CallArgs);
1436 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1437 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1439 Chain = getChain(PICCall);
1440 OperFlag = getOutFlag(PICCall);
1443 // Carrying the Constant 0 along the CALLSEQSTART
1444 // because there is nothing else to carry.
1445 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1447 Chain = getChain(SeqEnd);
1448 OperFlag = getOutFlag(SeqEnd);
1450 // Lower the return value reading after the call.
1452 return LowerDirectCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
1454 return LowerIndirectCallReturn(Op, Chain, OperFlag, DataAddr_Lo,
1458 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1459 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1460 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1461 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1466 // NeedToConvertToMemOp - Returns true if one of the operands of the
1467 // operation 'Op' needs to be put into memory. Also returns the
1468 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1469 // no instruction that can operation on two registers. Most insns take
1470 // one register and one memory operand (addwf) / Constant (addlw).
1471 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1472 // If one of the operand is a constant, return false.
1473 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1474 Op.getOperand(1).getOpcode() == ISD::Constant)
1477 // Return false if one of the operands is already a direct
1478 // load and that operand has only one use.
1479 if (isDirectLoad(Op.getOperand(0))) {
1480 if (Op.getOperand(0).hasOneUse())
1485 if (isDirectLoad(Op.getOperand(1))) {
1486 if (Op.getOperand(1).hasOneUse())
1494 // LowerBinOp - Lower a commutative binary operation that does not
1495 // affect status flag carry.
1496 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1497 DebugLoc dl = Op.getDebugLoc();
1499 // We should have handled larger operands in type legalizer itself.
1500 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1503 if (NeedToConvertToMemOp(Op, MemOp)) {
1504 // Put one value on stack.
1505 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1507 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1515 // LowerADD - Lower all types of ADD operations including the ones
1516 // that affects carry.
1517 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1518 // We should have handled larger operands in type legalizer itself.
1519 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1520 DebugLoc dl = Op.getDebugLoc();
1522 if (NeedToConvertToMemOp(Op, MemOp)) {
1523 // Put one value on stack.
1524 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1526 // ADDC and ADDE produce two results.
1527 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1529 // ADDE has three operands, the last one is the carry bit.
1530 if (Op.getOpcode() == ISD::ADDE)
1531 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1532 NewVal, Op.getOperand(2));
1533 // ADDC has two operands.
1534 else if (Op.getOpcode() == ISD::ADDC)
1535 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1537 // ADD it is. It produces only one result.
1539 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1546 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1547 DebugLoc dl = Op.getDebugLoc();
1548 // We should have handled larger operands in type legalizer itself.
1549 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1551 // Nothing to do if the first operand is already a direct load and it has
1553 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1556 // Put first operand on stack.
1557 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1559 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1560 if (Op.getOpcode() == ISD::SUBE)
1561 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1564 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1567 void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
1568 unsigned NumArgs = F->arg_size();
1570 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1573 ReservedFrameCount = NumArgs;
1575 ReservedFrameCount = NumArgs + 1;
1578 // LowerFORMAL_ARGUMENTS - Argument values are loaded from the
1579 // <fname>.args + offset. All arguments are already broken to leaglized
1580 // types, so the offset just runs from 0 to NumArgVals - 1.
1582 SDValue PIC16TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1583 SelectionDAG &DAG) {
1584 SmallVector<SDValue, 8> ArgValues;
1585 unsigned NumArgVals = Op.getNode()->getNumValues() - 1;
1586 DebugLoc dl = Op.getDebugLoc();
1587 SDValue Chain = Op.getOperand(0); // Formal arguments' chain
1590 // Get the callee's name to create the <fname>.args label to pass args.
1591 MachineFunction &MF = DAG.getMachineFunction();
1592 const Function *F = MF.getFunction();
1593 std::string FuncName = F->getName();
1595 // Reset the map of FI and TmpOffset
1596 ResetTmpOffsetMap();
1597 // Initialize the ReserveFrameCount
1598 InitReservedFrameCount(F);
1600 // Create the <fname>.args external symbol.
1601 const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
1602 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1604 // Load arg values from the label + offset.
1605 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1606 SDValue BS = DAG.getConstant(1, MVT::i8);
1607 for (unsigned i = 0; i < NumArgVals ; ++i) {
1608 SDValue Offset = DAG.getConstant(i, MVT::i8);
1609 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1611 Chain = getChain(PICLoad);
1612 ArgValues.push_back(PICLoad);
1615 // Return a MERGE_VALUE node.
1616 ArgValues.push_back(Op.getOperand(0));
1617 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1618 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1621 // Perform DAGCombine of PIC16Load.
1622 // FIXME - Need a more elaborate comment here.
1623 SDValue PIC16TargetLowering::
1624 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1625 SelectionDAG &DAG = DCI.DAG;
1626 SDValue Chain = N->getOperand(0);
1627 if (N->hasNUsesOfValue(0, 0)) {
1628 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1633 // For all the functions with arguments some STORE nodes are generated
1634 // that store the argument on the frameindex. However in PIC16 the arguments
1635 // are passed on stack only. Therefore these STORE nodes are redundant.
1636 // To remove these STORE nodes will be removed in PerformStoreCombine
1638 // Currently this function is doint nothing and will be updated for removing
1639 // unwanted store operations
1640 SDValue PIC16TargetLowering::
1641 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1642 return SDValue(N, 0);
1644 // Storing an undef value is of no use, so remove it
1645 if (isStoringUndef(N, Chain, DAG)) {
1646 return Chain; // remove the store and return the chain
1648 //else everything is ok.
1649 return SDValue(N, 0);
1653 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1654 DAGCombinerInfo &DCI) const {
1655 switch (N->getOpcode()) {
1657 return PerformStoreCombine(N, DCI);
1658 case PIC16ISD::PIC16Load:
1659 return PerformPIC16LoadCombine(N, DCI);
1664 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1666 default: assert(0 && "Unknown condition code!");
1667 case ISD::SETNE: return PIC16CC::NE;
1668 case ISD::SETEQ: return PIC16CC::EQ;
1669 case ISD::SETGT: return PIC16CC::GT;
1670 case ISD::SETGE: return PIC16CC::GE;
1671 case ISD::SETLT: return PIC16CC::LT;
1672 case ISD::SETLE: return PIC16CC::LE;
1673 case ISD::SETULT: return PIC16CC::ULT;
1674 case ISD::SETULE: return PIC16CC::ULE;
1675 case ISD::SETUGE: return PIC16CC::UGE;
1676 case ISD::SETUGT: return PIC16CC::UGT;
1680 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1681 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1682 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1683 ISD::CondCode CC, unsigned &SPCC) {
1684 if (isa<ConstantSDNode>(RHS) &&
1685 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1687 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1688 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1689 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1690 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1691 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1692 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1693 SDValue CMPCC = LHS.getOperand(3);
1694 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1695 LHS = CMPCC.getOperand(0);
1696 RHS = CMPCC.getOperand(1);
1700 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1701 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1702 unsigned CC, SDValue &PIC16CC,
1703 SelectionDAG &DAG, DebugLoc dl) {
1704 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1706 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1707 // i.e. a < 12 can be rewritten as 12 > a.
1708 if (RHS.getOpcode() == ISD::Constant) {
1717 CondCode = PIC16CC::GT;
1720 CondCode = PIC16CC::LT;
1723 CondCode = PIC16CC::UGT;
1726 CondCode = PIC16CC::ULT;
1729 CondCode = PIC16CC::LE;
1732 CondCode = PIC16CC::GE;
1735 CondCode = PIC16CC::UGE;
1738 CondCode = PIC16CC::ULE;
1743 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1745 // These are signed comparisons.
1746 SDValue Mask = DAG.getConstant(128, MVT::i8);
1747 if (isSignedComparison(CondCode)) {
1748 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1749 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1752 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1753 // We can use a subtract operation to set the condition codes. But
1754 // we need to put one operand in memory if required.
1755 // Nothing to do if the first operand is already a valid type (direct load
1756 // for subwf and literal for sublw) and it is used by this operation only.
1757 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1759 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1761 // else convert the first operand to mem.
1762 LHS = ConvertToMemOperand (LHS, DAG, dl);
1763 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1767 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1768 SDValue LHS = Op.getOperand(0);
1769 SDValue RHS = Op.getOperand(1);
1770 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1771 SDValue TrueVal = Op.getOperand(2);
1772 SDValue FalseVal = Op.getOperand(3);
1773 unsigned ORIGCC = ~0;
1774 DebugLoc dl = Op.getDebugLoc();
1776 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1777 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1779 // A setcc: lhs, rhs, cc is expanded by llvm to
1780 // select_cc: result of setcc, 0, 1, 0, setne
1781 // We can think of it as:
1782 // select_cc: lhs, rhs, 1, 0, cc
1783 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1784 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1787 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1789 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1790 FalseVal, PIC16CC, Cmp.getValue(1));
1794 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1795 MachineBasicBlock *BB) const {
1796 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1797 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1798 DebugLoc dl = MI->getDebugLoc();
1800 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1801 // control-flow pattern. The incoming instruction knows the destination vreg
1802 // to set, the condition code register to branch on, the true/false values to
1803 // select between, and a branch opcode to use.
1804 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1805 MachineFunction::iterator It = BB;
1812 // fallthrough --> copy0MBB
1813 MachineBasicBlock *thisMBB = BB;
1814 MachineFunction *F = BB->getParent();
1815 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1816 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1817 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1818 F->insert(It, copy0MBB);
1819 F->insert(It, sinkMBB);
1821 // Update machine-CFG edges by transferring all successors of the current
1822 // block to the new block which will contain the Phi node for the select.
1823 sinkMBB->transferSuccessors(BB);
1824 // Next, add the true and fallthrough blocks as its successors.
1825 BB->addSuccessor(copy0MBB);
1826 BB->addSuccessor(sinkMBB);
1829 // %FalseValue = ...
1830 // # fallthrough to sinkMBB
1833 // Update machine-CFG edges
1834 BB->addSuccessor(sinkMBB);
1837 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1840 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1841 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1842 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1844 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1849 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1850 SDValue Chain = Op.getOperand(0);
1851 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1852 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1853 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1854 SDValue Dest = Op.getOperand(4); // BB to jump to
1855 unsigned ORIGCC = ~0;
1856 DebugLoc dl = Op.getDebugLoc();
1858 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1859 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1860 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1861 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1863 // Get the Compare insn and condition code.
1865 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1867 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,