2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
16 #include "PIC16ISelLowering.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 static const char *getIntrinsicName(unsigned opcode) {
33 default: assert (0 && "do not know intrinsic name");
34 // Arithmetic Right shift for integer types.
35 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
36 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
37 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
39 // Left shift for integer types.
40 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
41 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
42 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
44 // Logical Right Shift for integer types.
45 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
46 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
47 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
49 // Multiply for integer types.
50 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
51 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
52 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
54 // Signed division for integers.
55 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
56 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
58 // Unsigned division for integers.
59 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
60 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
62 // Signed Modulas for integers.
63 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
64 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
66 // Unsigned Modulas for integers.
67 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
68 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
70 //////////////////////
71 // LIBCALLS FOR FLOATS
72 //////////////////////
74 // Float to signed integrals
75 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
76 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
77 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
79 // Signed integrals to float. char and int are first sign extended to i32
80 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
81 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
83 // Float to Unsigned conversions.
84 // Signed conversion can be used for unsigned conversion as well.
85 // In signed and unsigned versions only the interpretation of the
86 // MSB is different. Bit representation remains the same.
87 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
88 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
89 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
91 // Unsigned to Float conversions. char and int are first zero extended
92 // before being converted to float.
93 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
95 // Floating point add, sub, mul, div.
96 case RTLIB::ADD_F32: Basename = "add.f32"; break;
97 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
98 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
99 case RTLIB::DIV_F32: Basename = "div.f32"; break;
101 // Floating point comparison
102 case RTLIB::O_F32: Basename = "unordered.f32"; break;
103 case RTLIB::UO_F32: Basename = "unordered.f32"; break;
104 case RTLIB::OLE_F32: Basename = "le.f32"; break;
105 case RTLIB::OGE_F32: Basename = "ge.f32"; break;
106 case RTLIB::OLT_F32: Basename = "lt.f32"; break;
107 case RTLIB::OGT_F32: Basename = "gt.f32"; break;
108 case RTLIB::OEQ_F32: Basename = "eq.f32"; break;
109 case RTLIB::UNE_F32: Basename = "neq.f32"; break;
112 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
113 std::string tagname = PAN::getTagName(PAN::LIBCALL);
114 std::string Fullname = prefix + tagname + Basename;
116 // The name has to live through program life.
117 char *tmp = new char[Fullname.size() + 1];
118 strcpy (tmp, Fullname.c_str());
123 // PIC16TargetLowering Constructor.
124 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
125 : TargetLowering(TM), TmpSize(0) {
127 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
129 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
131 setShiftAmountType(MVT::i8);
132 setShiftAmountFlavor(Extend);
134 // SRA library call names
135 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
136 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
137 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
139 // SHL library call names
140 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
141 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
142 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
144 // SRL library call names
145 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
146 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
147 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
149 // MUL Library call names
150 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
151 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
152 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
154 // Signed division lib call names
155 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
156 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
158 // Unsigned division lib call names
159 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
160 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
162 // Signed remainder lib call names
163 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
164 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
166 // Unsigned remainder lib call names
167 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
168 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
170 // Floating point to signed int conversions.
171 setLibcallName(RTLIB::FPTOSINT_F32_I8,
172 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
173 setLibcallName(RTLIB::FPTOSINT_F32_I16,
174 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
175 setLibcallName(RTLIB::FPTOSINT_F32_I32,
176 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
178 // Signed int to floats.
179 setLibcallName(RTLIB::SINTTOFP_I32_F32,
180 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
182 // Floating points to unsigned ints.
183 setLibcallName(RTLIB::FPTOUINT_F32_I8,
184 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
185 setLibcallName(RTLIB::FPTOUINT_F32_I16,
186 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
187 setLibcallName(RTLIB::FPTOUINT_F32_I32,
188 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
190 // Unsigned int to floats.
191 setLibcallName(RTLIB::UINTTOFP_I32_F32,
192 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
194 // Floating point add, sub, mul ,div.
195 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
196 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
197 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
198 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
200 // Floationg point comparison
201 setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32));
202 setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32));
203 setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32));
204 setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32));
205 setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32));
206 setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32));
207 setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32));
209 // Return value comparisons of floating point calls.
210 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
219 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
220 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
222 setOperationAction(ISD::LOAD, MVT::i8, Legal);
223 setOperationAction(ISD::LOAD, MVT::i16, Custom);
224 setOperationAction(ISD::LOAD, MVT::i32, Custom);
226 setOperationAction(ISD::STORE, MVT::i8, Legal);
227 setOperationAction(ISD::STORE, MVT::i16, Custom);
228 setOperationAction(ISD::STORE, MVT::i32, Custom);
230 setOperationAction(ISD::ADDE, MVT::i8, Custom);
231 setOperationAction(ISD::ADDC, MVT::i8, Custom);
232 setOperationAction(ISD::SUBE, MVT::i8, Custom);
233 setOperationAction(ISD::SUBC, MVT::i8, Custom);
234 setOperationAction(ISD::SUB, MVT::i8, Custom);
235 setOperationAction(ISD::ADD, MVT::i8, Custom);
236 setOperationAction(ISD::ADD, MVT::i16, Custom);
238 setOperationAction(ISD::OR, MVT::i8, Custom);
239 setOperationAction(ISD::AND, MVT::i8, Custom);
240 setOperationAction(ISD::XOR, MVT::i8, Custom);
242 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
243 setOperationAction(ISD::CALL, MVT::i16, Custom);
244 setOperationAction(ISD::RET, MVT::Other, Custom);
246 setOperationAction(ISD::MUL, MVT::i8, Custom);
247 setOperationAction(ISD::MUL, MVT::i16, Expand);
248 setOperationAction(ISD::MUL, MVT::i32, Expand);
250 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
251 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
252 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
253 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
254 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
255 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
256 setOperationAction(ISD::MULHU, MVT::i8, Expand);
257 setOperationAction(ISD::MULHU, MVT::i16, Expand);
258 setOperationAction(ISD::MULHU, MVT::i32, Expand);
259 setOperationAction(ISD::MULHS, MVT::i8, Expand);
260 setOperationAction(ISD::MULHS, MVT::i16, Expand);
261 setOperationAction(ISD::MULHS, MVT::i32, Expand);
263 setOperationAction(ISD::SRA, MVT::i8, Custom);
264 setOperationAction(ISD::SRA, MVT::i16, Expand);
265 setOperationAction(ISD::SRA, MVT::i32, Expand);
266 setOperationAction(ISD::SHL, MVT::i8, Custom);
267 setOperationAction(ISD::SHL, MVT::i16, Expand);
268 setOperationAction(ISD::SHL, MVT::i32, Expand);
269 setOperationAction(ISD::SRL, MVT::i8, Custom);
270 setOperationAction(ISD::SRL, MVT::i16, Expand);
271 setOperationAction(ISD::SRL, MVT::i32, Expand);
273 // PIC16 does not support shift parts
274 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
275 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
276 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
277 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
278 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
280 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
281 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
282 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
285 // PIC16 does not have a SETCC, expand it to SELECT_CC.
286 setOperationAction(ISD::SETCC, MVT::i8, Expand);
287 setOperationAction(ISD::SELECT, MVT::i8, Expand);
288 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
289 setOperationAction(ISD::BRIND, MVT::Other, Expand);
291 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
292 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
294 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
295 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
297 // Now deduce the information based on the above mentioned
299 computeRegisterProperties();
302 // getOutFlag - Extract the flag result if the Op has it.
303 static SDValue getOutFlag(SDValue &Op) {
304 // Flag is the last value of the node.
305 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
307 assert (Flag.getValueType() == MVT::Flag
308 && "Node does not have an out Flag");
312 // Get the TmpOffset for FrameIndex
313 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
314 std::map<unsigned, unsigned>::iterator
315 MapIt = FiTmpOffsetMap.find(FI);
316 if (MapIt != FiTmpOffsetMap.end())
317 return MapIt->second;
319 // This FI (FrameIndex) is not yet mapped, so map it
320 FiTmpOffsetMap[FI] = TmpSize;
322 return FiTmpOffsetMap[FI];
325 // To extract chain value from the SDValue Nodes
326 // This function will help to maintain the chain extracting
327 // code at one place. In case of any change in future it will
328 // help maintain the code.
329 static SDValue getChain(SDValue &Op) {
330 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
332 // If the last value returned in Flag then the chain is
333 // second last value returned.
334 if (Chain.getValueType() == MVT::Flag)
335 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
337 // All nodes may not produce a chain. Therefore following assert
338 // verifies that the node is returning a chain only.
339 assert (Chain.getValueType() == MVT::Other
340 && "Node does not have a chain");
345 /// PopulateResults - Helper function to LowerOperation.
346 /// If a node wants to return multiple results after lowering,
347 /// it stuffs them into an array of SDValue called Results.
349 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
350 if (N.getOpcode() == ISD::MERGE_VALUES) {
351 int NumResults = N.getNumOperands();
352 for( int i = 0; i < NumResults; i++)
353 Results.push_back(N.getOperand(i));
356 Results.push_back(N);
359 MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
363 /// The type legalizer framework of generating legalizer can generate libcalls
364 /// only when the operand/result types are illegal.
365 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
366 /// For example an arithmetic right shift. These functions are used to lower
367 /// such operations that generate libcall for legal types.
370 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
372 PIC16LibcallNames[Call] = Name;
376 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
377 return PIC16LibcallNames[Call];
381 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
382 MVT RetVT, const SDValue *Ops,
383 unsigned NumOps, bool isSigned,
384 SelectionDAG &DAG, DebugLoc dl) {
386 TargetLowering::ArgListTy Args;
387 Args.reserve(NumOps);
389 TargetLowering::ArgListEntry Entry;
390 for (unsigned i = 0; i != NumOps; ++i) {
392 Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
393 Entry.isSExt = isSigned;
394 Entry.isZExt = !isSigned;
395 Args.push_back(Entry);
397 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
399 const Type *RetTy = RetVT.getTypeForMVT();
400 std::pair<SDValue,SDValue> CallInfo =
401 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
402 false, CallingConv::C, false, Callee, Args, DAG, dl);
404 return CallInfo.first;
407 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
409 default: return NULL;
410 case PIC16ISD::Lo: return "PIC16ISD::Lo";
411 case PIC16ISD::Hi: return "PIC16ISD::Hi";
412 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
413 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
414 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
415 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
416 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
417 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
418 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
419 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
420 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
421 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
422 case PIC16ISD::BCF: return "PIC16ISD::BCF";
423 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
424 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
425 case PIC16ISD::RLF: return "PIC16ISD::RLF";
426 case PIC16ISD::RRF: return "PIC16ISD::RRF";
427 case PIC16ISD::CALL: return "PIC16ISD::CALL";
428 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
429 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
430 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
431 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
432 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
436 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
437 SmallVectorImpl<SDValue>&Results,
440 switch (N->getOpcode()) {
441 case ISD::GlobalAddress:
442 Results.push_back(ExpandGlobalAddress(N, DAG));
444 case ISD::ExternalSymbol:
445 Results.push_back(ExpandExternalSymbol(N, DAG));
448 Results.push_back(ExpandStore(N, DAG));
451 PopulateResults(ExpandLoad(N, DAG), Results);
454 // Results.push_back(ExpandAdd(N, DAG));
456 case ISD::FrameIndex:
457 Results.push_back(ExpandFrameIndex(N, DAG));
460 assert (0 && "not implemented");
465 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
467 // Currently handling FrameIndex of size MVT::i16 only
468 // One example of this scenario is when return value is written on
471 if (N->getValueType(0) != MVT::i16)
474 // Expand the FrameIndex into ExternalSymbol and a Constant node
475 // The constant will represent the frame index number
476 // Get the current function frame
477 MachineFunction &MF = DAG.getMachineFunction();
478 const Function *Func = MF.getFunction();
479 const std::string Name = Func->getName();
481 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
482 // FIXME there isn't really debug info here
483 DebugLoc dl = FR->getDebugLoc();
485 // Expand FrameIndex like GlobalAddress and ExternalSymbol
486 // Also use Offset field for lo and hi parts. The default
491 SDValue FI = SDValue(N,0);
492 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
493 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
494 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
495 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
496 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
500 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
501 StoreSDNode *St = cast<StoreSDNode>(N);
502 SDValue Chain = St->getChain();
503 SDValue Src = St->getValue();
504 SDValue Ptr = St->getBasePtr();
505 MVT ValueType = Src.getValueType();
506 unsigned StoreOffset = 0;
507 DebugLoc dl = N->getDebugLoc();
509 SDValue PtrLo, PtrHi;
510 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
512 if (ValueType == MVT::i8) {
513 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
515 DAG.getConstant (0 + StoreOffset, MVT::i8));
517 else if (ValueType == MVT::i16) {
518 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
519 SDValue SrcLo, SrcHi;
520 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
521 SDValue ChainLo = Chain, ChainHi = Chain;
522 if (Chain.getOpcode() == ISD::TokenFactor) {
523 ChainLo = Chain.getOperand(0);
524 ChainHi = Chain.getOperand(1);
526 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
529 DAG.getConstant (0 + StoreOffset, MVT::i8));
531 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
533 DAG.getConstant (1 + StoreOffset, MVT::i8));
535 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
538 else if (ValueType == MVT::i32) {
539 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
540 SDValue SrcLo, SrcHi;
541 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
543 // Get the expanded parts of each of SrcLo and SrcHi.
544 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
545 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
546 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
548 SDValue ChainLo = Chain, ChainHi = Chain;
549 if (Chain.getOpcode() == ISD::TokenFactor) {
550 ChainLo = Chain.getOperand(0);
551 ChainHi = Chain.getOperand(1);
553 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
555 if (ChainLo.getOpcode() == ISD::TokenFactor) {
556 ChainLo1 = ChainLo.getOperand(0);
557 ChainLo2 = ChainLo.getOperand(1);
559 if (ChainHi.getOpcode() == ISD::TokenFactor) {
560 ChainHi1 = ChainHi.getOperand(0);
561 ChainHi2 = ChainHi.getOperand(1);
563 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
565 SrcLo1, PtrLo, PtrHi,
566 DAG.getConstant (0 + StoreOffset, MVT::i8));
568 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
569 SrcLo2, PtrLo, PtrHi,
570 DAG.getConstant (1 + StoreOffset, MVT::i8));
572 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
573 SrcHi1, PtrLo, PtrHi,
574 DAG.getConstant (2 + StoreOffset, MVT::i8));
576 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
577 SrcHi2, PtrLo, PtrHi,
578 DAG.getConstant (3 + StoreOffset, MVT::i8));
580 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
581 getChain(Store1), getChain(Store2));
582 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
583 getChain(Store3), getChain(Store4));
584 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
588 assert (0 && "value type not supported");
593 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
595 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
596 // FIXME there isn't really debug info here
597 DebugLoc dl = ES->getDebugLoc();
599 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
600 SDValue Offset = DAG.getConstant(0, MVT::i8);
601 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
602 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
604 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
607 // ExpandGlobalAddress -
608 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
609 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
610 // FIXME there isn't really debug info here
611 DebugLoc dl = G->getDebugLoc();
613 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
616 SDValue Offset = DAG.getConstant(0, MVT::i8);
617 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
618 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
620 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
623 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
624 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
626 if (Op.getOpcode() == ISD::BUILD_PAIR) {
627 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
633 // Return true if DirectAddress is in ROM_SPACE
634 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
636 // RomAddress is a GlobalAddress in ROM_SPACE_
637 // If the Op is not a GlobalAddress return NULL without checking
639 if (!isDirectAddress(Op))
642 // Its a GlobalAddress.
643 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
644 SDValue TGA = Op.getOperand(0).getOperand(0);
645 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
647 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
650 // Any other address space return it false
655 // GetExpandedParts - This function is on the similiar lines as
656 // the GetExpandedInteger in type legalizer is. This returns expanded
657 // parts of Op in Lo and Hi.
659 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
660 SDValue &Lo, SDValue &Hi) {
661 SDNode *N = Op.getNode();
662 DebugLoc dl = N->getDebugLoc();
663 MVT NewVT = getTypeToTransformTo(N->getValueType(0));
665 // Extract the lo component.
666 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
667 DAG.getConstant(0, MVT::i8));
669 // extract the hi component
670 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
671 DAG.getConstant(1, MVT::i8));
674 // Legalize FrameIndex into ExternalSymbol and offset.
676 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
677 SDValue &ES, int &Offset) {
679 MachineFunction &MF = DAG.getMachineFunction();
680 const Function *Func = MF.getFunction();
681 MachineFrameInfo *MFI = MF.getFrameInfo();
682 const std::string Name = Func->getName();
684 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
686 // FrameIndices are not stack offsets. But they represent the request
687 // for space on stack. That space requested may be more than one byte.
688 // Therefore, to calculate the stack offset that a FrameIndex aligns
689 // with, we need to traverse all the FrameIndices available earlier in
690 // the list and add their requested size.
691 unsigned FIndex = FR->getIndex();
693 if (FIndex < ReservedFrameCount) {
694 tmpName = createESName(PAN::getFrameLabel(Name));
695 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
697 for (unsigned i=0; i<FIndex ; ++i) {
698 Offset += MFI->getObjectSize(i);
701 // FrameIndex has been made for some temporary storage
702 tmpName = createESName(PAN::getTempdataLabel(Name));
703 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
704 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
710 // This function legalizes the PIC16 Addresses. If the Pointer is
711 // -- Direct address variable residing
712 // --> then a Banksel for that variable will be created.
714 // --> then it will be treated as an indirect address.
715 // -- Indirect address
716 // --> then the address will be loaded into FSR
717 // -- ADD with constant operand
718 // --> then constant operand of ADD will be returned as Offset
719 // and non-constant operand of ADD will be treated as pointer.
720 // Returns the high and lo part of the address, and the offset(in case of ADD).
722 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
723 SDValue &Lo, SDValue &Hi,
724 unsigned &Offset, DebugLoc dl) {
726 // Offset, by default, should be 0
729 // If the pointer is ADD with constant,
730 // return the constant value as the offset
731 if (Ptr.getOpcode() == ISD::ADD) {
732 SDValue OperLeft = Ptr.getOperand(0);
733 SDValue OperRight = Ptr.getOperand(1);
734 if ((OperLeft.getOpcode() == ISD::Constant) &&
735 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
736 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
738 } else if ((OperRight.getOpcode() == ISD::Constant) &&
739 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
740 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
745 // If the pointer is Type i8 and an external symbol
746 // then treat it as direct address.
747 // One example for such case is storing and loading
748 // from function frame during a call
749 if (Ptr.getValueType() == MVT::i8) {
750 switch (Ptr.getOpcode()) {
751 case ISD::TargetExternalSymbol:
753 Hi = DAG.getConstant(1, MVT::i8);
758 // Expansion of FrameIndex has Lo/Hi parts
759 if (isDirectAddress(Ptr)) {
760 SDValue TFI = Ptr.getOperand(0).getOperand(0);
762 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
763 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
764 Hi = DAG.getConstant(1, MVT::i8);
765 Offset += FrameOffset;
767 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
768 // FrameIndex has already been expanded.
769 // Now just make use of its expansion
771 Hi = DAG.getConstant(1, MVT::i8);
772 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
773 assert (FOffset.getOpcode() == ISD::Constant &&
774 "Invalid operand of PIC16ISD::Lo");
775 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
780 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
781 // Direct addressing case for RAM variables. The Hi part is constant
782 // and the Lo part is the TGA itself.
783 Lo = Ptr.getOperand(0).getOperand(0);
785 // For direct addresses Hi is a constant. Value 1 for the constant
786 // signifies that banksel needs to generated for it. Value 0 for
787 // the constant signifies that banksel does not need to be generated
788 // for it. Mark it as 1 now and optimize later.
789 Hi = DAG.getConstant(1, MVT::i8);
793 // Indirect addresses. Get the hi and lo parts of ptr.
794 GetExpandedParts(Ptr, DAG, Lo, Hi);
796 // Put the hi and lo parts into FSR.
797 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
798 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
803 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
804 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
805 SDValue Chain = LD->getChain();
806 SDValue Ptr = LD->getBasePtr();
807 DebugLoc dl = LD->getDebugLoc();
809 SDValue Load, Offset;
812 SDValue PtrLo, PtrHi;
815 // Legalize direct/indirect addresses. This will give the lo and hi parts
816 // of the address and the offset.
817 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
819 // Load from the pointer (direct address or FSR)
820 VT = N->getValueType(0);
821 unsigned NumLoads = VT.getSizeInBits() / 8;
822 std::vector<SDValue> PICLoads;
824 MVT MemVT = LD->getMemoryVT();
825 if(ISD::isNON_EXTLoad(N)) {
826 for (iter=0; iter<NumLoads ; ++iter) {
827 // Add the pointer offset if any
828 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
829 Tys = DAG.getVTList(MVT::i8, MVT::Other);
830 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
832 PICLoads.push_back(Load);
835 // If it is extended load then use PIC16Load for Memory Bytes
836 // and for all extended bytes perform action based on type of
837 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
840 // For extended loads this is the memory value type
841 // i.e. without any extension
842 MVT MemVT = LD->getMemoryVT();
843 unsigned MemBytes = MemVT.getSizeInBits() / 8;
844 unsigned ExtdBytes = VT.getSizeInBits() / 8;
845 Offset = DAG.getConstant(LoadOffset, MVT::i8);
847 Tys = DAG.getVTList(MVT::i8, MVT::Other);
848 // For MemBytes generate PIC16Load with proper offset
849 for (iter=0; iter<MemBytes; ++iter) {
850 // Add the pointer offset if any
851 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
852 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
854 PICLoads.push_back(Load);
857 // For SignExtendedLoad
858 if (ISD::isSEXTLoad(N)) {
859 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
861 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
862 DAG.getConstant(7, MVT::i8));
863 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
864 PICLoads.push_back(SRA);
866 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
867 //} else if (ISD::isZEXTLoad(N)) {
868 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
869 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
870 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
871 PICLoads.push_back(ConstZero);
878 // Operand of Load is illegal -- Load itself is legal
881 else if (VT == MVT::i16) {
882 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
883 if (MemVT == MVT::i8)
884 Chain = getChain(PICLoads[0]);
886 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
887 getChain(PICLoads[0]), getChain(PICLoads[1]));
888 } else if (VT == MVT::i32) {
890 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
891 PICLoads[0], PICLoads[1]);
892 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
893 PICLoads[2], PICLoads[3]);
894 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
895 if (MemVT == MVT::i8)
896 Chain = getChain(PICLoads[0]);
897 else if (MemVT == MVT::i16)
898 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
899 getChain(PICLoads[0]), getChain(PICLoads[1]));
902 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
903 getChain(PICLoads[0]), getChain(PICLoads[1]));
904 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
905 getChain(PICLoads[2]), getChain(PICLoads[3]));
906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
907 Chains[0], Chains[1]);
910 Tys = DAG.getVTList(VT, MVT::Other);
911 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
914 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
915 // We should have handled larger operands in type legalizer itself.
916 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
918 SDNode *N = Op.getNode();
919 SDValue Value = N->getOperand(0);
920 SDValue Amt = N->getOperand(1);
921 PIC16ISD::PIC16Libcall CallCode;
922 switch (N->getOpcode()) {
924 CallCode = PIC16ISD::SRA_I8;
927 CallCode = PIC16ISD::SLL_I8;
930 CallCode = PIC16ISD::SRL_I8;
933 assert ( 0 && "This shift is not implemented yet.");
936 SmallVector<SDValue, 2> Ops(2);
939 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
940 true, DAG, N->getDebugLoc());
945 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
946 SmallVectorImpl<SDValue>&Results,
948 SDValue Op = SDValue(N, 0);
951 switch (Op.getOpcode()) {
952 case ISD::FORMAL_ARGUMENTS:
953 Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
955 Res = ExpandLoad(Op.getNode(), DAG); break;
957 Res = LowerCALL(Op, DAG); break;
959 // All other operations are handled in LowerOperation.
960 Res = LowerOperation(Op, DAG);
962 Results.push_back(Res);
969 unsigned NumValues = N->getNumValues();
970 for (i = 0; i < NumValues ; i++) {
971 Results.push_back(SDValue(N, i));
975 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
976 switch (Op.getOpcode()) {
977 case ISD::FORMAL_ARGUMENTS:
978 return LowerFORMAL_ARGUMENTS(Op, DAG);
982 return LowerADD(Op, DAG);
986 return LowerSUB(Op, DAG);
988 return ExpandLoad(Op.getNode(), DAG);
990 return ExpandStore(Op.getNode(), DAG);
994 return LowerShift(Op, DAG);
998 return LowerBinOp(Op, DAG);
1000 return LowerCALL(Op, DAG);
1002 return LowerRET(Op, DAG);
1004 return LowerBR_CC(Op, DAG);
1005 case ISD::SELECT_CC:
1006 return LowerSELECT_CC(Op, DAG);
1011 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
1014 assert (Op.getValueType() == MVT::i8
1015 && "illegal value type to store on stack.");
1017 MachineFunction &MF = DAG.getMachineFunction();
1018 const Function *Func = MF.getFunction();
1019 const std::string FuncName = Func->getName();
1022 // Put the value on stack.
1023 // Get a stack slot index and convert to es.
1024 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
1025 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
1026 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1028 // Store the value to ES.
1029 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1032 DAG.getConstant (1, MVT::i8), // Banksel.
1033 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1036 // Load the value from ES.
1037 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1038 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1039 ES, DAG.getConstant (1, MVT::i8),
1040 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1043 return Load.getValue(0);
1046 SDValue PIC16TargetLowering::
1047 LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag,
1048 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1049 SelectionDAG &DAG) {
1050 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1051 unsigned NumOps = TheCall->getNumArgs();
1052 DebugLoc dl = TheCall->getDebugLoc();
1054 // If call has no arguments then do nothing and return.
1058 std::vector<SDValue> Ops;
1059 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1060 SDValue Arg, StoreRet;
1062 // For PIC16 ABI the arguments come after the return value.
1063 unsigned RetVals = TheCall->getNumRetVals();
1064 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1065 // Get the arguments
1066 Arg = TheCall->getArg(i);
1069 Ops.push_back(Chain);
1071 Ops.push_back(DataAddr_Lo);
1072 Ops.push_back(DataAddr_Hi);
1073 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1074 Ops.push_back(InFlag);
1076 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1078 Chain = getChain(StoreRet);
1079 InFlag = getOutFlag(StoreRet);
1085 SDValue PIC16TargetLowering::
1086 LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue ArgLabel,
1087 SDValue InFlag, SelectionDAG &DAG) {
1088 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1089 unsigned NumOps = TheCall->getNumArgs();
1090 DebugLoc dl = TheCall->getDebugLoc();
1092 SDValue Arg, StoreAt;
1095 unsigned ArgCount=0;
1097 // If call has no arguments then do nothing and return.
1101 // FIXME: This portion of code currently assumes only
1102 // primitive types being passed as arguments.
1104 // Legalize the address before use
1105 SDValue PtrLo, PtrHi;
1106 unsigned AddressOffset;
1107 int StoreOffset = 0;
1108 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1111 std::vector<SDValue> Ops;
1112 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1113 for (unsigned i=ArgCount, Offset = 0; i<NumOps; i++) {
1115 Arg = TheCall->getArg(i);
1116 StoreOffset = (Offset + AddressOffset);
1118 // Store the argument on frame
1121 Ops.push_back(Chain);
1123 Ops.push_back(PtrLo);
1124 Ops.push_back(PtrHi);
1125 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1126 Ops.push_back(InFlag);
1128 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1130 Chain = getChain(StoreRet);
1131 InFlag = getOutFlag(StoreRet);
1133 // Update the frame offset to be used for next argument
1134 ArgVT = Arg.getValueType();
1135 Size = ArgVT.getSizeInBits();
1136 Size = Size/8; // Calculate size in bytes
1137 Offset += Size; // Increase the frame offset
1142 SDValue PIC16TargetLowering::
1143 LowerIndirectCallReturn (SDValue Op, SDValue Chain, SDValue InFlag,
1144 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1145 SelectionDAG &DAG) {
1146 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1147 DebugLoc dl = TheCall->getDebugLoc();
1148 unsigned RetVals = TheCall->getNumRetVals();
1150 // If call does not have anything to return
1151 // then do nothing and go back.
1155 // Call has something to return
1156 std::vector<SDValue> ResultVals;
1159 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1160 for(unsigned i=0;i<RetVals;i++) {
1161 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1162 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1164 InFlag = getOutFlag(LoadRet);
1165 Chain = getChain(LoadRet);
1166 ResultVals.push_back(LoadRet);
1168 ResultVals.push_back(Chain);
1169 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1173 SDValue PIC16TargetLowering::
1174 LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue RetLabel,
1175 SDValue InFlag, SelectionDAG &DAG) {
1176 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1177 DebugLoc dl = TheCall->getDebugLoc();
1178 // Currently handling primitive types only. They will come in
1180 unsigned RetVals = TheCall->getNumRetVals();
1182 std::vector<SDValue> ResultVals;
1184 // Return immediately if the return type is void
1188 // Call has something to return
1190 // Legalize the address before use
1193 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1195 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1198 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1200 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1201 DAG.getConstant(LdOffset + Offset, MVT::i8),
1204 InFlag = getOutFlag(LoadRet);
1206 Chain = getChain(LoadRet);
1208 ResultVals.push_back(LoadRet);
1211 // To return use MERGE_VALUES
1212 ResultVals.push_back(Chain);
1213 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
1217 SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1218 SDValue Chain = Op.getOperand(0);
1219 DebugLoc dl = Op.getDebugLoc();
1221 if (Op.getNumOperands() == 1) // return void
1224 // return should have odd number of operands
1225 if ((Op.getNumOperands() % 2) == 0 ) {
1226 assert(0 && "Do not know how to return this many arguments!");
1230 // Number of values to return
1231 unsigned NumRet = (Op.getNumOperands() / 2);
1233 // Function returns value always on stack with the offset starting
1235 MachineFunction &MF = DAG.getMachineFunction();
1236 const Function *F = MF.getFunction();
1237 std::string FuncName = F->getName();
1239 const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
1240 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1241 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1242 SDValue BS = DAG.getConstant(1, MVT::i8);
1244 for(unsigned i=0;i<NumRet; ++i) {
1245 RetVal = Op.getNode()->getOperand(2*i + 1);
1246 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1248 DAG.getConstant (i, MVT::i8));
1251 return DAG.getNode(ISD::RET, dl, MVT::Other, Chain);
1254 // CALL node may have some operands non-legal to PIC16. Generate new CALL
1255 // node with all the operands legal.
1256 // Currently only Callee operand of the CALL node is non-legal. This function
1257 // legalizes the Callee operand and uses all other operands as are to generate
1260 SDValue PIC16TargetLowering::LegalizeCALL(SDValue Op, SelectionDAG &DAG) {
1261 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1262 SDValue Chain = TheCall->getChain();
1263 SDValue Callee = TheCall->getCallee();
1264 DebugLoc dl = TheCall->getDebugLoc();
1267 assert(Callee.getValueType() == MVT::i16 &&
1268 "Don't know how to legalize this call node!!!");
1269 assert(Callee.getOpcode() == ISD::BUILD_PAIR &&
1270 "Don't know how to legalize this call node!!!");
1272 if (isDirectAddress(Callee)) {
1273 // Come here for direct calls
1274 Callee = Callee.getOperand(0).getOperand(0);
1276 // Come here for indirect calls
1278 // Indirect addresses. Get the hi and lo parts of ptr.
1279 GetExpandedParts(Callee, DAG, Lo, Hi);
1280 // Connect Lo and Hi parts of the callee with the PIC16Connect
1281 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1283 std::vector<SDValue> Ops;
1284 Ops.push_back(Chain);
1285 Ops.push_back(Callee);
1287 // Add the call arguments and their flags
1288 unsigned NumArgs = TheCall->getNumArgs();
1289 for(i=0;i<NumArgs;i++) {
1290 Ops.push_back(TheCall->getArg(i));
1291 Ops.push_back(TheCall->getArgFlagsVal(i));
1293 std::vector<MVT> NodeTys;
1294 unsigned NumRets = TheCall->getNumRetVals();
1295 for(i=0;i<NumRets;i++)
1296 NodeTys.push_back(TheCall->getRetValType(i));
1298 // Return a Chain as well
1299 NodeTys.push_back(MVT::Other);
1301 SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
1302 // Generate new call with all the operands legal
1303 return DAG.getCall(TheCall->getCallingConv(), dl,
1304 TheCall->isVarArg(), TheCall->isTailCall(),
1305 TheCall->isInreg(), VTs, &Ops[0], Ops.size());
1308 void PIC16TargetLowering::
1309 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1310 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1311 SelectionDAG &DAG) {
1312 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1313 && "Don't know what to do of such callee!!");
1314 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1315 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1316 Chain = getChain(SeqStart);
1317 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1319 // Get the Lo and Hi part of code address
1320 SDValue Lo = Callee.getOperand(0);
1321 SDValue Hi = Callee.getOperand(1);
1323 SDValue Data_Lo, Data_Hi;
1324 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1325 // Subtract 2 from Address to get the Lower part of DataAddress.
1326 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1327 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1328 DAG.getConstant(2, MVT::i8));
1329 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1330 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1331 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1332 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1333 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1335 Chain = getChain(Call);
1336 OperFlag = getOutFlag(Call);
1337 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1339 Chain = getChain(SeqEnd);
1340 OperFlag = getOutFlag(SeqEnd);
1342 // Low part of Data Address
1343 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1345 // Make the second call.
1346 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1347 Chain = getChain(SeqStart);
1348 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1350 // Subtract 1 from Address to get high part of data address.
1351 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1352 DAG.getConstant(1, MVT::i8));
1353 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1354 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1355 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1357 // Use new Lo to make another CALLW
1358 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1359 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1360 Chain = getChain(Call);
1361 OperFlag = getOutFlag(Call);
1362 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1364 Chain = getChain(SeqEnd);
1365 OperFlag = getOutFlag(SeqEnd);
1366 // Hi part of Data Address
1367 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1371 SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1372 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
1373 SDValue Chain = TheCall->getChain();
1374 SDValue Callee = TheCall->getCallee();
1375 DebugLoc dl = TheCall->getDebugLoc();
1376 if (Callee.getValueType() == MVT::i16 &&
1377 Callee.getOpcode() == ISD::BUILD_PAIR) {
1378 // Control should come here only from TypeLegalizer for lowering
1380 // Legalize the non-legal arguments of call and return the
1381 // new call with legal arguments.
1382 return LegalizeCALL(Op, DAG);
1384 // Control should come here from Legalize DAG.
1385 // Here all the operands of CALL node should be legal.
1387 // If this is an indirect call then to pass the arguments
1388 // and read the return value back, we need the data address
1389 // of the function being called.
1390 // To get the data address two more calls need to be made.
1392 // The flag to track if this is a direct or indirect call.
1393 bool IsDirectCall = true;
1394 unsigned RetVals = TheCall->getNumRetVals();
1395 unsigned NumArgs = TheCall->getNumArgs();
1397 SDValue DataAddr_Lo, DataAddr_Hi;
1398 if (Callee.getOpcode() == PIC16ISD::PIC16Connect) {
1399 IsDirectCall = false; // This is indirect call
1400 // Read DataAddress only if we have to pass arguments or
1401 // read return value.
1402 if ((RetVals > 0) || (NumArgs > 0))
1403 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1406 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1408 // Start the call sequence.
1409 // Carring the Constant 0 along the CALLSEQSTART
1410 // because there is nothing else to carry.
1411 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1412 Chain = getChain(SeqStart);
1413 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1416 // For any direct call - callee will be GlobalAddressNode or
1418 SDValue ArgLabel, RetLabel;
1420 // Considering the GlobalAddressNode case here.
1421 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1422 GlobalValue *GV = G->getGlobal();
1423 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1424 Name = G->getGlobal()->getName();
1425 } else {// Considering the ExternalSymbol case here
1426 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1427 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1428 Name = ES->getSymbol();
1431 // Label for argument passing
1432 const char *argFrame = createESName(PAN::getArgsLabel(Name));
1433 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1435 // Label for reading return value
1436 const char *retName = createESName(PAN::getRetvalLabel(Name));
1437 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1440 SDValue CodeAddr_Lo = Callee.getOperand(0);
1441 SDValue CodeAddr_Hi = Callee.getOperand(1);
1443 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1444 DAG.getConstant(2, MVT::i8));*/
1446 // move Hi part in PCLATH
1447 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1448 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1452 // Pass the argument to function before making the call.
1455 CallArgs = LowerDirectCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
1456 Chain = getChain(CallArgs);
1457 OperFlag = getOutFlag(CallArgs);
1459 CallArgs = LowerIndirectCallArguments(Op, Chain, OperFlag, DataAddr_Lo,
1461 Chain = getChain(CallArgs);
1462 OperFlag = getOutFlag(CallArgs);
1465 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1466 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1468 Chain = getChain(PICCall);
1469 OperFlag = getOutFlag(PICCall);
1472 // Carrying the Constant 0 along the CALLSEQSTART
1473 // because there is nothing else to carry.
1474 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1476 Chain = getChain(SeqEnd);
1477 OperFlag = getOutFlag(SeqEnd);
1479 // Lower the return value reading after the call.
1481 return LowerDirectCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
1483 return LowerIndirectCallReturn(Op, Chain, OperFlag, DataAddr_Lo,
1487 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1488 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1489 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1490 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1495 // NeedToConvertToMemOp - Returns true if one of the operands of the
1496 // operation 'Op' needs to be put into memory. Also returns the
1497 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1498 // no instruction that can operation on two registers. Most insns take
1499 // one register and one memory operand (addwf) / Constant (addlw).
1500 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1501 // If one of the operand is a constant, return false.
1502 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1503 Op.getOperand(1).getOpcode() == ISD::Constant)
1506 // Return false if one of the operands is already a direct
1507 // load and that operand has only one use.
1508 if (isDirectLoad(Op.getOperand(0))) {
1509 if (Op.getOperand(0).hasOneUse())
1514 if (isDirectLoad(Op.getOperand(1))) {
1515 if (Op.getOperand(1).hasOneUse())
1523 // LowerBinOp - Lower a commutative binary operation that does not
1524 // affect status flag carry.
1525 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1526 DebugLoc dl = Op.getDebugLoc();
1528 // We should have handled larger operands in type legalizer itself.
1529 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1532 if (NeedToConvertToMemOp(Op, MemOp)) {
1533 // Put one value on stack.
1534 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1536 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1544 // LowerADD - Lower all types of ADD operations including the ones
1545 // that affects carry.
1546 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1547 // We should have handled larger operands in type legalizer itself.
1548 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1549 DebugLoc dl = Op.getDebugLoc();
1551 if (NeedToConvertToMemOp(Op, MemOp)) {
1552 // Put one value on stack.
1553 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1555 // ADDC and ADDE produce two results.
1556 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1558 // ADDE has three operands, the last one is the carry bit.
1559 if (Op.getOpcode() == ISD::ADDE)
1560 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1561 NewVal, Op.getOperand(2));
1562 // ADDC has two operands.
1563 else if (Op.getOpcode() == ISD::ADDC)
1564 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1566 // ADD it is. It produces only one result.
1568 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1575 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1576 DebugLoc dl = Op.getDebugLoc();
1577 // We should have handled larger operands in type legalizer itself.
1578 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1580 // Nothing to do if the first operand is already a direct load and it has
1582 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1585 // Put first operand on stack.
1586 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1588 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1589 if (Op.getOpcode() == ISD::SUBE)
1590 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1593 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1596 void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
1597 unsigned NumArgs = F->arg_size();
1599 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1602 ReservedFrameCount = NumArgs;
1604 ReservedFrameCount = NumArgs + 1;
1607 // LowerFORMAL_ARGUMENTS - Argument values are loaded from the
1608 // <fname>.args + offset. All arguments are already broken to leaglized
1609 // types, so the offset just runs from 0 to NumArgVals - 1.
1611 SDValue PIC16TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1612 SelectionDAG &DAG) {
1613 SmallVector<SDValue, 8> ArgValues;
1614 unsigned NumArgVals = Op.getNode()->getNumValues() - 1;
1615 DebugLoc dl = Op.getDebugLoc();
1616 SDValue Chain = Op.getOperand(0); // Formal arguments' chain
1619 // Get the callee's name to create the <fname>.args label to pass args.
1620 MachineFunction &MF = DAG.getMachineFunction();
1621 const Function *F = MF.getFunction();
1622 std::string FuncName = F->getName();
1624 // Reset the map of FI and TmpOffset
1625 ResetTmpOffsetMap();
1626 // Initialize the ReserveFrameCount
1627 InitReservedFrameCount(F);
1629 // Create the <fname>.args external symbol.
1630 const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
1631 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1633 // Load arg values from the label + offset.
1634 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1635 SDValue BS = DAG.getConstant(1, MVT::i8);
1636 for (unsigned i = 0; i < NumArgVals ; ++i) {
1637 SDValue Offset = DAG.getConstant(i, MVT::i8);
1638 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1640 Chain = getChain(PICLoad);
1641 ArgValues.push_back(PICLoad);
1644 // Return a MERGE_VALUE node.
1645 ArgValues.push_back(Op.getOperand(0));
1646 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1647 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1650 // Perform DAGCombine of PIC16Load.
1651 // FIXME - Need a more elaborate comment here.
1652 SDValue PIC16TargetLowering::
1653 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1654 SelectionDAG &DAG = DCI.DAG;
1655 SDValue Chain = N->getOperand(0);
1656 if (N->hasNUsesOfValue(0, 0)) {
1657 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1662 // For all the functions with arguments some STORE nodes are generated
1663 // that store the argument on the frameindex. However in PIC16 the arguments
1664 // are passed on stack only. Therefore these STORE nodes are redundant.
1665 // To remove these STORE nodes will be removed in PerformStoreCombine
1667 // Currently this function is doint nothing and will be updated for removing
1668 // unwanted store operations
1669 SDValue PIC16TargetLowering::
1670 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1671 return SDValue(N, 0);
1673 // Storing an undef value is of no use, so remove it
1674 if (isStoringUndef(N, Chain, DAG)) {
1675 return Chain; // remove the store and return the chain
1677 //else everything is ok.
1678 return SDValue(N, 0);
1682 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1683 DAGCombinerInfo &DCI) const {
1684 switch (N->getOpcode()) {
1686 return PerformStoreCombine(N, DCI);
1687 case PIC16ISD::PIC16Load:
1688 return PerformPIC16LoadCombine(N, DCI);
1693 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1695 default: assert(0 && "Unknown condition code!");
1696 case ISD::SETNE: return PIC16CC::NE;
1697 case ISD::SETEQ: return PIC16CC::EQ;
1698 case ISD::SETGT: return PIC16CC::GT;
1699 case ISD::SETGE: return PIC16CC::GE;
1700 case ISD::SETLT: return PIC16CC::LT;
1701 case ISD::SETLE: return PIC16CC::LE;
1702 case ISD::SETULT: return PIC16CC::ULT;
1703 case ISD::SETULE: return PIC16CC::ULE;
1704 case ISD::SETUGE: return PIC16CC::UGE;
1705 case ISD::SETUGT: return PIC16CC::UGT;
1709 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1710 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1711 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1712 ISD::CondCode CC, unsigned &SPCC) {
1713 if (isa<ConstantSDNode>(RHS) &&
1714 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1716 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1717 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1718 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1719 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1720 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1721 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1722 SDValue CMPCC = LHS.getOperand(3);
1723 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1724 LHS = CMPCC.getOperand(0);
1725 RHS = CMPCC.getOperand(1);
1729 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1730 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1731 unsigned CC, SDValue &PIC16CC,
1732 SelectionDAG &DAG, DebugLoc dl) {
1733 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1735 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1736 // i.e. a < 12 can be rewritten as 12 > a.
1737 if (RHS.getOpcode() == ISD::Constant) {
1746 CondCode = PIC16CC::GT;
1749 CondCode = PIC16CC::LT;
1752 CondCode = PIC16CC::UGT;
1755 CondCode = PIC16CC::ULT;
1758 CondCode = PIC16CC::LE;
1761 CondCode = PIC16CC::GE;
1764 CondCode = PIC16CC::UGE;
1767 CondCode = PIC16CC::ULE;
1772 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1774 // These are signed comparisons.
1775 SDValue Mask = DAG.getConstant(128, MVT::i8);
1776 if (isSignedComparison(CondCode)) {
1777 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1778 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1781 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1782 // We can use a subtract operation to set the condition codes. But
1783 // we need to put one operand in memory if required.
1784 // Nothing to do if the first operand is already a valid type (direct load
1785 // for subwf and literal for sublw) and it is used by this operation only.
1786 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1788 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1790 // else convert the first operand to mem.
1791 LHS = ConvertToMemOperand (LHS, DAG, dl);
1792 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1796 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1797 SDValue LHS = Op.getOperand(0);
1798 SDValue RHS = Op.getOperand(1);
1799 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1800 SDValue TrueVal = Op.getOperand(2);
1801 SDValue FalseVal = Op.getOperand(3);
1802 unsigned ORIGCC = ~0;
1803 DebugLoc dl = Op.getDebugLoc();
1805 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1806 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1808 // A setcc: lhs, rhs, cc is expanded by llvm to
1809 // select_cc: result of setcc, 0, 1, 0, setne
1810 // We can think of it as:
1811 // select_cc: lhs, rhs, 1, 0, cc
1812 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1813 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1816 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1818 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1819 FalseVal, PIC16CC, Cmp.getValue(1));
1823 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1824 MachineBasicBlock *BB) const {
1825 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1826 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1827 DebugLoc dl = MI->getDebugLoc();
1829 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1830 // control-flow pattern. The incoming instruction knows the destination vreg
1831 // to set, the condition code register to branch on, the true/false values to
1832 // select between, and a branch opcode to use.
1833 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1834 MachineFunction::iterator It = BB;
1841 // fallthrough --> copy0MBB
1842 MachineBasicBlock *thisMBB = BB;
1843 MachineFunction *F = BB->getParent();
1844 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1845 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1846 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1847 F->insert(It, copy0MBB);
1848 F->insert(It, sinkMBB);
1850 // Update machine-CFG edges by transferring all successors of the current
1851 // block to the new block which will contain the Phi node for the select.
1852 sinkMBB->transferSuccessors(BB);
1853 // Next, add the true and fallthrough blocks as its successors.
1854 BB->addSuccessor(copy0MBB);
1855 BB->addSuccessor(sinkMBB);
1858 // %FalseValue = ...
1859 // # fallthrough to sinkMBB
1862 // Update machine-CFG edges
1863 BB->addSuccessor(sinkMBB);
1866 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1869 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1870 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1871 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1873 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1878 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1879 SDValue Chain = Op.getOperand(0);
1880 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1881 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1882 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1883 SDValue Dest = Op.getOperand(4); // BB to jump to
1884 unsigned ORIGCC = ~0;
1885 DebugLoc dl = Op.getDebugLoc();
1887 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1888 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1889 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1890 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1892 // Get the Compare insn and condition code.
1894 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1896 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,