2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
15 #include "PIC16ABINames.h"
16 #include "PIC16ISelLowering.h"
17 #include "PIC16TargetObjectFile.h"
18 #include "PIC16TargetMachine.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Function.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Support/ErrorHandling.h"
32 static const char *getIntrinsicName(unsigned opcode) {
35 default: llvm_unreachable("do not know intrinsic name");
36 // Arithmetic Right shift for integer types.
37 case PIC16ISD::SRA_I8: Basename = "sra.i8"; break;
38 case RTLIB::SRA_I16: Basename = "sra.i16"; break;
39 case RTLIB::SRA_I32: Basename = "sra.i32"; break;
41 // Left shift for integer types.
42 case PIC16ISD::SLL_I8: Basename = "sll.i8"; break;
43 case RTLIB::SHL_I16: Basename = "sll.i16"; break;
44 case RTLIB::SHL_I32: Basename = "sll.i32"; break;
46 // Logical Right Shift for integer types.
47 case PIC16ISD::SRL_I8: Basename = "srl.i8"; break;
48 case RTLIB::SRL_I16: Basename = "srl.i16"; break;
49 case RTLIB::SRL_I32: Basename = "srl.i32"; break;
51 // Multiply for integer types.
52 case PIC16ISD::MUL_I8: Basename = "mul.i8"; break;
53 case RTLIB::MUL_I16: Basename = "mul.i16"; break;
54 case RTLIB::MUL_I32: Basename = "mul.i32"; break;
56 // Signed division for integers.
57 case RTLIB::SDIV_I16: Basename = "sdiv.i16"; break;
58 case RTLIB::SDIV_I32: Basename = "sdiv.i32"; break;
60 // Unsigned division for integers.
61 case RTLIB::UDIV_I16: Basename = "udiv.i16"; break;
62 case RTLIB::UDIV_I32: Basename = "udiv.i32"; break;
64 // Signed Modulas for integers.
65 case RTLIB::SREM_I16: Basename = "srem.i16"; break;
66 case RTLIB::SREM_I32: Basename = "srem.i32"; break;
68 // Unsigned Modulas for integers.
69 case RTLIB::UREM_I16: Basename = "urem.i16"; break;
70 case RTLIB::UREM_I32: Basename = "urem.i32"; break;
72 //////////////////////
73 // LIBCALLS FOR FLOATS
74 //////////////////////
76 // Float to signed integrals
77 case RTLIB::FPTOSINT_F32_I8: Basename = "f32_to_si32"; break;
78 case RTLIB::FPTOSINT_F32_I16: Basename = "f32_to_si32"; break;
79 case RTLIB::FPTOSINT_F32_I32: Basename = "f32_to_si32"; break;
81 // Signed integrals to float. char and int are first sign extended to i32
82 // before being converted to float, so an I8_F32 or I16_F32 isn't required.
83 case RTLIB::SINTTOFP_I32_F32: Basename = "si32_to_f32"; break;
85 // Float to Unsigned conversions.
86 // Signed conversion can be used for unsigned conversion as well.
87 // In signed and unsigned versions only the interpretation of the
88 // MSB is different. Bit representation remains the same.
89 case RTLIB::FPTOUINT_F32_I8: Basename = "f32_to_si32"; break;
90 case RTLIB::FPTOUINT_F32_I16: Basename = "f32_to_si32"; break;
91 case RTLIB::FPTOUINT_F32_I32: Basename = "f32_to_si32"; break;
93 // Unsigned to Float conversions. char and int are first zero extended
94 // before being converted to float.
95 case RTLIB::UINTTOFP_I32_F32: Basename = "ui32_to_f32"; break;
97 // Floating point add, sub, mul, div.
98 case RTLIB::ADD_F32: Basename = "add.f32"; break;
99 case RTLIB::SUB_F32: Basename = "sub.f32"; break;
100 case RTLIB::MUL_F32: Basename = "mul.f32"; break;
101 case RTLIB::DIV_F32: Basename = "div.f32"; break;
103 // Floating point comparison
104 case RTLIB::O_F32: Basename = "unordered.f32"; break;
105 case RTLIB::UO_F32: Basename = "unordered.f32"; break;
106 case RTLIB::OLE_F32: Basename = "le.f32"; break;
107 case RTLIB::OGE_F32: Basename = "ge.f32"; break;
108 case RTLIB::OLT_F32: Basename = "lt.f32"; break;
109 case RTLIB::OGT_F32: Basename = "gt.f32"; break;
110 case RTLIB::OEQ_F32: Basename = "eq.f32"; break;
111 case RTLIB::UNE_F32: Basename = "neq.f32"; break;
114 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
115 std::string tagname = PAN::getTagName(PAN::LIBCALL);
116 std::string Fullname = prefix + tagname + Basename;
118 // The name has to live through program life.
119 return createESName(Fullname);
122 // getStdLibCallName - Get the name for the standard library function.
123 static const char *getStdLibCallName(unsigned opcode) {
124 std::string BaseName;
126 case RTLIB::COS_F32: BaseName = "cos";
128 case RTLIB::SIN_F32: BaseName = "sin";
130 case RTLIB::MEMCPY: BaseName = "memcpy";
132 case RTLIB::MEMSET: BaseName = "memset";
134 case RTLIB::MEMMOVE: BaseName = "memmove";
136 default: llvm_unreachable("do not know std lib call name");
138 std::string prefix = PAN::getTagName(PAN::PREFIX_SYMBOL);
139 std::string LibCallName = prefix + BaseName;
141 // The name has to live through program life.
142 return createESName(LibCallName);
145 // PIC16TargetLowering Constructor.
146 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
147 : TargetLowering(TM, new PIC16TargetObjectFile()), TmpSize(0) {
149 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
151 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
153 setShiftAmountType(MVT::i8);
155 // Std lib call names
156 setLibcallName(RTLIB::COS_F32, getStdLibCallName(RTLIB::COS_F32));
157 setLibcallName(RTLIB::SIN_F32, getStdLibCallName(RTLIB::SIN_F32));
158 setLibcallName(RTLIB::MEMCPY, getStdLibCallName(RTLIB::MEMCPY));
159 setLibcallName(RTLIB::MEMSET, getStdLibCallName(RTLIB::MEMSET));
160 setLibcallName(RTLIB::MEMMOVE, getStdLibCallName(RTLIB::MEMMOVE));
162 // SRA library call names
163 setPIC16LibcallName(PIC16ISD::SRA_I8, getIntrinsicName(PIC16ISD::SRA_I8));
164 setLibcallName(RTLIB::SRA_I16, getIntrinsicName(RTLIB::SRA_I16));
165 setLibcallName(RTLIB::SRA_I32, getIntrinsicName(RTLIB::SRA_I32));
167 // SHL library call names
168 setPIC16LibcallName(PIC16ISD::SLL_I8, getIntrinsicName(PIC16ISD::SLL_I8));
169 setLibcallName(RTLIB::SHL_I16, getIntrinsicName(RTLIB::SHL_I16));
170 setLibcallName(RTLIB::SHL_I32, getIntrinsicName(RTLIB::SHL_I32));
172 // SRL library call names
173 setPIC16LibcallName(PIC16ISD::SRL_I8, getIntrinsicName(PIC16ISD::SRL_I8));
174 setLibcallName(RTLIB::SRL_I16, getIntrinsicName(RTLIB::SRL_I16));
175 setLibcallName(RTLIB::SRL_I32, getIntrinsicName(RTLIB::SRL_I32));
177 // MUL Library call names
178 setPIC16LibcallName(PIC16ISD::MUL_I8, getIntrinsicName(PIC16ISD::MUL_I8));
179 setLibcallName(RTLIB::MUL_I16, getIntrinsicName(RTLIB::MUL_I16));
180 setLibcallName(RTLIB::MUL_I32, getIntrinsicName(RTLIB::MUL_I32));
182 // Signed division lib call names
183 setLibcallName(RTLIB::SDIV_I16, getIntrinsicName(RTLIB::SDIV_I16));
184 setLibcallName(RTLIB::SDIV_I32, getIntrinsicName(RTLIB::SDIV_I32));
186 // Unsigned division lib call names
187 setLibcallName(RTLIB::UDIV_I16, getIntrinsicName(RTLIB::UDIV_I16));
188 setLibcallName(RTLIB::UDIV_I32, getIntrinsicName(RTLIB::UDIV_I32));
190 // Signed remainder lib call names
191 setLibcallName(RTLIB::SREM_I16, getIntrinsicName(RTLIB::SREM_I16));
192 setLibcallName(RTLIB::SREM_I32, getIntrinsicName(RTLIB::SREM_I32));
194 // Unsigned remainder lib call names
195 setLibcallName(RTLIB::UREM_I16, getIntrinsicName(RTLIB::UREM_I16));
196 setLibcallName(RTLIB::UREM_I32, getIntrinsicName(RTLIB::UREM_I32));
198 // Floating point to signed int conversions.
199 setLibcallName(RTLIB::FPTOSINT_F32_I8,
200 getIntrinsicName(RTLIB::FPTOSINT_F32_I8));
201 setLibcallName(RTLIB::FPTOSINT_F32_I16,
202 getIntrinsicName(RTLIB::FPTOSINT_F32_I16));
203 setLibcallName(RTLIB::FPTOSINT_F32_I32,
204 getIntrinsicName(RTLIB::FPTOSINT_F32_I32));
206 // Signed int to floats.
207 setLibcallName(RTLIB::SINTTOFP_I32_F32,
208 getIntrinsicName(RTLIB::SINTTOFP_I32_F32));
210 // Floating points to unsigned ints.
211 setLibcallName(RTLIB::FPTOUINT_F32_I8,
212 getIntrinsicName(RTLIB::FPTOUINT_F32_I8));
213 setLibcallName(RTLIB::FPTOUINT_F32_I16,
214 getIntrinsicName(RTLIB::FPTOUINT_F32_I16));
215 setLibcallName(RTLIB::FPTOUINT_F32_I32,
216 getIntrinsicName(RTLIB::FPTOUINT_F32_I32));
218 // Unsigned int to floats.
219 setLibcallName(RTLIB::UINTTOFP_I32_F32,
220 getIntrinsicName(RTLIB::UINTTOFP_I32_F32));
222 // Floating point add, sub, mul ,div.
223 setLibcallName(RTLIB::ADD_F32, getIntrinsicName(RTLIB::ADD_F32));
224 setLibcallName(RTLIB::SUB_F32, getIntrinsicName(RTLIB::SUB_F32));
225 setLibcallName(RTLIB::MUL_F32, getIntrinsicName(RTLIB::MUL_F32));
226 setLibcallName(RTLIB::DIV_F32, getIntrinsicName(RTLIB::DIV_F32));
228 // Floationg point comparison
229 setLibcallName(RTLIB::UO_F32, getIntrinsicName(RTLIB::UO_F32));
230 setLibcallName(RTLIB::OLE_F32, getIntrinsicName(RTLIB::OLE_F32));
231 setLibcallName(RTLIB::OGE_F32, getIntrinsicName(RTLIB::OGE_F32));
232 setLibcallName(RTLIB::OLT_F32, getIntrinsicName(RTLIB::OLT_F32));
233 setLibcallName(RTLIB::OGT_F32, getIntrinsicName(RTLIB::OGT_F32));
234 setLibcallName(RTLIB::OEQ_F32, getIntrinsicName(RTLIB::OEQ_F32));
235 setLibcallName(RTLIB::UNE_F32, getIntrinsicName(RTLIB::UNE_F32));
237 // Return value comparisons of floating point calls.
238 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
239 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
240 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
241 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
242 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
243 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
244 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
245 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
247 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
248 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
250 setOperationAction(ISD::LOAD, MVT::i8, Legal);
251 setOperationAction(ISD::LOAD, MVT::i16, Custom);
252 setOperationAction(ISD::LOAD, MVT::i32, Custom);
254 setOperationAction(ISD::STORE, MVT::i8, Legal);
255 setOperationAction(ISD::STORE, MVT::i16, Custom);
256 setOperationAction(ISD::STORE, MVT::i32, Custom);
257 setOperationAction(ISD::STORE, MVT::i64, Custom);
259 setOperationAction(ISD::ADDE, MVT::i8, Custom);
260 setOperationAction(ISD::ADDC, MVT::i8, Custom);
261 setOperationAction(ISD::SUBE, MVT::i8, Custom);
262 setOperationAction(ISD::SUBC, MVT::i8, Custom);
263 setOperationAction(ISD::SUB, MVT::i8, Custom);
264 setOperationAction(ISD::ADD, MVT::i8, Custom);
265 setOperationAction(ISD::ADD, MVT::i16, Custom);
267 setOperationAction(ISD::OR, MVT::i8, Custom);
268 setOperationAction(ISD::AND, MVT::i8, Custom);
269 setOperationAction(ISD::XOR, MVT::i8, Custom);
271 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
273 setOperationAction(ISD::MUL, MVT::i8, Custom);
275 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
276 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
277 setOperationAction(ISD::MULHU, MVT::i8, Expand);
278 setOperationAction(ISD::MULHS, MVT::i8, Expand);
280 setOperationAction(ISD::SRA, MVT::i8, Custom);
281 setOperationAction(ISD::SHL, MVT::i8, Custom);
282 setOperationAction(ISD::SRL, MVT::i8, Custom);
284 setOperationAction(ISD::ROTL, MVT::i8, Expand);
285 setOperationAction(ISD::ROTR, MVT::i8, Expand);
287 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
289 // PIC16 does not support shift parts
290 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
291 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
292 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
295 // PIC16 does not have a SETCC, expand it to SELECT_CC.
296 setOperationAction(ISD::SETCC, MVT::i8, Expand);
297 setOperationAction(ISD::SELECT, MVT::i8, Expand);
298 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
299 setOperationAction(ISD::BRIND, MVT::Other, Expand);
301 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
302 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
304 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
305 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
307 // Now deduce the information based on the above mentioned
309 computeRegisterProperties();
312 // getOutFlag - Extract the flag result if the Op has it.
313 static SDValue getOutFlag(SDValue &Op) {
314 // Flag is the last value of the node.
315 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
317 assert (Flag.getValueType() == MVT::Flag
318 && "Node does not have an out Flag");
322 // Get the TmpOffset for FrameIndex
323 unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size) {
324 std::map<unsigned, unsigned>::iterator
325 MapIt = FiTmpOffsetMap.find(FI);
326 if (MapIt != FiTmpOffsetMap.end())
327 return MapIt->second;
329 // This FI (FrameIndex) is not yet mapped, so map it
330 FiTmpOffsetMap[FI] = TmpSize;
332 return FiTmpOffsetMap[FI];
335 // To extract chain value from the SDValue Nodes
336 // This function will help to maintain the chain extracting
337 // code at one place. In case of any change in future it will
338 // help maintain the code.
339 static SDValue getChain(SDValue &Op) {
340 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
342 // If the last value returned in Flag then the chain is
343 // second last value returned.
344 if (Chain.getValueType() == MVT::Flag)
345 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
347 // All nodes may not produce a chain. Therefore following assert
348 // verifies that the node is returning a chain only.
349 assert (Chain.getValueType() == MVT::Other
350 && "Node does not have a chain");
355 /// PopulateResults - Helper function to LowerOperation.
356 /// If a node wants to return multiple results after lowering,
357 /// it stuffs them into an array of SDValue called Results.
359 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
360 if (N.getOpcode() == ISD::MERGE_VALUES) {
361 int NumResults = N.getNumOperands();
362 for( int i = 0; i < NumResults; i++)
363 Results.push_back(N.getOperand(i));
366 Results.push_back(N);
370 PIC16TargetLowering::getSetCCResultType(EVT ValType) const {
374 /// The type legalizer framework of generating legalizer can generate libcalls
375 /// only when the operand/result types are illegal.
376 /// PIC16 needs to generate libcalls even for the legal types (i8) for some ops.
377 /// For example an arithmetic right shift. These functions are used to lower
378 /// such operations that generate libcall for legal types.
381 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
383 PIC16LibcallNames[Call] = Name;
387 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
388 return PIC16LibcallNames[Call];
392 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
393 EVT RetVT, const SDValue *Ops,
394 unsigned NumOps, bool isSigned,
395 SelectionDAG &DAG, DebugLoc dl) {
397 TargetLowering::ArgListTy Args;
398 Args.reserve(NumOps);
400 TargetLowering::ArgListEntry Entry;
401 for (unsigned i = 0; i != NumOps; ++i) {
403 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
404 Entry.isSExt = isSigned;
405 Entry.isZExt = !isSigned;
406 Args.push_back(Entry);
409 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16);
411 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
412 std::pair<SDValue,SDValue> CallInfo =
413 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
414 false, 0, CallingConv::C, false,
415 /*isReturnValueUsed=*/true,
416 Callee, Args, DAG, dl);
418 return CallInfo.first;
421 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
423 default: return NULL;
424 case PIC16ISD::Lo: return "PIC16ISD::Lo";
425 case PIC16ISD::Hi: return "PIC16ISD::Hi";
426 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
427 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
428 case PIC16ISD::MTPCLATH: return "PIC16ISD::MTPCLATH";
429 case PIC16ISD::PIC16Connect: return "PIC16ISD::PIC16Connect";
430 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
431 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
432 case PIC16ISD::PIC16LdArg: return "PIC16ISD::PIC16LdArg";
433 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
434 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
435 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
436 case PIC16ISD::BCF: return "PIC16ISD::BCF";
437 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
438 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
439 case PIC16ISD::RLF: return "PIC16ISD::RLF";
440 case PIC16ISD::RRF: return "PIC16ISD::RRF";
441 case PIC16ISD::CALL: return "PIC16ISD::CALL";
442 case PIC16ISD::CALLW: return "PIC16ISD::CALLW";
443 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
444 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
445 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
446 case PIC16ISD::RET: return "PIC16ISD::RET";
447 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
451 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
452 SmallVectorImpl<SDValue>&Results,
455 switch (N->getOpcode()) {
456 case ISD::GlobalAddress:
457 Results.push_back(ExpandGlobalAddress(N, DAG));
459 case ISD::ExternalSymbol:
460 Results.push_back(ExpandExternalSymbol(N, DAG));
463 Results.push_back(ExpandStore(N, DAG));
466 PopulateResults(ExpandLoad(N, DAG), Results);
469 // Results.push_back(ExpandAdd(N, DAG));
471 case ISD::FrameIndex:
472 Results.push_back(ExpandFrameIndex(N, DAG));
475 assert (0 && "not implemented");
480 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
482 // Currently handling FrameIndex of size MVT::i16 only
483 // One example of this scenario is when return value is written on
486 if (N->getValueType(0) != MVT::i16)
489 // Expand the FrameIndex into ExternalSymbol and a Constant node
490 // The constant will represent the frame index number
491 // Get the current function frame
492 MachineFunction &MF = DAG.getMachineFunction();
493 const Function *Func = MF.getFunction();
494 const std::string Name = Func->getName();
496 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
497 // FIXME there isn't really debug info here
498 DebugLoc dl = FR->getDebugLoc();
500 // Expand FrameIndex like GlobalAddress and ExternalSymbol
501 // Also use Offset field for lo and hi parts. The default
506 SDValue FI = SDValue(N,0);
507 LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
508 SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
509 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
510 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
511 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
515 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
516 StoreSDNode *St = cast<StoreSDNode>(N);
517 SDValue Chain = St->getChain();
518 SDValue Src = St->getValue();
519 SDValue Ptr = St->getBasePtr();
520 EVT ValueType = Src.getValueType();
521 unsigned StoreOffset = 0;
522 DebugLoc dl = N->getDebugLoc();
524 SDValue PtrLo, PtrHi;
525 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
527 if (ValueType == MVT::i8) {
528 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
530 DAG.getConstant (0 + StoreOffset, MVT::i8));
532 else if (ValueType == MVT::i16) {
533 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
534 SDValue SrcLo, SrcHi;
535 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
536 SDValue ChainLo = Chain, ChainHi = Chain;
537 // FIXME: This makes unsafe assumptions. The Chain may be a TokenFactor
538 // created for an unrelated purpose, in which case it may not have
539 // exactly two operands. Also, even if it does have two operands, they
540 // may not be the low and high parts of an aligned load that was split.
541 if (Chain.getOpcode() == ISD::TokenFactor) {
542 ChainLo = Chain.getOperand(0);
543 ChainHi = Chain.getOperand(1);
545 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
548 DAG.getConstant (0 + StoreOffset, MVT::i8));
550 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
552 DAG.getConstant (1 + StoreOffset, MVT::i8));
554 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
557 else if (ValueType == MVT::i32) {
558 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
559 SDValue SrcLo, SrcHi;
560 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
562 // Get the expanded parts of each of SrcLo and SrcHi.
563 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
564 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
565 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
567 SDValue ChainLo = Chain, ChainHi = Chain;
568 // FIXME: This makes unsafe assumptions; see the FIXME above.
569 if (Chain.getOpcode() == ISD::TokenFactor) {
570 ChainLo = Chain.getOperand(0);
571 ChainHi = Chain.getOperand(1);
573 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
575 // FIXME: This makes unsafe assumptions; see the FIXME above.
576 if (ChainLo.getOpcode() == ISD::TokenFactor) {
577 ChainLo1 = ChainLo.getOperand(0);
578 ChainLo2 = ChainLo.getOperand(1);
580 // FIXME: This makes unsafe assumptions; see the FIXME above.
581 if (ChainHi.getOpcode() == ISD::TokenFactor) {
582 ChainHi1 = ChainHi.getOperand(0);
583 ChainHi2 = ChainHi.getOperand(1);
585 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
587 SrcLo1, PtrLo, PtrHi,
588 DAG.getConstant (0 + StoreOffset, MVT::i8));
590 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
591 SrcLo2, PtrLo, PtrHi,
592 DAG.getConstant (1 + StoreOffset, MVT::i8));
594 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
595 SrcHi1, PtrLo, PtrHi,
596 DAG.getConstant (2 + StoreOffset, MVT::i8));
598 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
599 SrcHi2, PtrLo, PtrHi,
600 DAG.getConstant (3 + StoreOffset, MVT::i8));
602 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
603 getChain(Store1), getChain(Store2));
604 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
605 getChain(Store3), getChain(Store4));
606 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
608 } else if (ValueType == MVT::i64) {
609 SDValue SrcLo, SrcHi;
610 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
611 SDValue ChainLo = Chain, ChainHi = Chain;
612 // FIXME: This makes unsafe assumptions; see the FIXME above.
613 if (Chain.getOpcode() == ISD::TokenFactor) {
614 ChainLo = Chain.getOperand(0);
615 ChainHi = Chain.getOperand(1);
617 SDValue Store1 = DAG.getStore(ChainLo, dl, SrcLo, Ptr, NULL,
620 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
621 DAG.getConstant(4, Ptr.getValueType()));
622 SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, NULL,
625 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1,
628 assert (0 && "value type not supported");
633 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
635 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
636 // FIXME there isn't really debug info here
637 DebugLoc dl = ES->getDebugLoc();
639 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
640 SDValue Offset = DAG.getConstant(0, MVT::i8);
641 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset);
642 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset);
644 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
647 // ExpandGlobalAddress -
648 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
649 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
650 // FIXME there isn't really debug info here
651 DebugLoc dl = G->getDebugLoc();
653 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
656 SDValue Offset = DAG.getConstant(0, MVT::i8);
657 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset);
658 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset);
660 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
663 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
664 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
666 if (Op.getOpcode() == ISD::BUILD_PAIR) {
667 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
673 // Return true if DirectAddress is in ROM_SPACE
674 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
676 // RomAddress is a GlobalAddress in ROM_SPACE_
677 // If the Op is not a GlobalAddress return NULL without checking
679 if (!isDirectAddress(Op))
682 // Its a GlobalAddress.
683 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
684 SDValue TGA = Op.getOperand(0).getOperand(0);
685 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
687 if (GSDN->getAddressSpace() == PIC16ISD::ROM_SPACE)
690 // Any other address space return it false
695 // GetExpandedParts - This function is on the similiar lines as
696 // the GetExpandedInteger in type legalizer is. This returns expanded
697 // parts of Op in Lo and Hi.
699 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
700 SDValue &Lo, SDValue &Hi) {
701 SDNode *N = Op.getNode();
702 DebugLoc dl = N->getDebugLoc();
703 EVT NewVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
705 // Extract the lo component.
706 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
707 DAG.getConstant(0, MVT::i8));
709 // extract the hi component
710 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
711 DAG.getConstant(1, MVT::i8));
714 // Legalize FrameIndex into ExternalSymbol and offset.
716 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
717 SDValue &ES, int &Offset) {
719 MachineFunction &MF = DAG.getMachineFunction();
720 const Function *Func = MF.getFunction();
721 MachineFrameInfo *MFI = MF.getFrameInfo();
722 const std::string Name = Func->getName();
724 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
726 // FrameIndices are not stack offsets. But they represent the request
727 // for space on stack. That space requested may be more than one byte.
728 // Therefore, to calculate the stack offset that a FrameIndex aligns
729 // with, we need to traverse all the FrameIndices available earlier in
730 // the list and add their requested size.
731 unsigned FIndex = FR->getIndex();
733 if (FIndex < ReservedFrameCount) {
734 tmpName = createESName(PAN::getFrameLabel(Name));
735 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
737 for (unsigned i=0; i<FIndex ; ++i) {
738 Offset += MFI->getObjectSize(i);
741 // FrameIndex has been made for some temporary storage
742 tmpName = createESName(PAN::getTempdataLabel(Name));
743 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
744 Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex));
750 // This function legalizes the PIC16 Addresses. If the Pointer is
751 // -- Direct address variable residing
752 // --> then a Banksel for that variable will be created.
754 // --> then it will be treated as an indirect address.
755 // -- Indirect address
756 // --> then the address will be loaded into FSR
757 // -- ADD with constant operand
758 // --> then constant operand of ADD will be returned as Offset
759 // and non-constant operand of ADD will be treated as pointer.
760 // Returns the high and lo part of the address, and the offset(in case of ADD).
762 void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
763 SDValue &Lo, SDValue &Hi,
764 unsigned &Offset, DebugLoc dl) {
766 // Offset, by default, should be 0
769 // If the pointer is ADD with constant,
770 // return the constant value as the offset
771 if (Ptr.getOpcode() == ISD::ADD) {
772 SDValue OperLeft = Ptr.getOperand(0);
773 SDValue OperRight = Ptr.getOperand(1);
774 if ((OperLeft.getOpcode() == ISD::Constant) &&
775 (dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue() < 32 )) {
776 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
778 } else if ((OperRight.getOpcode() == ISD::Constant) &&
779 (dyn_cast<ConstantSDNode>(OperRight)->getZExtValue() < 32 )){
780 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
785 // If the pointer is Type i8 and an external symbol
786 // then treat it as direct address.
787 // One example for such case is storing and loading
788 // from function frame during a call
789 if (Ptr.getValueType() == MVT::i8) {
790 switch (Ptr.getOpcode()) {
791 case ISD::TargetExternalSymbol:
793 Hi = DAG.getConstant(1, MVT::i8);
798 // Expansion of FrameIndex has Lo/Hi parts
799 if (isDirectAddress(Ptr)) {
800 SDValue TFI = Ptr.getOperand(0).getOperand(0);
802 if (TFI.getOpcode() == ISD::TargetFrameIndex) {
803 LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
804 Hi = DAG.getConstant(1, MVT::i8);
805 Offset += FrameOffset;
807 } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
808 // FrameIndex has already been expanded.
809 // Now just make use of its expansion
811 Hi = DAG.getConstant(1, MVT::i8);
812 SDValue FOffset = Ptr.getOperand(0).getOperand(1);
813 assert (FOffset.getOpcode() == ISD::Constant &&
814 "Invalid operand of PIC16ISD::Lo");
815 Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
820 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
821 // Direct addressing case for RAM variables. The Hi part is constant
822 // and the Lo part is the TGA itself.
823 Lo = Ptr.getOperand(0).getOperand(0);
825 // For direct addresses Hi is a constant. Value 1 for the constant
826 // signifies that banksel needs to generated for it. Value 0 for
827 // the constant signifies that banksel does not need to be generated
828 // for it. Mark it as 1 now and optimize later.
829 Hi = DAG.getConstant(1, MVT::i8);
833 // Indirect addresses. Get the hi and lo parts of ptr.
834 GetExpandedParts(Ptr, DAG, Lo, Hi);
836 // Put the hi and lo parts into FSR.
837 Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
838 Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
843 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
844 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
845 SDValue Chain = LD->getChain();
846 SDValue Ptr = LD->getBasePtr();
847 DebugLoc dl = LD->getDebugLoc();
849 SDValue Load, Offset;
852 SDValue PtrLo, PtrHi;
855 // Legalize direct/indirect addresses. This will give the lo and hi parts
856 // of the address and the offset.
857 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
859 // Load from the pointer (direct address or FSR)
860 VT = N->getValueType(0);
861 unsigned NumLoads = VT.getSizeInBits() / 8;
862 std::vector<SDValue> PICLoads;
864 EVT MemVT = LD->getMemoryVT();
865 if(ISD::isNON_EXTLoad(N)) {
866 for (iter=0; iter<NumLoads ; ++iter) {
867 // Add the pointer offset if any
868 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
869 Tys = DAG.getVTList(MVT::i8, MVT::Other);
870 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
872 PICLoads.push_back(Load);
875 // If it is extended load then use PIC16Load for Memory Bytes
876 // and for all extended bytes perform action based on type of
877 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
880 // For extended loads this is the memory value type
881 // i.e. without any extension
882 EVT MemVT = LD->getMemoryVT();
883 unsigned MemBytes = MemVT.getSizeInBits() / 8;
884 // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero
886 if (MemBytes == 0) MemBytes = 1;
888 unsigned ExtdBytes = VT.getSizeInBits() / 8;
889 Offset = DAG.getConstant(LoadOffset, MVT::i8);
891 Tys = DAG.getVTList(MVT::i8, MVT::Other);
892 // For MemBytes generate PIC16Load with proper offset
893 for (iter=0; iter < MemBytes; ++iter) {
894 // Add the pointer offset if any
895 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
896 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
898 PICLoads.push_back(Load);
901 // For SignExtendedLoad
902 if (ISD::isSEXTLoad(N)) {
903 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
905 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
906 DAG.getConstant(7, MVT::i8));
907 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
908 PICLoads.push_back(SRA);
910 } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
911 //} else if (ISD::isZEXTLoad(N)) {
912 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
913 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
914 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
915 PICLoads.push_back(ConstZero);
922 // Operand of Load is illegal -- Load itself is legal
925 else if (VT == MVT::i16) {
926 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
927 if (MemVT == MVT::i8)
928 Chain = getChain(PICLoads[0]);
930 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
931 getChain(PICLoads[0]), getChain(PICLoads[1]));
932 } else if (VT == MVT::i32) {
934 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
935 PICLoads[0], PICLoads[1]);
936 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
937 PICLoads[2], PICLoads[3]);
938 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
939 if (MemVT == MVT::i8)
940 Chain = getChain(PICLoads[0]);
941 else if (MemVT == MVT::i16)
942 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
943 getChain(PICLoads[0]), getChain(PICLoads[1]));
946 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
947 getChain(PICLoads[0]), getChain(PICLoads[1]));
948 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
949 getChain(PICLoads[2]), getChain(PICLoads[3]));
950 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
951 Chains[0], Chains[1]);
954 Tys = DAG.getVTList(VT, MVT::Other);
955 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
958 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
959 // We should have handled larger operands in type legalizer itself.
960 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
962 SDNode *N = Op.getNode();
963 SDValue Value = N->getOperand(0);
964 SDValue Amt = N->getOperand(1);
965 PIC16ISD::PIC16Libcall CallCode;
966 switch (N->getOpcode()) {
968 CallCode = PIC16ISD::SRA_I8;
971 CallCode = PIC16ISD::SLL_I8;
974 CallCode = PIC16ISD::SRL_I8;
977 assert ( 0 && "This shift is not implemented yet.");
980 SmallVector<SDValue, 2> Ops(2);
983 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
984 true, DAG, N->getDebugLoc());
988 SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
989 // We should have handled larger operands in type legalizer itself.
990 assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
992 SDNode *N = Op.getNode();
993 SmallVector<SDValue, 2> Ops(2);
994 Ops[0] = N->getOperand(0);
995 Ops[1] = N->getOperand(1);
996 SDValue Call = MakePIC16Libcall(PIC16ISD::MUL_I8, N->getValueType(0),
997 &Ops[0], 2, true, DAG, N->getDebugLoc());
1002 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
1003 SmallVectorImpl<SDValue>&Results,
1004 SelectionDAG &DAG) {
1005 SDValue Op = SDValue(N, 0);
1008 switch (Op.getOpcode()) {
1010 Res = ExpandLoad(Op.getNode(), DAG); break;
1012 // All other operations are handled in LowerOperation.
1013 Res = LowerOperation(Op, DAG);
1015 Results.push_back(Res);
1022 unsigned NumValues = N->getNumValues();
1023 for (i = 0; i < NumValues ; i++) {
1024 Results.push_back(SDValue(N, i));
1028 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1029 switch (Op.getOpcode()) {
1033 return LowerADD(Op, DAG);
1037 return LowerSUB(Op, DAG);
1039 return ExpandLoad(Op.getNode(), DAG);
1041 return ExpandStore(Op.getNode(), DAG);
1043 return LowerMUL(Op, DAG);
1047 return LowerShift(Op, DAG);
1051 return LowerBinOp(Op, DAG);
1053 return LowerBR_CC(Op, DAG);
1054 case ISD::SELECT_CC:
1055 return LowerSELECT_CC(Op, DAG);
1060 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
1063 assert (Op.getValueType() == MVT::i8
1064 && "illegal value type to store on stack.");
1066 MachineFunction &MF = DAG.getMachineFunction();
1067 const Function *Func = MF.getFunction();
1068 const std::string FuncName = Func->getName();
1071 // Put the value on stack.
1072 // Get a stack slot index and convert to es.
1073 int FI = MF.getFrameInfo()->CreateStackObject(1, 1, false);
1074 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
1075 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1077 // Store the value to ES.
1078 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
1081 DAG.getConstant (1, MVT::i8), // Banksel.
1082 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1085 // Load the value from ES.
1086 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
1087 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
1088 ES, DAG.getConstant (1, MVT::i8),
1089 DAG.getConstant (GetTmpOffsetForFI(FI, 1),
1092 return Load.getValue(0);
1095 SDValue PIC16TargetLowering::
1096 LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
1097 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1098 const SmallVectorImpl<ISD::OutputArg> &Outs,
1099 const SmallVectorImpl<ISD::InputArg> &Ins,
1100 DebugLoc dl, SelectionDAG &DAG) {
1101 unsigned NumOps = Outs.size();
1103 // If call has no arguments then do nothing and return.
1107 std::vector<SDValue> Ops;
1108 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1109 SDValue Arg, StoreRet;
1111 // For PIC16 ABI the arguments come after the return value.
1112 unsigned RetVals = Ins.size();
1113 for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
1114 // Get the arguments
1118 Ops.push_back(Chain);
1120 Ops.push_back(DataAddr_Lo);
1121 Ops.push_back(DataAddr_Hi);
1122 Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8));
1123 Ops.push_back(InFlag);
1125 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1127 Chain = getChain(StoreRet);
1128 InFlag = getOutFlag(StoreRet);
1134 SDValue PIC16TargetLowering::
1135 LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
1136 const SmallVectorImpl<ISD::OutputArg> &Outs,
1137 DebugLoc dl, SelectionDAG &DAG) {
1138 unsigned NumOps = Outs.size();
1140 SDValue Arg, StoreAt;
1144 // If call has no arguments then do nothing and return.
1148 // FIXME: This portion of code currently assumes only
1149 // primitive types being passed as arguments.
1151 // Legalize the address before use
1152 SDValue PtrLo, PtrHi;
1153 unsigned AddressOffset;
1154 int StoreOffset = 0;
1155 LegalizeAddress(ArgLabel, DAG, PtrLo, PtrHi, AddressOffset, dl);
1158 std::vector<SDValue> Ops;
1159 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1160 for (unsigned i=0, Offset = 0; i<NumOps; i++) {
1163 StoreOffset = (Offset + AddressOffset);
1165 // Store the argument on frame
1168 Ops.push_back(Chain);
1170 Ops.push_back(PtrLo);
1171 Ops.push_back(PtrHi);
1172 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
1173 Ops.push_back(InFlag);
1175 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
1177 Chain = getChain(StoreRet);
1178 InFlag = getOutFlag(StoreRet);
1180 // Update the frame offset to be used for next argument
1181 ArgVT = Arg.getValueType();
1182 Size = ArgVT.getSizeInBits();
1183 Size = Size/8; // Calculate size in bytes
1184 Offset += Size; // Increase the frame offset
1189 SDValue PIC16TargetLowering::
1190 LowerIndirectCallReturn(SDValue Chain, SDValue InFlag,
1191 SDValue DataAddr_Lo, SDValue DataAddr_Hi,
1192 const SmallVectorImpl<ISD::InputArg> &Ins,
1193 DebugLoc dl, SelectionDAG &DAG,
1194 SmallVectorImpl<SDValue> &InVals) {
1195 unsigned RetVals = Ins.size();
1197 // If call does not have anything to return
1198 // then do nothing and go back.
1202 // Call has something to return
1205 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1206 for(unsigned i=0;i<RetVals;i++) {
1207 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo,
1208 DataAddr_Hi, DAG.getConstant(i, MVT::i8),
1210 InFlag = getOutFlag(LoadRet);
1211 Chain = getChain(LoadRet);
1212 InVals.push_back(LoadRet);
1217 SDValue PIC16TargetLowering::
1218 LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag,
1219 const SmallVectorImpl<ISD::InputArg> &Ins,
1220 DebugLoc dl, SelectionDAG &DAG,
1221 SmallVectorImpl<SDValue> &InVals) {
1223 // Currently handling primitive types only. They will come in
1225 unsigned RetVals = Ins.size();
1227 // Return immediately if the return type is void
1231 // Call has something to return
1233 // Legalize the address before use
1236 LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl);
1238 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1241 for(unsigned i=0, Offset=0;i<RetVals;i++) {
1243 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
1244 DAG.getConstant(LdOffset + Offset, MVT::i8),
1247 InFlag = getOutFlag(LoadRet);
1249 Chain = getChain(LoadRet);
1251 InVals.push_back(LoadRet);
1258 PIC16TargetLowering::LowerReturn(SDValue Chain,
1259 CallingConv::ID CallConv, bool isVarArg,
1260 const SmallVectorImpl<ISD::OutputArg> &Outs,
1261 DebugLoc dl, SelectionDAG &DAG) {
1263 // Number of values to return
1264 unsigned NumRet = Outs.size();
1266 // Function returns value always on stack with the offset starting
1268 MachineFunction &MF = DAG.getMachineFunction();
1269 const Function *F = MF.getFunction();
1270 std::string FuncName = F->getName();
1272 const char *tmpName = createESName(PAN::getFrameLabel(FuncName));
1273 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1274 SDValue BS = DAG.getConstant(1, MVT::i8);
1276 for(unsigned i=0;i<NumRet; ++i) {
1277 RetVal = Outs[i].Val;
1278 Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
1280 DAG.getConstant (i, MVT::i8));
1283 return DAG.getNode(PIC16ISD::RET, dl, MVT::Other, Chain);
1286 void PIC16TargetLowering::
1287 GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
1288 SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
1289 SelectionDAG &DAG) {
1290 assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
1291 && "Don't know what to do of such callee!!");
1292 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1293 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1294 Chain = getChain(SeqStart);
1295 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1297 // Get the Lo and Hi part of code address
1298 SDValue Lo = Callee.getOperand(0);
1299 SDValue Hi = Callee.getOperand(1);
1301 SDValue Data_Lo, Data_Hi;
1302 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
1303 // Subtract 2 from Address to get the Lower part of DataAddress.
1304 SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag);
1305 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1306 DAG.getConstant(2, MVT::i8));
1307 SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1308 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3);
1309 SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1310 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1311 SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee,
1313 Chain = getChain(Call);
1314 OperFlag = getOutFlag(Call);
1315 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1317 Chain = getChain(SeqEnd);
1318 OperFlag = getOutFlag(SeqEnd);
1320 // Low part of Data Address
1321 DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag);
1323 // Make the second call.
1324 SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1325 Chain = getChain(SeqStart);
1326 OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1328 // Subtract 1 from Address to get high part of data address.
1329 Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo,
1330 DAG.getConstant(1, MVT::i8));
1331 SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)};
1332 Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1333 PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi);
1335 // Use new Lo to make another CALLW
1336 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH);
1337 Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag);
1338 Chain = getChain(Call);
1339 OperFlag = getOutFlag(Call);
1340 SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1342 Chain = getChain(SeqEnd);
1343 OperFlag = getOutFlag(SeqEnd);
1344 // Hi part of Data Address
1345 DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag);
1349 PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1350 CallingConv::ID CallConv, bool isVarArg,
1352 const SmallVectorImpl<ISD::OutputArg> &Outs,
1353 const SmallVectorImpl<ISD::InputArg> &Ins,
1354 DebugLoc dl, SelectionDAG &DAG,
1355 SmallVectorImpl<SDValue> &InVals) {
1357 assert(Callee.getValueType() == MVT::i16 &&
1358 "Don't know how to legalize this call node!!!");
1360 // The flag to track if this is a direct or indirect call.
1361 bool IsDirectCall = true;
1362 unsigned RetVals = Ins.size();
1363 unsigned NumArgs = Outs.size();
1365 SDValue DataAddr_Lo, DataAddr_Hi;
1366 if (!isa<GlobalAddressSDNode>(Callee) &&
1367 !isa<ExternalSymbolSDNode>(Callee)) {
1368 IsDirectCall = false; // This is indirect call
1370 // If this is an indirect call then to pass the arguments
1371 // and read the return value back, we need the data address
1372 // of the function being called.
1373 // To get the data address two more calls need to be made.
1375 // Come here for indirect calls
1377 // Indirect addresses. Get the hi and lo parts of ptr.
1378 GetExpandedParts(Callee, DAG, Lo, Hi);
1379 // Connect Lo and Hi parts of the callee with the PIC16Connect
1380 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi);
1382 // Read DataAddress only if we have to pass arguments or
1383 // read return value.
1384 if ((RetVals > 0) || (NumArgs > 0))
1385 GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG);
1388 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1390 // Start the call sequence.
1391 // Carring the Constant 0 along the CALLSEQSTART
1392 // because there is nothing else to carry.
1393 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1394 Chain = getChain(SeqStart);
1395 SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency
1398 // For any direct call - callee will be GlobalAddressNode or
1400 SDValue ArgLabel, RetLabel;
1402 // Considering the GlobalAddressNode case here.
1403 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1404 GlobalValue *GV = G->getGlobal();
1405 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1406 Name = G->getGlobal()->getName();
1407 } else {// Considering the ExternalSymbol case here
1408 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
1409 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1410 Name = ES->getSymbol();
1413 // Label for argument passing
1414 const char *argFrame = createESName(PAN::getArgsLabel(Name));
1415 ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1417 // Label for reading return value
1418 const char *retName = createESName(PAN::getRetvalLabel(Name));
1419 RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1422 SDValue CodeAddr_Lo = Callee.getOperand(0);
1423 SDValue CodeAddr_Hi = Callee.getOperand(1);
1425 /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo,
1426 DAG.getConstant(2, MVT::i8));*/
1428 // move Hi part in PCLATH
1429 CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi);
1430 Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo,
1434 // Pass the argument to function before making the call.
1437 CallArgs = LowerDirectCallArguments(ArgLabel, Chain, OperFlag,
1439 Chain = getChain(CallArgs);
1440 OperFlag = getOutFlag(CallArgs);
1442 CallArgs = LowerIndirectCallArguments(Chain, OperFlag, DataAddr_Lo,
1443 DataAddr_Hi, Outs, Ins, dl, DAG);
1444 Chain = getChain(CallArgs);
1445 OperFlag = getOutFlag(CallArgs);
1448 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1449 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1451 Chain = getChain(PICCall);
1452 OperFlag = getOutFlag(PICCall);
1455 // Carrying the Constant 0 along the CALLSEQSTART
1456 // because there is nothing else to carry.
1457 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1459 Chain = getChain(SeqEnd);
1460 OperFlag = getOutFlag(SeqEnd);
1462 // Lower the return value reading after the call.
1464 return LowerDirectCallReturn(RetLabel, Chain, OperFlag,
1465 Ins, dl, DAG, InVals);
1467 return LowerIndirectCallReturn(Chain, OperFlag, DataAddr_Lo,
1468 DataAddr_Hi, Ins, dl, DAG, InVals);
1471 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1472 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1473 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1474 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1479 // NeedToConvertToMemOp - Returns true if one of the operands of the
1480 // operation 'Op' needs to be put into memory. Also returns the
1481 // operand no. of the operand to be converted in 'MemOp'. Remember, PIC16 has
1482 // no instruction that can operation on two registers. Most insns take
1483 // one register and one memory operand (addwf) / Constant (addlw).
1484 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1485 // If one of the operand is a constant, return false.
1486 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1487 Op.getOperand(1).getOpcode() == ISD::Constant)
1490 // Return false if one of the operands is already a direct
1491 // load and that operand has only one use.
1492 if (isDirectLoad(Op.getOperand(0))) {
1493 if (Op.getOperand(0).hasOneUse())
1498 if (isDirectLoad(Op.getOperand(1))) {
1499 if (Op.getOperand(1).hasOneUse())
1507 // LowerBinOp - Lower a commutative binary operation that does not
1508 // affect status flag carry.
1509 SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1510 DebugLoc dl = Op.getDebugLoc();
1512 // We should have handled larger operands in type legalizer itself.
1513 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1516 if (NeedToConvertToMemOp(Op, MemOp)) {
1517 // Put one value on stack.
1518 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1520 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1528 // LowerADD - Lower all types of ADD operations including the ones
1529 // that affects carry.
1530 SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
1531 // We should have handled larger operands in type legalizer itself.
1532 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1533 DebugLoc dl = Op.getDebugLoc();
1535 if (NeedToConvertToMemOp(Op, MemOp)) {
1536 // Put one value on stack.
1537 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1539 // ADDC and ADDE produce two results.
1540 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1542 // ADDE has three operands, the last one is the carry bit.
1543 if (Op.getOpcode() == ISD::ADDE)
1544 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1545 NewVal, Op.getOperand(2));
1546 // ADDC has two operands.
1547 else if (Op.getOpcode() == ISD::ADDC)
1548 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1550 // ADD it is. It produces only one result.
1552 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1559 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1560 DebugLoc dl = Op.getDebugLoc();
1561 // We should have handled larger operands in type legalizer itself.
1562 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1564 // Nothing to do if the first operand is already a direct load and it has
1566 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1569 // Put first operand on stack.
1570 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1572 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1573 switch (Op.getOpcode()) {
1575 assert (0 && "Opcode unknown.");
1577 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1581 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1584 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1));
1589 void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
1590 unsigned NumArgs = F->arg_size();
1592 bool isVoidFunc = (F->getReturnType()->getTypeID() == Type::VoidTyID);
1595 ReservedFrameCount = NumArgs;
1597 ReservedFrameCount = NumArgs + 1;
1600 // LowerFormalArguments - Argument values are loaded from the
1601 // <fname>.args + offset. All arguments are already broken to leaglized
1602 // types, so the offset just runs from 0 to NumArgVals - 1.
1605 PIC16TargetLowering::LowerFormalArguments(SDValue Chain,
1606 CallingConv::ID CallConv,
1608 const SmallVectorImpl<ISD::InputArg> &Ins,
1611 SmallVectorImpl<SDValue> &InVals) {
1612 unsigned NumArgVals = Ins.size();
1614 // Get the callee's name to create the <fname>.args label to pass args.
1615 MachineFunction &MF = DAG.getMachineFunction();
1616 const Function *F = MF.getFunction();
1617 std::string FuncName = F->getName();
1619 // Reset the map of FI and TmpOffset
1620 ResetTmpOffsetMap();
1621 // Initialize the ReserveFrameCount
1622 InitReservedFrameCount(F);
1624 // Create the <fname>.args external symbol.
1625 const char *tmpName = createESName(PAN::getArgsLabel(FuncName));
1626 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
1628 // Load arg values from the label + offset.
1629 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other);
1630 SDValue BS = DAG.getConstant(1, MVT::i8);
1631 for (unsigned i = 0; i < NumArgVals ; ++i) {
1632 SDValue Offset = DAG.getConstant(i, MVT::i8);
1633 SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS,
1635 Chain = getChain(PICLoad);
1636 InVals.push_back(PICLoad);
1642 // Perform DAGCombine of PIC16Load.
1643 // FIXME - Need a more elaborate comment here.
1644 SDValue PIC16TargetLowering::
1645 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1646 SelectionDAG &DAG = DCI.DAG;
1647 SDValue Chain = N->getOperand(0);
1648 if (N->hasNUsesOfValue(0, 0)) {
1649 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1654 // For all the functions with arguments some STORE nodes are generated
1655 // that store the argument on the frameindex. However in PIC16 the arguments
1656 // are passed on stack only. Therefore these STORE nodes are redundant.
1657 // To remove these STORE nodes will be removed in PerformStoreCombine
1659 // Currently this function is doint nothing and will be updated for removing
1660 // unwanted store operations
1661 SDValue PIC16TargetLowering::
1662 PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1663 return SDValue(N, 0);
1665 // Storing an undef value is of no use, so remove it
1666 if (isStoringUndef(N, Chain, DAG)) {
1667 return Chain; // remove the store and return the chain
1669 //else everything is ok.
1670 return SDValue(N, 0);
1674 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1675 DAGCombinerInfo &DCI) const {
1676 switch (N->getOpcode()) {
1678 return PerformStoreCombine(N, DCI);
1679 case PIC16ISD::PIC16Load:
1680 return PerformPIC16LoadCombine(N, DCI);
1685 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1687 default: llvm_unreachable("Unknown condition code!");
1688 case ISD::SETNE: return PIC16CC::NE;
1689 case ISD::SETEQ: return PIC16CC::EQ;
1690 case ISD::SETGT: return PIC16CC::GT;
1691 case ISD::SETGE: return PIC16CC::GE;
1692 case ISD::SETLT: return PIC16CC::LT;
1693 case ISD::SETLE: return PIC16CC::LE;
1694 case ISD::SETULT: return PIC16CC::ULT;
1695 case ISD::SETULE: return PIC16CC::ULE;
1696 case ISD::SETUGE: return PIC16CC::UGE;
1697 case ISD::SETUGT: return PIC16CC::UGT;
1701 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1702 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1703 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1704 ISD::CondCode CC, unsigned &SPCC) {
1705 if (isa<ConstantSDNode>(RHS) &&
1706 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1708 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1709 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1710 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1711 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1712 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1713 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1714 SDValue CMPCC = LHS.getOperand(3);
1715 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1716 LHS = CMPCC.getOperand(0);
1717 RHS = CMPCC.getOperand(1);
1721 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1722 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1723 unsigned CC, SDValue &PIC16CC,
1724 SelectionDAG &DAG, DebugLoc dl) {
1725 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1727 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1728 // i.e. a < 12 can be rewritten as 12 > a.
1729 if (RHS.getOpcode() == ISD::Constant) {
1738 CondCode = PIC16CC::GT;
1741 CondCode = PIC16CC::LT;
1744 CondCode = PIC16CC::UGT;
1747 CondCode = PIC16CC::ULT;
1750 CondCode = PIC16CC::LE;
1753 CondCode = PIC16CC::GE;
1756 CondCode = PIC16CC::UGE;
1759 CondCode = PIC16CC::ULE;
1764 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1766 // These are signed comparisons.
1767 SDValue Mask = DAG.getConstant(128, MVT::i8);
1768 if (isSignedComparison(CondCode)) {
1769 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1770 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1773 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1774 // We can use a subtract operation to set the condition codes. But
1775 // we need to put one operand in memory if required.
1776 // Nothing to do if the first operand is already a valid type (direct load
1777 // for subwf and literal for sublw) and it is used by this operation only.
1778 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1780 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1782 // else convert the first operand to mem.
1783 LHS = ConvertToMemOperand (LHS, DAG, dl);
1784 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1788 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1789 SDValue LHS = Op.getOperand(0);
1790 SDValue RHS = Op.getOperand(1);
1791 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1792 SDValue TrueVal = Op.getOperand(2);
1793 SDValue FalseVal = Op.getOperand(3);
1794 unsigned ORIGCC = ~0;
1795 DebugLoc dl = Op.getDebugLoc();
1797 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1798 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1800 // A setcc: lhs, rhs, cc is expanded by llvm to
1801 // select_cc: result of setcc, 0, 1, 0, setne
1802 // We can think of it as:
1803 // select_cc: lhs, rhs, 1, 0, cc
1804 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1805 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1808 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1810 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1811 FalseVal, PIC16CC, Cmp.getValue(1));
1815 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1816 MachineBasicBlock *BB,
1817 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1818 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1819 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1820 DebugLoc dl = MI->getDebugLoc();
1822 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1823 // control-flow pattern. The incoming instruction knows the destination vreg
1824 // to set, the condition code register to branch on, the true/false values to
1825 // select between, and a branch opcode to use.
1826 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1827 MachineFunction::iterator It = BB;
1834 // fallthrough --> copy0MBB
1835 MachineBasicBlock *thisMBB = BB;
1836 MachineFunction *F = BB->getParent();
1837 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1838 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1839 BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1840 F->insert(It, copy0MBB);
1841 F->insert(It, sinkMBB);
1843 // Update machine-CFG edges by first adding all successors of the current
1844 // block to the new block which will contain the Phi node for the select.
1845 // Also inform sdisel of the edge changes.
1846 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
1847 E = BB->succ_end(); I != E; ++I) {
1848 EM->insert(std::make_pair(*I, sinkMBB));
1849 sinkMBB->addSuccessor(*I);
1851 // Next, remove all successors of the current block, and add the true
1852 // and fallthrough blocks as its successors.
1853 while (!BB->succ_empty())
1854 BB->removeSuccessor(BB->succ_begin());
1855 // Next, add the true and fallthrough blocks as its successors.
1856 BB->addSuccessor(copy0MBB);
1857 BB->addSuccessor(sinkMBB);
1860 // %FalseValue = ...
1861 // # fallthrough to sinkMBB
1864 // Update machine-CFG edges
1865 BB->addSuccessor(sinkMBB);
1868 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1871 BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1872 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1873 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1875 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1880 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1881 SDValue Chain = Op.getOperand(0);
1882 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1883 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1884 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1885 SDValue Dest = Op.getOperand(4); // BB to jump to
1886 unsigned ORIGCC = ~0;
1887 DebugLoc dl = Op.getDebugLoc();
1889 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1890 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1891 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1892 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1894 // Get the Compare insn and condition code.
1896 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1898 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,