2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PIC16 uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pic16-lower"
16 #include "PIC16ISelLowering.h"
17 #include "PIC16TargetMachine.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/GlobalValue.h"
20 #include "llvm/Function.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 // PIC16TargetLowering Constructor.
33 PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
34 : TargetLowering(TM) {
36 Subtarget = &TM.getSubtarget<PIC16Subtarget>();
38 addRegisterClass(MVT::i8, PIC16::GPRRegisterClass);
40 setShiftAmountType(MVT::i8);
41 setShiftAmountFlavor(Extend);
43 // SRA library call names
44 setPIC16LibcallName(PIC16ISD::SRA_I8, "__intrinsics.sra.i8");
45 setLibcallName(RTLIB::SRA_I16, "__intrinsics.sra.i16");
46 setLibcallName(RTLIB::SRA_I32, "__intrinsics.sra.i32");
48 // SHL library call names
49 setPIC16LibcallName(PIC16ISD::SLL_I8, "__intrinsics.sll.i8");
50 setLibcallName(RTLIB::SHL_I16, "__intrinsics.sll.i16");
51 setLibcallName(RTLIB::SHL_I32, "__intrinsics.sll.i32");
53 // SRL library call names
54 setPIC16LibcallName(PIC16ISD::SRL_I8, "__intrinsics.srl.i8");
55 setLibcallName(RTLIB::SRL_I16, "__intrinsics.srl.i16");
56 setLibcallName(RTLIB::SRL_I32, "__intrinsics.srl.i32");
58 // MUL Library call names
59 setPIC16LibcallName(PIC16ISD::MUL_I8, "__intrinsics.mul.i8");
60 setLibcallName(RTLIB::MUL_I16, "__intrinsics.mul.i16");
61 setLibcallName(RTLIB::MUL_I32, "__intrinsics.mul.i32");
63 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
64 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
66 setOperationAction(ISD::LOAD, MVT::i8, Legal);
67 setOperationAction(ISD::LOAD, MVT::i16, Custom);
68 setOperationAction(ISD::LOAD, MVT::i32, Custom);
70 setOperationAction(ISD::STORE, MVT::i8, Legal);
71 setOperationAction(ISD::STORE, MVT::i16, Custom);
72 setOperationAction(ISD::STORE, MVT::i32, Custom);
74 setOperationAction(ISD::ADDE, MVT::i8, Custom);
75 setOperationAction(ISD::ADDC, MVT::i8, Custom);
76 setOperationAction(ISD::SUBE, MVT::i8, Custom);
77 setOperationAction(ISD::SUBC, MVT::i8, Custom);
78 setOperationAction(ISD::ADD, MVT::i8, Custom);
79 setOperationAction(ISD::ADD, MVT::i16, Custom);
81 setOperationAction(ISD::OR, MVT::i8, Custom);
82 setOperationAction(ISD::AND, MVT::i8, Custom);
83 setOperationAction(ISD::XOR, MVT::i8, Custom);
85 setOperationAction(ISD::FrameIndex, MVT::i16, Custom);
86 setOperationAction(ISD::CALL, MVT::i16, Custom);
87 setOperationAction(ISD::RET, MVT::Other, Custom);
89 setOperationAction(ISD::MUL, MVT::i8, Custom);
90 setOperationAction(ISD::MUL, MVT::i16, Expand);
91 setOperationAction(ISD::MUL, MVT::i32, Expand);
93 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
95 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
96 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
97 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
98 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
99 setOperationAction(ISD::MULHU, MVT::i8, Expand);
100 setOperationAction(ISD::MULHU, MVT::i16, Expand);
101 setOperationAction(ISD::MULHU, MVT::i32, Expand);
102 setOperationAction(ISD::MULHS, MVT::i8, Expand);
103 setOperationAction(ISD::MULHS, MVT::i16, Expand);
104 setOperationAction(ISD::MULHS, MVT::i32, Expand);
106 setOperationAction(ISD::SRA, MVT::i8, Custom);
107 setOperationAction(ISD::SRA, MVT::i16, Expand);
108 setOperationAction(ISD::SRA, MVT::i32, Expand);
109 setOperationAction(ISD::SHL, MVT::i8, Custom);
110 setOperationAction(ISD::SHL, MVT::i16, Expand);
111 setOperationAction(ISD::SHL, MVT::i32, Expand);
112 setOperationAction(ISD::SRL, MVT::i8, Custom);
113 setOperationAction(ISD::SRL, MVT::i16, Expand);
114 setOperationAction(ISD::SRL, MVT::i32, Expand);
116 // PIC16 does not support shift parts
117 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
118 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
119 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
120 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
121 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
122 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
124 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
125 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
128 // PIC16 does not have a SETCC, expand it to SELECT_CC.
129 setOperationAction(ISD::SETCC, MVT::i8, Expand);
130 setOperationAction(ISD::SELECT, MVT::i8, Expand);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BRIND, MVT::Other, Expand);
134 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
135 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
137 //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom);
138 setTruncStoreAction(MVT::i16, MVT::i8, Custom);
140 // Now deduce the information based on the above mentioned
142 computeRegisterProperties();
145 static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) {
146 if (N.getOpcode() == ISD::MERGE_VALUES) {
147 int NumResults = N.getNumOperands();
148 for( int i = 0; i < NumResults; i++)
149 Results.push_back(N.getOperand(i));
152 Results.push_back(N);
155 MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
161 PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
163 PIC16LibcallNames[Call] = Name;
167 PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
168 return PIC16LibcallNames[Call];
172 PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
173 MVT RetVT, const SDValue *Ops,
174 unsigned NumOps, bool isSigned,
175 SelectionDAG &DAG, DebugLoc dl) {
177 TargetLowering::ArgListTy Args;
178 Args.reserve(NumOps);
180 TargetLowering::ArgListEntry Entry;
181 for (unsigned i = 0; i != NumOps; ++i) {
183 Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
184 Entry.isSExt = isSigned;
185 Entry.isZExt = !isSigned;
186 Args.push_back(Entry);
188 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
190 const Type *RetTy = RetVT.getTypeForMVT();
191 std::pair<SDValue,SDValue> CallInfo =
192 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
193 false, CallingConv::C, false, Callee, Args, DAG, dl);
195 return CallInfo.first;
199 PIC16TargetLowering::getCurrentFrame(SelectionDAG &DAG) {
200 MachineFunction &MF = DAG.getMachineFunction();
201 const Function *Func = MF.getFunction();
202 const std::string FuncName = Func->getName();
204 // this is causing memory waste
205 // because for every call new memory will be allocated
206 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
207 sprintf(tmpName, "%s.tmp", FuncName.c_str());
209 // if the external symbol of the same name already exists then
210 // it will not create the new one.
211 return DAG.getTargetExternalSymbol(tmpName, MVT::i8);
215 PIC16TargetLowering::getCurrentFrameIndex(SelectionDAG &DAG, SDValue &ES,
216 unsigned SlotSize, int &FromFI) {
217 MachineFunction &MF = DAG.getMachineFunction();
218 const Function *Func = MF.getFunction();
219 const std::string FuncName = Func->getName();
221 // this is causing memory waste
222 // because for every call new memory will be allocated
223 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
224 sprintf(tmpName, "%s.tmp", FuncName.c_str());
226 // if the external symbol of the same name already exists then
227 // it will not create the new one.
228 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
230 // Alignment is always 1
231 //FromFI = MF.getFrameInfo()->CreateStackObject(SlotSize, 1);
232 FromFI = MF.getFrameInfo()->CreateStackObject(1, 1);
234 for(unsigned i=1;i<SlotSize; ++i) {
235 FI = MF.getFrameInfo()->CreateStackObject(1, 1);
239 const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
241 default: return NULL;
242 case PIC16ISD::Lo: return "PIC16ISD::Lo";
243 case PIC16ISD::Hi: return "PIC16ISD::Hi";
244 case PIC16ISD::MTLO: return "PIC16ISD::MTLO";
245 case PIC16ISD::MTHI: return "PIC16ISD::MTHI";
246 case PIC16ISD::Banksel: return "PIC16ISD::Banksel";
247 case PIC16ISD::PIC16Load: return "PIC16ISD::PIC16Load";
248 case PIC16ISD::PIC16LdWF: return "PIC16ISD::PIC16LdWF";
249 case PIC16ISD::PIC16Store: return "PIC16ISD::PIC16Store";
250 case PIC16ISD::PIC16StWF: return "PIC16ISD::PIC16StWF";
251 case PIC16ISD::BCF: return "PIC16ISD::BCF";
252 case PIC16ISD::LSLF: return "PIC16ISD::LSLF";
253 case PIC16ISD::LRLF: return "PIC16ISD::LRLF";
254 case PIC16ISD::RLF: return "PIC16ISD::RLF";
255 case PIC16ISD::RRF: return "PIC16ISD::RRF";
256 case PIC16ISD::CALL: return "PIC16ISD::CALL";
257 case PIC16ISD::SUBCC: return "PIC16ISD::SUBCC";
258 case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC";
259 case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND";
260 case PIC16ISD::Dummy: return "PIC16ISD::Dummy";
264 void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
265 SmallVectorImpl<SDValue>&Results,
268 switch (N->getOpcode()) {
269 case ISD::GlobalAddress:
270 Results.push_back(ExpandGlobalAddress(N, DAG));
272 case ISD::ExternalSymbol:
273 Results.push_back(ExpandExternalSymbol(N, DAG));
276 Results.push_back(ExpandStore(N, DAG));
279 PopulateResults(ExpandLoad(N, DAG), Results);
282 // Results.push_back(ExpandAdd(N, DAG));
284 case ISD::FrameIndex:
285 Results.push_back(ExpandFrameIndex(N, DAG));
288 assert (0 && "not implemented");
293 SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
295 // Currently handling FrameIndex of size MVT::i16 only
296 // One example of this scenario is when return value is written on
299 if (N->getValueType(0) != MVT::i16)
302 // Expand the FrameIndex into ExternalSymbol and a Constant node
303 // The constant will represent the frame index number
304 // Get the current function frame
305 MachineFunction &MF = DAG.getMachineFunction();
306 const Function *Func = MF.getFunction();
307 const std::string Name = Func->getName();
309 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
310 // FIXME there isn't really debug info here
311 DebugLoc dl = FR->getDebugLoc();
312 int Index = FR->getIndex();
315 FI[0] = DAG.getTargetFrameIndex(Index, MVT::i8);
316 FI[1] = DAG.getTargetFrameIndex(Index + 1, MVT::i8);
317 return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), FI[0], FI[1]);
321 SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
322 StoreSDNode *St = cast<StoreSDNode>(N);
323 SDValue Chain = St->getChain();
324 SDValue Src = St->getValue();
325 SDValue Ptr = St->getBasePtr();
326 MVT ValueType = Src.getValueType();
327 unsigned StoreOffset = 0;
328 DebugLoc dl = N->getDebugLoc();
330 SDValue PtrLo, PtrHi;
331 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset);
333 if (ValueType == MVT::i8) {
334 return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
336 DAG.getConstant (0 + StoreOffset, MVT::i8));
338 else if (ValueType == MVT::i16) {
339 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
340 SDValue SrcLo, SrcHi;
341 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
342 SDValue ChainLo = Chain, ChainHi = Chain;
343 if (Chain.getOpcode() == ISD::TokenFactor) {
344 ChainLo = Chain.getOperand(0);
345 ChainHi = Chain.getOperand(1);
347 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
350 DAG.getConstant (0 + StoreOffset, MVT::i8));
352 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
354 DAG.getConstant (1 + StoreOffset, MVT::i8));
356 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
359 else if (ValueType == MVT::i32) {
360 // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR.
361 SDValue SrcLo, SrcHi;
362 GetExpandedParts(Src, DAG, SrcLo, SrcHi);
364 // Get the expanded parts of each of SrcLo and SrcHi.
365 SDValue SrcLo1, SrcLo2, SrcHi1, SrcHi2;
366 GetExpandedParts(SrcLo, DAG, SrcLo1, SrcLo2);
367 GetExpandedParts(SrcHi, DAG, SrcHi1, SrcHi2);
369 SDValue ChainLo = Chain, ChainHi = Chain;
370 if (Chain.getOpcode() == ISD::TokenFactor) {
371 ChainLo = Chain.getOperand(0);
372 ChainHi = Chain.getOperand(1);
374 SDValue ChainLo1 = ChainLo, ChainLo2 = ChainLo, ChainHi1 = ChainHi,
376 if (ChainLo.getOpcode() == ISD::TokenFactor) {
377 ChainLo1 = ChainLo.getOperand(0);
378 ChainLo2 = ChainLo.getOperand(1);
380 if (ChainHi.getOpcode() == ISD::TokenFactor) {
381 ChainHi1 = ChainHi.getOperand(0);
382 ChainHi2 = ChainHi.getOperand(1);
384 SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
386 SrcLo1, PtrLo, PtrHi,
387 DAG.getConstant (0 + StoreOffset, MVT::i8));
389 SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
390 SrcLo2, PtrLo, PtrHi,
391 DAG.getConstant (1 + StoreOffset, MVT::i8));
393 SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
394 SrcHi1, PtrLo, PtrHi,
395 DAG.getConstant (2 + StoreOffset, MVT::i8));
397 SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
398 SrcHi2, PtrLo, PtrHi,
399 DAG.getConstant (3 + StoreOffset, MVT::i8));
401 SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
402 getChain(Store1), getChain(Store2));
403 SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
404 getChain(Store3), getChain(Store4));
405 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
409 assert (0 && "value type not supported");
414 SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
416 ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
417 // FIXME there isn't really debug info here
418 DebugLoc dl = ES->getDebugLoc();
420 SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
422 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES);
423 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES);
425 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
428 // ExpandGlobalAddress -
429 SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
430 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
431 // FIXME there isn't really debug info here
432 DebugLoc dl = G->getDebugLoc();
434 SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
437 SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA);
438 SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA);
440 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
443 bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
444 assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
446 if (Op.getOpcode() == ISD::BUILD_PAIR) {
447 if (Op.getOperand(0).getOpcode() == PIC16ISD::Lo)
453 // Return true if DirectAddress is in ROM_SPACE
454 bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
456 // RomAddress is a GlobalAddress in ROM_SPACE_
457 // If the Op is not a GlobalAddress return NULL without checking
459 if (!isDirectAddress(Op))
462 // Its a GlobalAddress.
463 // It is BUILD_PAIR((PIC16Lo TGA), (PIC16Hi TGA)) and Op is BUILD_PAIR
464 SDValue TGA = Op.getOperand(0).getOperand(0);
465 GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(TGA);
466 const Type *ValueType = GSDN->getGlobal()->getType();
468 if (!isa<PointerType>(ValueType)) {
469 assert(0 && "TGA must be of a PointerType");
472 int AddrSpace = dyn_cast<PointerType>(ValueType)->getAddressSpace();
473 if (AddrSpace == PIC16ISD::ROM_SPACE)
476 // Any other address space return it false
480 // Extract the out flag
481 SDValue PIC16TargetLowering::getOutFlag(SDValue &Op) {
482 SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1);
484 assert (Flag.getValueType() == MVT::Flag && "Node does not have an out Flag");
489 // To extract chain value from the SDValue Nodes
490 // This function will help to maintain the chain extracting
491 // code at one place. In case of any change in future it will
492 // help maintain the code.
493 SDValue PIC16TargetLowering::getChain(SDValue &Op) {
494 SDValue Chain = Op.getValue(Op.getNode()->getNumValues() - 1);
496 // If the last value returned in Flag then the chain is
497 // second last value returned.
498 if (Chain.getValueType() == MVT::Flag)
499 Chain = Op.getValue(Op.getNode()->getNumValues() - 2);
501 // All nodes may not produce a chain. Therefore following assert
502 // verifies that the node is returning a chain only.
503 assert (Chain.getValueType() == MVT::Other && "Node does not have a chain");
508 void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
509 SDValue &Lo, SDValue &Hi) {
510 SDNode *N = Op.getNode();
511 DebugLoc dl = N->getDebugLoc();
513 std::vector<SDValue> Opers;
514 NewVT = getTypeToTransformTo(N->getValueType(0));
516 // extract the lo component
518 Opers.push_back(DAG.getConstant(0,MVT::i8));
519 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT,dl,NewVT,&Opers[0],Opers.size());
520 // extract the hi component
523 Opers.push_back(DAG.getConstant(1,MVT::i8));
524 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT,dl,NewVT,&Opers[0],Opers.size());
527 // Legalize FrameIndex into ExternalSymbol and offset.
529 PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
530 SDValue &ES, int &Offset) {
532 MachineFunction &MF = DAG.getMachineFunction();
533 const Function *Func = MF.getFunction();
534 const std::string Name = Func->getName();
536 char *tmpName = new char [strlen(Name.c_str()) + 8];
537 sprintf(tmpName, "%s.args", Name.c_str());
538 ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
539 FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(Op);
540 Offset = FR->getIndex();
545 // This function legalizes the PIC16 Addresses. If the Pointer is
546 // -- Direct address variable residing
547 // --> then a Banksel for that variable will be created.
549 // --> then it will be treated as an indirect address.
550 // -- Indirect address
551 // --> then the address will be loaded into FSR
552 // -- ADD with constant operand
553 // --> then constant operand of ADD will be returned as Offset
554 // and non-constant operand of ADD will be treated as pointer.
555 // Returns the high and lo part of the address, and the offset(in case of ADD).
557 void PIC16TargetLowering:: LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
558 SDValue &Lo, SDValue &Hi,
561 // Offset, by default, should be 0
564 // If the pointer is ADD with constant,
565 // return the constant value as the offset
566 if (Ptr.getOpcode() == ISD::ADD) {
567 SDValue OperLeft = Ptr.getOperand(0);
568 SDValue OperRight = Ptr.getOperand(1);
569 if (OperLeft.getOpcode() == ISD::Constant) {
570 Offset = dyn_cast<ConstantSDNode>(OperLeft)->getZExtValue();
572 } else if (OperRight.getOpcode() == ISD::Constant) {
573 Offset = dyn_cast<ConstantSDNode>(OperRight)->getZExtValue();
578 // If the pointer is Type i8 and an external symbol
579 // then treat it as direct address.
580 // One example for such case is storing and loading
581 // from function frame during a call
582 if (Ptr.getValueType() == MVT::i8) {
583 switch (Ptr.getOpcode()) {
584 case ISD::TargetExternalSymbol:
586 Hi = DAG.getConstant(1, MVT::i8);
591 if (Ptr.getOpcode() == ISD::BUILD_PAIR &&
592 Ptr.getOperand(0).getOpcode() == ISD::TargetFrameIndex) {
595 LegalizeFrameIndex(Ptr.getOperand(0), DAG, Lo, FrameOffset);
596 Hi = DAG.getConstant(1, MVT::i8);
597 Offset += FrameOffset;
601 if (isDirectAddress(Ptr) && !isRomAddress(Ptr)) {
602 // Direct addressing case for RAM variables. The Hi part is constant
603 // and the Lo part is the TGA itself.
604 Lo = Ptr.getOperand(0).getOperand(0);
606 // For direct addresses Hi is a constant. Value 1 for the constant
607 // signifies that banksel needs to generated for it. Value 0 for
608 // the constant signifies that banksel does not need to be generated
609 // for it. Mark it as 1 now and optimize later.
610 Hi = DAG.getConstant(1, MVT::i8);
614 // Indirect addresses. Get the hi and lo parts of ptr.
615 GetExpandedParts(Ptr, DAG, Lo, Hi);
617 // Put the hi and lo parts into FSR.
618 Lo = DAG.getNode(PIC16ISD::MTLO, MVT::i8, Lo);
619 Hi = DAG.getNode(PIC16ISD::MTHI, MVT::i8, Hi);
624 //SDValue PIC16TargetLowering::ExpandAdd(SDNode *N, SelectionDAG &DAG) {
625 //SDValue OperLeft = N->getOperand(0);
626 //SDValue OperRight = N->getOperand(1);
628 //if((OperLeft.getOpcode() == ISD::Constant) ||
629 //(OperRight.getOpcode() == ISD::Constant)) {
633 // These case are yet to be handled
637 SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
638 LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
639 SDValue Chain = LD->getChain();
640 SDValue Ptr = LD->getBasePtr();
641 DebugLoc dl = LD->getDebugLoc();
643 SDValue Load, Offset;
646 SDValue PtrLo, PtrHi;
649 // Legalize direct/indirect addresses. This will give the lo and hi parts
650 // of the address and the offset.
651 LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset);
653 // Load from the pointer (direct address or FSR)
654 VT = N->getValueType(0);
655 unsigned NumLoads = VT.getSizeInBits() / 8;
656 std::vector<SDValue> PICLoads;
658 MVT MemVT = LD->getMemoryVT();
659 if(ISD::isNON_EXTLoad(N)) {
660 for (iter=0; iter<NumLoads ; ++iter) {
661 // Add the pointer offset if any
662 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
663 Tys = DAG.getVTList(MVT::i8, MVT::Other);
664 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
666 PICLoads.push_back(Load);
669 // If it is extended load then use PIC16Load for Memory Bytes
670 // and for all extended bytes perform action based on type of
671 // extention - i.e. SignExtendedLoad or ZeroExtendedLoad
674 // For extended loads this is the memory value type
675 // i.e. without any extension
676 MVT MemVT = LD->getMemoryVT();
677 unsigned MemBytes = MemVT.getSizeInBits() / 8;
678 unsigned ExtdBytes = VT.getSizeInBits() / 8;
679 Offset = DAG.getConstant(LoadOffset, MVT::i8);
681 Tys = DAG.getVTList(MVT::i8, MVT::Other);
682 // For MemBytes generate PIC16Load with proper offset
683 for (iter=0; iter<MemBytes; ++iter) {
684 // Add the pointer offset if any
685 Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
686 Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
688 PICLoads.push_back(Load);
691 // For SignExtendedLoad
692 if (ISD::isSEXTLoad(N)) {
693 // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
695 SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
696 DAG.getConstant(7, MVT::i8));
697 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
698 PICLoads.push_back(SRA);
700 } else if (ISD::isZEXTLoad(N)) {
701 // ZeroExtendedLoad -- For all ExtdBytes use constant 0
702 SDValue ConstZero = DAG.getConstant(0, MVT::i8);
703 for (iter=MemBytes; iter<ExtdBytes; ++iter) {
704 PICLoads.push_back(ConstZero);
711 // Operand of Load is illegal -- Load itself is legal
714 else if (VT == MVT::i16) {
715 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
716 if (MemVT == MVT::i8)
717 Chain = getChain(PICLoads[0]);
719 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
720 getChain(PICLoads[0]), getChain(PICLoads[1]));
721 } else if (VT == MVT::i32) {
723 BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
724 PICLoads[0], PICLoads[1]);
725 BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
726 PICLoads[2], PICLoads[3]);
727 BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
728 if (MemVT == MVT::i8)
729 Chain = getChain(PICLoads[0]);
730 else if (MemVT == MVT::i16)
731 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
732 getChain(PICLoads[0]), getChain(PICLoads[1]));
735 Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
736 getChain(PICLoads[0]), getChain(PICLoads[1]));
737 Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
738 getChain(PICLoads[2]), getChain(PICLoads[3]));
739 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
740 Chains[0], Chains[1]);
743 Tys = DAG.getVTList(VT, MVT::Other);
744 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
747 SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
748 // We should have handled larger operands in type legalizer itself.
749 assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
751 SDNode *N = Op.getNode();
752 SDValue Value = N->getOperand(0);
753 SDValue Amt = N->getOperand(1);
754 PIC16ISD::PIC16Libcall CallCode;
755 switch (N->getOpcode()) {
757 CallCode = PIC16ISD::SRA_I8;
760 CallCode = PIC16ISD::SLL_I8;
763 CallCode = PIC16ISD::SRL_I8;
766 assert ( 0 && "This shift is not implemented yet.");
769 SmallVector<SDValue, 2> Ops(2);
772 SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
773 true, DAG, N->getDebugLoc());
778 PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
779 SmallVectorImpl<SDValue>&Results,
781 SDValue Op = SDValue(N, 0);
784 switch (Op.getOpcode()) {
785 case ISD::FORMAL_ARGUMENTS:
786 Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
788 Res = ExpandLoad(Op.getNode(), DAG); break;
790 Res = LowerCALL(Op, DAG); break;
792 // All other operations are handled in LowerOperation.
793 Res = LowerOperation(Op, DAG);
795 Results.push_back(Res);
802 unsigned NumValues = N->getNumValues();
803 for (i = 0; i < NumValues ; i++) {
804 Results.push_back(SDValue(N, i));
808 SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
809 switch (Op.getOpcode()) {
810 case ISD::FORMAL_ARGUMENTS:
811 return LowerFORMAL_ARGUMENTS(Op, DAG);
815 return LowerADD(Op, DAG);
819 return LowerSUB(Op, DAG);
821 return ExpandLoad(Op.getNode(), DAG);
823 return ExpandStore(Op.getNode(), DAG);
827 return LowerShift(Op, DAG);
831 return LowerBinOp(Op, DAG);
833 return LowerCALL(Op, DAG);
835 return LowerRET(Op, DAG);
837 return LowerBR_CC(Op, DAG);
839 return LowerSELECT_CC(Op, DAG);
844 SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
847 assert (Op.getValueType() == MVT::i8
848 && "illegal value type to store on stack.");
850 MachineFunction &MF = DAG.getMachineFunction();
851 const Function *Func = MF.getFunction();
852 const std::string FuncName = Func->getName();
854 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
856 // Put the value on stack.
857 // Get a stack slot index and convert to es.
858 int FI = MF.getFrameInfo()->CreateStackObject(1, 1);
859 sprintf(tmpName, "%s.tmp", FuncName.c_str());
860 SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
862 // Store the value to ES.
863 SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
866 DAG.getConstant (1, MVT::i8), // Banksel.
867 DAG.getConstant (FI, MVT::i8));
869 // Load the value from ES.
870 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
871 SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
872 ES, DAG.getConstant (1, MVT::i8),
873 DAG.getConstant (FI, MVT::i8));
875 return Load.getValue(0);
879 PIC16TargetLowering::LowerCallArguments(SDValue Op, SDValue Chain,
880 SDValue FrameAddress,
883 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
884 unsigned NumOps = TheCall->getNumArgs();
885 DebugLoc dl = TheCall->getDebugLoc();
887 SDValue Arg, StoreAt;
893 // FIXME: This portion of code currently assumes only
894 // primitive types being passed as arguments.
896 // Legalize the address before use
897 SDValue PtrLo, PtrHi;
898 unsigned AddressOffset;
900 LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset);
903 std::vector<SDValue> Ops;
904 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
905 for (unsigned i=ArgCount, Offset = 0; i<NumOps; i++) {
907 Arg = TheCall->getArg(i);
909 StoreOffset = (Offset + AddressOffset);
911 // Store the argument on frame
914 Ops.push_back(Chain);
915 Ops.push_back(Arg.getValue(0));
916 Ops.push_back(PtrLo);
917 Ops.push_back(PtrHi);
918 Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
919 Ops.push_back(InFlag);
921 StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
923 Chain = getChain(StoreRet);
924 InFlag = getOutFlag(StoreRet);
926 // Update the frame offset to be used for next argument
927 ArgVT = Arg.getValueType();
928 Size = ArgVT.getSizeInBits();
929 Size = Size/8; // Calculate size in bytes
930 Offset += Size; // Increase the frame offset
936 PIC16TargetLowering::LowerCallReturn(SDValue Op, SDValue Chain,
937 SDValue FrameAddress,
940 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
941 DebugLoc dl = TheCall->getDebugLoc();
942 // Currently handling primitive types only. They will come in
944 unsigned RetVals = TheCall->getNumRetVals();
946 std::vector<SDValue> ResultVals;
948 // Return immediately if the return type is void
952 // Call has something to return
954 // Legalize the address before use
957 LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset);
959 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
962 for(unsigned i=0, Offset=0;i<RetVals;i++) {
964 LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
965 DAG.getConstant(LdOffset + Offset, MVT::i8),
968 InFlag = getOutFlag(LoadRet);
970 Chain = getChain(LoadRet);
972 ResultVals.push_back(LoadRet);
975 // To return use MERGE_VALUES
976 ResultVals.push_back(Chain);
977 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
981 SDValue PIC16TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
982 //int NumOps = Op.getNode()->getNumOperands();
984 // For default cases LLVM returns the value on the function frame
985 // So let LLVM do this for all the cases other than character
989 SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
990 CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
991 SDValue Chain = TheCall->getChain();
992 SDValue Callee = TheCall->getCallee();
993 DebugLoc dl = TheCall->getDebugLoc();
995 if (Callee.getValueType() == MVT::i16 &&
996 Callee.getOpcode() == ISD::BUILD_PAIR) {
997 // It has come from TypeLegalizer for lowering
999 Callee = Callee.getOperand(0).getOperand(0);
1001 std::vector<SDValue> Ops;
1002 Ops.push_back(Chain);
1003 Ops.push_back(Callee);
1005 // Add the call arguments and their flags
1006 unsigned NumArgs = TheCall->getNumArgs();
1007 for(i=0;i<NumArgs;i++) {
1008 Ops.push_back(TheCall->getArg(i));
1009 Ops.push_back(TheCall->getArgFlagsVal(i));
1012 std::vector<MVT> NodeTys;
1013 unsigned NumRets = TheCall->getNumRetVals();
1014 for(i=0;i<NumRets;i++)
1015 NodeTys.push_back(TheCall->getRetValType(i));
1017 // Return a Chain as well
1018 NodeTys.push_back(MVT::Other);
1020 SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
1022 DAG.getCall(TheCall->getCallingConv(), dl,
1023 TheCall->isVarArg(), TheCall->isTailCall(),
1024 TheCall->isInreg(), VTs, &Ops[0], Ops.size());
1029 SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
1031 // Start the call sequence.
1032 // Carring the Constant 0 along the CALLSEQSTART
1033 // because there is nothing else to carry.
1034 SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand);
1035 Chain = getChain(SeqStart);
1037 // For any direct call - callee will be GlobalAddressNode or
1040 // Considering the GlobalAddressNode case here.
1041 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1042 GlobalValue *GV = G->getGlobal();
1043 Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
1046 // Considering the ExternalSymbol case here
1047 if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1048 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
1051 SDValue OperFlag = getOutFlag(Chain); // To manage the data dependency
1055 // Considering GlobalAddress here
1056 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1057 Name = G->getGlobal()->getName();
1059 // Considering ExternalSymbol here
1060 if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee))
1061 Name = ES->getSymbol();
1063 char *argFrame = new char [strlen(Name.c_str()) + 8];
1064 sprintf(argFrame, "%s.args", Name.c_str());
1065 SDValue ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8);
1067 char *retName = new char [strlen(Name.c_str()) + 8];
1068 sprintf(retName, "%s.retval", Name.c_str());
1069 SDValue RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8);
1071 // Pass the argument to function before making the call.
1072 SDValue CallArgs = LowerCallArguments(Op, Chain, ArgLabel, OperFlag, DAG);
1073 Chain = getChain(CallArgs);
1074 OperFlag = getOutFlag(CallArgs);
1076 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
1077 SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
1079 Chain = getChain(PICCall);
1080 OperFlag = getOutFlag(PICCall);
1083 // Carrying the Constant 0 along the CALLSEQSTART
1084 // because there is nothing else to carry.
1085 SDValue SeqEnd = DAG.getCALLSEQ_END(Chain, ZeroOperand, ZeroOperand,
1087 Chain = getChain(SeqEnd);
1088 OperFlag = getOutFlag(SeqEnd);
1090 // Lower the return value reading after the call.
1091 return LowerCallReturn(Op, Chain, RetLabel, OperFlag, DAG);
1094 bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
1095 if (Op.getOpcode() == PIC16ISD::PIC16Load)
1096 if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
1097 || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
1102 bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) {
1103 // Return false if one of the operands is already a direct
1104 // load and that operand has only one use.
1105 if (Op.getOperand(0).getOpcode() == ISD::Constant ||
1106 Op.getOperand(1).getOpcode() == ISD::Constant)
1108 if (isDirectLoad(Op.getOperand(0))) {
1109 if (Op.getOperand(0).hasOneUse())
1114 if (isDirectLoad(Op.getOperand(1))) {
1115 if (Op.getOperand(1).hasOneUse())
1123 SDValue PIC16TargetLowering:: LowerBinOp(SDValue Op, SelectionDAG &DAG) {
1124 DebugLoc dl = Op.getDebugLoc();
1125 // We should have handled larger operands in type legalizer itself.
1126 assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
1128 if (NeedToConvertToMemOp(Op, MemOp)) {
1129 // Put one value on stack.
1130 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1132 return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
1140 SDValue PIC16TargetLowering:: LowerADD(SDValue Op, SelectionDAG &DAG) {
1141 // We should have handled larger operands in type legalizer itself.
1142 assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
1143 DebugLoc dl = Op.getDebugLoc();
1145 if (NeedToConvertToMemOp(Op, MemOp)) {
1146 // Put one value on stack.
1147 SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
1149 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1151 if (Op.getOpcode() == ISD::ADDE)
1152 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1153 NewVal, Op.getOperand(2));
1155 return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
1158 else if (Op.getOpcode() == ISD::ADD) {
1166 SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
1167 DebugLoc dl = Op.getDebugLoc();
1168 // We should have handled larger operands in type legalizer itself.
1169 assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
1171 // Nothing to do if the first operand is already a direct load and it has
1173 if (isDirectLoad(Op.getOperand(0)) && Op.getOperand(0).hasOneUse())
1176 // Put first operand on stack.
1177 SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
1179 SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
1180 if (Op.getOpcode() == ISD::SUBE)
1181 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
1184 return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
1187 // LowerFORMAL_ARGUMENTS - In Lowering FORMAL ARGUMENTS - MERGE_VALUES nodes
1188 // is returned. MERGE_VALUES nodes number of operands and number of values are
1189 // equal. Therefore to construct MERGE_VALUE node, UNDEF nodes equal to the
1190 // number of arguments of function have been created.
1192 SDValue PIC16TargetLowering:: LowerFORMAL_ARGUMENTS(SDValue Op,
1193 SelectionDAG &DAG) {
1194 SmallVector<SDValue, 8> ArgValues;
1195 unsigned NumArgs = Op.getNumOperands() - 3;
1196 DebugLoc dl = Op.getDebugLoc();
1198 // Creating UNDEF nodes to meet the requirement of MERGE_VALUES node.
1199 for(unsigned i = 0 ; i<NumArgs ; i++) {
1200 SDValue TempNode = DAG.getUNDEF(Op.getNode()->getValueType(i));
1201 ArgValues.push_back(TempNode);
1204 ArgValues.push_back(Op.getOperand(0));
1205 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1207 ArgValues.size()).getValue(Op.getResNo());
1210 // Perform DAGCombine of PIC16Load
1211 SDValue PIC16TargetLowering::
1212 PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1213 SelectionDAG &DAG = DCI.DAG;
1214 SDValue Chain = N->getOperand(0);
1215 if (N->hasNUsesOfValue(0, 0)) {
1216 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), Chain);
1222 SDValue PIC16TargetLowering::PerformDAGCombine(SDNode *N,
1223 DAGCombinerInfo &DCI) const {
1224 switch (N->getOpcode()) {
1225 case PIC16ISD::PIC16Load:
1226 return PerformPIC16LoadCombine(N, DCI);
1231 static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
1233 default: assert(0 && "Unknown condition code!");
1234 case ISD::SETNE: return PIC16CC::NE;
1235 case ISD::SETEQ: return PIC16CC::EQ;
1236 case ISD::SETGT: return PIC16CC::GT;
1237 case ISD::SETGE: return PIC16CC::GE;
1238 case ISD::SETLT: return PIC16CC::LT;
1239 case ISD::SETLE: return PIC16CC::LE;
1240 case ISD::SETULT: return PIC16CC::ULT;
1241 case ISD::SETULE: return PIC16CC::LE;
1242 case ISD::SETUGE: return PIC16CC::GE;
1243 case ISD::SETUGT: return PIC16CC::UGT;
1247 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1248 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1249 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1250 ISD::CondCode CC, unsigned &SPCC) {
1251 if (isa<ConstantSDNode>(RHS) &&
1252 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1254 (LHS.getOpcode() == PIC16ISD::SELECT_ICC &&
1255 LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) &&
1256 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1257 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1258 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
1259 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
1260 SDValue CMPCC = LHS.getOperand(3);
1261 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1262 LHS = CMPCC.getOperand(0);
1263 RHS = CMPCC.getOperand(1);
1267 // Returns appropriate CMP insn and corresponding condition code in PIC16CC
1268 SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
1269 unsigned CC, SDValue &PIC16CC,
1270 SelectionDAG &DAG, DebugLoc dl) {
1271 PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
1273 // PIC16 sub is literal - W. So Swap the operands and condition if needed.
1274 // i.e. a < 12 can be rewritten as 12 > a.
1275 if (RHS.getOpcode() == ISD::Constant) {
1284 CondCode = PIC16CC::GT;
1287 CondCode = PIC16CC::LT;
1290 CondCode = PIC16CC::UGT;
1293 CondCode = PIC16CC::ULT;
1296 CondCode = PIC16CC::LE;
1299 CondCode = PIC16CC::GE;
1302 CondCode = PIC16CC::UGE;
1305 CondCode = PIC16CC::ULE;
1310 PIC16CC = DAG.getConstant(CondCode, MVT::i8);
1312 // These are signed comparisons.
1313 SDValue Mask = DAG.getConstant(128, MVT::i8);
1314 if (isSignedComparison(CondCode)) {
1315 LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
1316 RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
1319 SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
1320 // We can use a subtract operation to set the condition codes. But
1321 // we need to put one operand in memory if required.
1322 // Nothing to do if the first operand is already a valid type (direct load
1323 // for subwf and literal for sublw) and it is used by this operation only.
1324 if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
1326 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1328 // else convert the first operand to mem.
1329 LHS = ConvertToMemOperand (LHS, DAG, dl);
1330 return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
1334 SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1335 SDValue LHS = Op.getOperand(0);
1336 SDValue RHS = Op.getOperand(1);
1337 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1338 SDValue TrueVal = Op.getOperand(2);
1339 SDValue FalseVal = Op.getOperand(3);
1340 unsigned ORIGCC = ~0;
1341 DebugLoc dl = Op.getDebugLoc();
1343 // If this is a select_cc of a "setcc", and if the setcc got lowered into
1344 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1346 // A setcc: lhs, rhs, cc is expanded by llvm to
1347 // select_cc: result of setcc, 0, 1, 0, setne
1348 // We can think of it as:
1349 // select_cc: lhs, rhs, 1, 0, cc
1350 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1351 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1354 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1356 return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
1357 FalseVal, PIC16CC, Cmp.getValue(1));
1361 PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1362 MachineBasicBlock *BB) {
1363 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1364 unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
1366 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1367 // control-flow pattern. The incoming instruction knows the destination vreg
1368 // to set, the condition code register to branch on, the true/false values to
1369 // select between, and a branch opcode to use.
1370 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1371 MachineFunction::iterator It = BB;
1378 // fallthrough --> copy0MBB
1379 MachineBasicBlock *thisMBB = BB;
1380 MachineFunction *F = BB->getParent();
1381 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1382 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1383 BuildMI(BB, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
1384 F->insert(It, copy0MBB);
1385 F->insert(It, sinkMBB);
1387 // Update machine-CFG edges by transferring all successors of the current
1388 // block to the new block which will contain the Phi node for the select.
1389 sinkMBB->transferSuccessors(BB);
1390 // Next, add the true and fallthrough blocks as its successors.
1391 BB->addSuccessor(copy0MBB);
1392 BB->addSuccessor(sinkMBB);
1395 // %FalseValue = ...
1396 // # fallthrough to sinkMBB
1399 // Update machine-CFG edges
1400 BB->addSuccessor(sinkMBB);
1403 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1406 BuildMI(BB, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
1407 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1408 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1410 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1415 SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1416 SDValue Chain = Op.getOperand(0);
1417 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1418 SDValue LHS = Op.getOperand(2); // LHS of the condition.
1419 SDValue RHS = Op.getOperand(3); // RHS of the condition.
1420 SDValue Dest = Op.getOperand(4); // BB to jump to
1421 unsigned ORIGCC = ~0;
1422 DebugLoc dl = Op.getDebugLoc();
1424 // If this is a br_cc of a "setcc", and if the setcc got lowered into
1425 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
1426 LookThroughSetCC(LHS, RHS, CC, ORIGCC);
1427 if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
1429 // Get the Compare insn and condition code.
1431 SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
1433 return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,