1 //===- PIC16InstrInfo.cpp - PIC16 Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PIC16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "PIC16ABINames.h"
16 #include "PIC16InstrInfo.h"
17 #include "PIC16TargetMachine.h"
18 #include "PIC16GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
30 // FIXME: Add the subtarget support on this constructor.
31 PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
32 : TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
34 RegInfo(*this, *TM.getSubtargetImpl()) {}
37 /// isStoreToStackSlot - If the specified machine instruction is a direct
38 /// store to a stack slot, return the virtual or physical register number of
39 /// the source reg along with the FrameIndex of the loaded stack slot.
40 /// If not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than storing to the stack slot.
42 unsigned PIC16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
43 int &FrameIndex) const {
44 if (MI->getOpcode() == PIC16::movwf
45 && MI->getOperand(0).isReg()
46 && MI->getOperand(1).isSymbol()) {
47 FrameIndex = MI->getOperand(1).getIndex();
48 return MI->getOperand(0).getReg();
53 /// isLoadFromStackSlot - If the specified machine instruction is a direct
54 /// load from a stack slot, return the virtual or physical register number of
55 /// the dest reg along with the FrameIndex of the stack slot.
56 /// If not, return 0. This predicate must return 0 if the instruction has
57 /// any side effects other than storing to the stack slot.
58 unsigned PIC16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
59 int &FrameIndex) const {
60 if (MI->getOpcode() == PIC16::movf
61 && MI->getOperand(0).isReg()
62 && MI->getOperand(1).isSymbol()) {
63 FrameIndex = MI->getOperand(1).getIndex();
64 return MI->getOperand(0).getReg();
70 void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator I,
72 unsigned SrcReg, bool isKill, int FI,
73 const TargetRegisterClass *RC) const {
74 PIC16TargetLowering *PTLI = TM.getTargetLowering();
75 DebugLoc DL = DebugLoc::getUnknownLoc();
76 if (I != MBB.end()) DL = I->getDebugLoc();
78 const Function *Func = MBB.getParent()->getFunction();
79 const std::string FuncName = Func->getName();
81 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
83 // On the order of operands here: think "movwf SrcReg, tmp_slot, offset".
84 if (RC == PIC16::GPRRegisterClass) {
85 //MachineFunction &MF = *MBB.getParent();
86 //MachineRegisterInfo &RI = MF.getRegInfo();
87 BuildMI(MBB, I, DL, get(PIC16::movwf))
88 .addReg(SrcReg, getKillRegState(isKill))
89 .addImm(PTLI->GetTmpOffsetForFI(FI, 1))
90 .addExternalSymbol(tmpName)
91 .addImm(1); // Emit banksel for it.
93 else if (RC == PIC16::FSR16RegisterClass) {
94 // This is a 16-bit register and the frameindex given by llvm is of
95 // size two here. Break this index N into two zero based indexes and
96 // put one into the map. The second one is always obtained by adding 1
97 // to the first zero based index. In fact it is going to use 3 slots
98 // as saving FSRs corrupts W also and hence we need to save/restore W also.
100 unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0
102 BuildMI(MBB, I, DL, get(opcode))
103 .addReg(SrcReg, getKillRegState(isKill))
104 .addImm(PTLI->GetTmpOffsetForFI(FI, 3))
105 .addExternalSymbol(tmpName)
106 .addImm(1); // Emit banksel for it.
109 llvm_unreachable("Can't store this register to stack slot");
112 void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator I,
114 unsigned DestReg, int FI,
115 const TargetRegisterClass *RC) const {
116 PIC16TargetLowering *PTLI = TM.getTargetLowering();
117 DebugLoc DL = DebugLoc::getUnknownLoc();
118 if (I != MBB.end()) DL = I->getDebugLoc();
120 const Function *Func = MBB.getParent()->getFunction();
121 const std::string FuncName = Func->getName();
123 const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
125 // On the order of operands here: think "movf FrameIndex, W".
126 if (RC == PIC16::GPRRegisterClass) {
127 //MachineFunction &MF = *MBB.getParent();
128 //MachineRegisterInfo &RI = MF.getRegInfo();
129 BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
130 .addImm(PTLI->GetTmpOffsetForFI(FI, 1))
131 .addExternalSymbol(tmpName)
132 .addImm(1); // Emit banksel for it.
134 else if (RC == PIC16::FSR16RegisterClass) {
135 // This is a 16-bit register and the frameindex given by llvm is of
136 // size two here. Break this index N into two zero based indexes and
137 // put one into the map. The second one is always obtained by adding 1
138 // to the first zero based index. In fact it is going to use 3 slots
139 // as saving FSRs corrupts W also and hence we need to save/restore W also.
141 unsigned opcode = (DestReg == PIC16::FSR0) ? PIC16::restore_fsr0
142 : PIC16::restore_fsr1;
143 BuildMI(MBB, I, DL, get(opcode), DestReg)
144 .addImm(PTLI->GetTmpOffsetForFI(FI, 3))
145 .addExternalSymbol(tmpName)
146 .addImm(1); // Emit banksel for it.
149 llvm_unreachable("Can't load this register from stack slot");
152 bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator I,
154 unsigned DestReg, unsigned SrcReg,
155 const TargetRegisterClass *DestRC,
156 const TargetRegisterClass *SrcRC) const {
157 DebugLoc DL = DebugLoc::getUnknownLoc();
158 if (I != MBB.end()) DL = I->getDebugLoc();
160 if (DestRC == PIC16::FSR16RegisterClass) {
161 BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg);
165 if (DestRC == PIC16::GPRRegisterClass) {
166 BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg);
170 // Not yet supported.
174 bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
175 unsigned &SrcReg, unsigned &DestReg,
176 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
177 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
179 if (MI.getOpcode() == PIC16::copy_fsr
180 || MI.getOpcode() == PIC16::copy_w) {
181 DestReg = MI.getOperand(0).getReg();
182 SrcReg = MI.getOperand(1).getReg();
189 /// InsertBranch - Insert a branch into the end of the specified
190 /// MachineBasicBlock. This operands to this method are the same as those
191 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
192 /// returns success and when an unconditional branch (TBB is non-null, FBB is
193 /// null, Cond is empty) needs to be inserted. It returns the number of
194 /// instructions inserted.
195 unsigned PIC16InstrInfo::
196 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
197 MachineBasicBlock *FBB,
198 const SmallVectorImpl<MachineOperand> &Cond) const {
199 // Shouldn't be a fall through.
200 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
202 if (FBB == 0) { // One way branch.
204 // Unconditional branch?
205 DebugLoc dl = DebugLoc::getUnknownLoc();
206 BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
211 // FIXME: If the there are some conditions specified then conditional branch
212 // should be generated.
213 // For the time being no instruction is being generated therefore
218 bool PIC16InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
219 MachineBasicBlock *&TBB,
220 MachineBasicBlock *&FBB,
221 SmallVectorImpl<MachineOperand> &Cond,
222 bool AllowModify) const {
223 MachineBasicBlock::iterator I = MBB.end();
224 if (I == MBB.begin())
227 // Get the terminator instruction.
229 // Handle unconditional branches. If the unconditional branch's target is
230 // successor basic block then remove the unconditional branch.
231 if (I->getOpcode() == PIC16::br_uncond && AllowModify) {
232 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
234 I->eraseFromParent();