1 //===- PIC16InstrInfo.cpp - PIC16 Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PIC16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "PIC16ABINames.h"
16 #include "PIC16InstrInfo.h"
17 #include "PIC16TargetMachine.h"
18 #include "PIC16GenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
30 // FIXME: Add the subtarget support on this constructor.
31 PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
32 : TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
34 RegInfo(*this, *TM.getSubtargetImpl()) {}
37 /// isStoreToStackSlot - If the specified machine instruction is a direct
38 /// store to a stack slot, return the virtual or physical register number of
39 /// the source reg along with the FrameIndex of the loaded stack slot.
40 /// If not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than storing to the stack slot.
42 unsigned PIC16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
43 int &FrameIndex) const {
44 if (MI->getOpcode() == PIC16::movwf
45 && MI->getOperand(0).isReg()
46 && MI->getOperand(1).isSymbol()) {
47 FrameIndex = MI->getOperand(1).getIndex();
48 return MI->getOperand(0).getReg();
53 /// isLoadFromStackSlot - If the specified machine instruction is a direct
54 /// load from a stack slot, return the virtual or physical register number of
55 /// the dest reg along with the FrameIndex of the stack slot.
56 /// If not, return 0. This predicate must return 0 if the instruction has
57 /// any side effects other than storing to the stack slot.
58 unsigned PIC16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
59 int &FrameIndex) const {
60 if (MI->getOpcode() == PIC16::movf
61 && MI->getOperand(0).isReg()
62 && MI->getOperand(1).isSymbol()) {
63 FrameIndex = MI->getOperand(1).getIndex();
64 return MI->getOperand(0).getReg();
70 void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator I,
72 unsigned SrcReg, bool isKill, int FI,
73 const TargetRegisterClass *RC,
74 const TargetRegisterInfo *TRI) const {
75 const PIC16TargetLowering *PTLI = TM.getTargetLowering();
77 if (I != MBB.end()) DL = I->getDebugLoc();
79 const Function *Func = MBB.getParent()->getFunction();
80 const std::string FuncName = Func->getName();
82 const char *tmpName = ESNames::createESName(PAN::getTempdataLabel(FuncName));
84 // On the order of operands here: think "movwf SrcReg, tmp_slot, offset".
85 if (RC == PIC16::GPRRegisterClass) {
86 //MachineFunction &MF = *MBB.getParent();
87 //MachineRegisterInfo &RI = MF.getRegInfo();
88 BuildMI(MBB, I, DL, get(PIC16::movwf))
89 .addReg(SrcReg, getKillRegState(isKill))
90 .addImm(PTLI->GetTmpOffsetForFI(FI, 1, *MBB.getParent()))
91 .addExternalSymbol(tmpName)
92 .addImm(1); // Emit banksel for it.
94 else if (RC == PIC16::FSR16RegisterClass) {
95 // This is a 16-bit register and the frameindex given by llvm is of
96 // size two here. Break this index N into two zero based indexes and
97 // put one into the map. The second one is always obtained by adding 1
98 // to the first zero based index. In fact it is going to use 3 slots
99 // as saving FSRs corrupts W also and hence we need to save/restore W also.
101 unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0
103 BuildMI(MBB, I, DL, get(opcode))
104 .addReg(SrcReg, getKillRegState(isKill))
105 .addImm(PTLI->GetTmpOffsetForFI(FI, 3, *MBB.getParent()))
106 .addExternalSymbol(tmpName)
107 .addImm(1); // Emit banksel for it.
110 llvm_unreachable("Can't store this register to stack slot");
113 void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator I,
115 unsigned DestReg, int FI,
116 const TargetRegisterClass *RC,
117 const TargetRegisterInfo *TRI) const {
118 const PIC16TargetLowering *PTLI = TM.getTargetLowering();
120 if (I != MBB.end()) DL = I->getDebugLoc();
122 const Function *Func = MBB.getParent()->getFunction();
123 const std::string FuncName = Func->getName();
125 const char *tmpName = ESNames::createESName(PAN::getTempdataLabel(FuncName));
127 // On the order of operands here: think "movf FrameIndex, W".
128 if (RC == PIC16::GPRRegisterClass) {
129 //MachineFunction &MF = *MBB.getParent();
130 //MachineRegisterInfo &RI = MF.getRegInfo();
131 BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
132 .addImm(PTLI->GetTmpOffsetForFI(FI, 1, *MBB.getParent()))
133 .addExternalSymbol(tmpName)
134 .addImm(1); // Emit banksel for it.
136 else if (RC == PIC16::FSR16RegisterClass) {
137 // This is a 16-bit register and the frameindex given by llvm is of
138 // size two here. Break this index N into two zero based indexes and
139 // put one into the map. The second one is always obtained by adding 1
140 // to the first zero based index. In fact it is going to use 3 slots
141 // as saving FSRs corrupts W also and hence we need to save/restore W also.
143 unsigned opcode = (DestReg == PIC16::FSR0) ? PIC16::restore_fsr0
144 : PIC16::restore_fsr1;
145 BuildMI(MBB, I, DL, get(opcode), DestReg)
146 .addImm(PTLI->GetTmpOffsetForFI(FI, 3, *MBB.getParent()))
147 .addExternalSymbol(tmpName)
148 .addImm(1); // Emit banksel for it.
151 llvm_unreachable("Can't load this register from stack slot");
154 void PIC16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
155 MachineBasicBlock::iterator I, DebugLoc DL,
156 unsigned DestReg, unsigned SrcReg,
157 bool KillSrc) const {
159 if (PIC16::FSR16RegClass.contains(DestReg, SrcReg))
160 Opc = PIC16::copy_fsr;
161 else if (PIC16::GPRRegClass.contains(DestReg, SrcReg))
164 llvm_unreachable("Impossible reg-to-reg copy");
166 BuildMI(MBB, I, DL, get(Opc), DestReg)
167 .addReg(SrcReg, getKillRegState(KillSrc));
170 /// InsertBranch - Insert a branch into the end of the specified
171 /// MachineBasicBlock. This operands to this method are the same as those
172 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
173 /// returns success and when an unconditional branch (TBB is non-null, FBB is
174 /// null, Cond is empty) needs to be inserted. It returns the number of
175 /// instructions inserted.
176 unsigned PIC16InstrInfo::
177 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
178 MachineBasicBlock *FBB,
179 const SmallVectorImpl<MachineOperand> &Cond,
181 // Shouldn't be a fall through.
182 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
184 if (FBB == 0) { // One way branch.
186 // Unconditional branch?
187 BuildMI(&MBB, DL, get(PIC16::br_uncond)).addMBB(TBB);
192 // FIXME: If the there are some conditions specified then conditional branch
193 // should be generated.
194 // For the time being no instruction is being generated therefore
199 bool PIC16InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
200 MachineBasicBlock *&TBB,
201 MachineBasicBlock *&FBB,
202 SmallVectorImpl<MachineOperand> &Cond,
203 bool AllowModify) const {
204 MachineBasicBlock::iterator I = MBB.end();
205 if (I == MBB.begin())
208 // Get the terminator instruction.
210 while (I->isDebugValue()) {
211 if (I == MBB.begin())
215 // Handle unconditional branches. If the unconditional branch's target is
216 // successor basic block then remove the unconditional branch.
217 if (I->getOpcode() == PIC16::br_uncond && AllowModify) {
218 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
220 I->eraseFromParent();