1 //===- PIC16InstrInfo.cpp - PIC16 Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PIC16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "PIC16InstrInfo.h"
16 #include "llvm/Function.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "PIC16GenInstrInfo.inc"
24 // FIXME: Add the subtarget support on this constructor.
25 PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
26 : TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImmediate() && op.getImm() == 0;
34 /// isLoadFromStackSlot - If the specified machine instruction is a direct
35 /// load from a stack slot, return the virtual or physical register number of
36 /// the destination along with the FrameIndex of the loaded stack slot. If
37 /// not, return 0. This predicate must return 0 if the instruction has
38 /// any side effects other than loading from the stack slot.
39 unsigned PIC16InstrInfo::
40 isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
42 if (MI->getOpcode() == PIC16::MOVF) {
43 if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
44 (MI->getOperand(1).isImmediate()) && // the imm is zero
45 (isZeroImm(MI->getOperand(1)))) {
46 FrameIndex = MI->getOperand(2).getIndex();
47 return MI->getOperand(0).getReg();
54 /// isStoreToStackSlot - If the specified machine instruction is a direct
55 /// store to a stack slot, return the virtual or physical register number of
56 /// the source reg along with the FrameIndex of the loaded stack slot. If
57 /// not, return 0. This predicate must return 0 if the instruction has
58 /// any side effects other than storing to the stack slot.
59 unsigned PIC16InstrInfo::
60 isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
62 if (MI->getOpcode() == PIC16::MOVWF) {
63 if ((MI->getOperand(0).isFrameIndex()) && // is a stack slot
64 (MI->getOperand(1).isImmediate()) && // the imm is zero
65 (isZeroImm(MI->getOperand(1)))) {
66 FrameIndex = MI->getOperand(0).getIndex();
67 return MI->getOperand(2).getReg();
74 storeRegToStackSlot(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator I,
76 unsigned SrcReg, bool isKill, int FI,
77 const TargetRegisterClass *RC) const {
78 const Function *Func = MBB.getParent()->getFunction();
79 const std::string FuncName = Func->getName();
81 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
82 sprintf(tmpName, "%s_tmp_%d",FuncName.c_str(),FI);
84 if (RC == PIC16::CPURegsRegisterClass) {
86 BuildMI(MBB, I, this->get(PIC16::MOVWF))
87 .addReg(SrcReg,false,false,true,true)
88 .addExternalSymbol(tmpName) // the current printer expects 3 operands,
89 .addExternalSymbol(tmpName); // all we need is actually one,
93 assert(0 && "Can't store this register to stack slot");
97 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
98 unsigned DestReg, int FI,
99 const TargetRegisterClass *RC) const
101 const Function *Func = MBB.getParent()->getFunction();
102 const std::string FuncName = Func->getName();
104 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
105 sprintf(tmpName, "%s_tmp_%d",FuncName.c_str(),FI);
107 if (RC == PIC16::CPURegsRegisterClass)
108 BuildMI(MBB, I, this->get(PIC16::MOVF), DestReg)
109 .addExternalSymbol(tmpName) // the current printer expects 3 operands,
110 .addExternalSymbol(tmpName); // all we need is actually one,so we repeat.
112 assert(0 && "Can't load this register from stack slot");
115 /// InsertBranch - Insert a branch into the end of the specified
116 /// MachineBasicBlock. This operands to this method are the same as those
117 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
118 /// returns success and when an unconditional branch (TBB is non-null, FBB is
119 /// null, Cond is empty) needs to be inserted. It returns the number of
120 /// instructions inserted.
121 unsigned PIC16InstrInfo::
122 InsertBranch(MachineBasicBlock &MBB,
123 MachineBasicBlock *TBB, MachineBasicBlock *FBB,
124 const SmallVectorImpl<MachineOperand> &Cond) const
126 // Shouldn't be a fall through.
127 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
129 if (FBB == 0) { // One way branch.
131 // Unconditional branch?
132 BuildMI(&MBB, get(PIC16::GOTO)).addMBB(TBB);
137 // FIXME: If the there are some conditions specified then conditional branch
138 // should be generated.
139 // For the time being no instruction is being generated therefore