1 //===- PIC16InstrInfo.cpp - PIC16 Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PIC16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "PIC16InstrInfo.h"
16 #include "PIC16TargetMachine.h"
17 #include "PIC16GenInstrInfo.inc"
18 #include "llvm/Function.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 // FIXME: Add the subtarget support on this constructor.
29 PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
30 : TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
32 RegInfo(*this, *TM.getSubtargetImpl()) {}
35 /// isStoreToStackSlot - If the specified machine instruction is a direct
36 /// store to a stack slot, return the virtual or physical register number of
37 /// the source reg along with the FrameIndex of the loaded stack slot.
38 /// If not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than storing to the stack slot.
40 unsigned PIC16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
41 int &FrameIndex) const {
42 if (MI->getOpcode() == PIC16::movwf
43 && MI->getOperand(0).isReg()
44 && MI->getOperand(1).isSymbol()) {
45 FrameIndex = MI->getOperand(1).getIndex();
46 return MI->getOperand(0).getReg();
51 /// isLoadFromStackSlot - If the specified machine instruction is a direct
52 /// load from a stack slot, return the virtual or physical register number of
53 /// the dest reg along with the FrameIndex of the stack slot.
54 /// If not, return 0. This predicate must return 0 if the instruction has
55 /// any side effects other than storing to the stack slot.
56 unsigned PIC16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
57 int &FrameIndex) const {
58 if (MI->getOpcode() == PIC16::movf
59 && MI->getOperand(0).isReg()
60 && MI->getOperand(1).isSymbol()) {
61 FrameIndex = MI->getOperand(1).getIndex();
62 return MI->getOperand(0).getReg();
68 void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I,
70 unsigned SrcReg, bool isKill, int FI,
71 const TargetRegisterClass *RC) const {
72 PIC16TargetLowering *PTLI = TM.getTargetLowering();
73 DebugLoc DL = DebugLoc::getUnknownLoc();
74 if (I != MBB.end()) DL = I->getDebugLoc();
76 const Function *Func = MBB.getParent()->getFunction();
77 const std::string FuncName = Func->getName();
79 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
80 sprintf(tmpName, "%s.tmp", FuncName.c_str());
82 // On the order of operands here: think "movwf SrcReg, tmp_slot, offset".
83 if (RC == PIC16::GPRRegisterClass) {
84 //MachineFunction &MF = *MBB.getParent();
85 //MachineRegisterInfo &RI = MF.getRegInfo();
86 BuildMI(MBB, I, DL, get(PIC16::movwf))
87 .addReg(SrcReg, false, false, isKill)
88 .addImm(PTLI->GetTmpOffsetForFI(FI))
89 .addExternalSymbol(tmpName)
90 .addImm(1); // Emit banksel for it.
92 else if (RC == PIC16::FSR16RegisterClass)
93 assert(0 && "Don't know yet how to store a FSR16 to stack slot");
95 assert(0 && "Can't store this register to stack slot");
98 void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator I,
100 unsigned DestReg, int FI,
101 const TargetRegisterClass *RC) const {
102 PIC16TargetLowering *PTLI = TM.getTargetLowering();
103 DebugLoc DL = DebugLoc::getUnknownLoc();
104 if (I != MBB.end()) DL = I->getDebugLoc();
106 const Function *Func = MBB.getParent()->getFunction();
107 const std::string FuncName = Func->getName();
109 char *tmpName = new char [strlen(FuncName.c_str()) + 6];
110 sprintf(tmpName, "%s.tmp", FuncName.c_str());
112 // On the order of operands here: think "movf FrameIndex, W".
113 if (RC == PIC16::GPRRegisterClass) {
114 //MachineFunction &MF = *MBB.getParent();
115 //MachineRegisterInfo &RI = MF.getRegInfo();
116 BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
117 .addImm(PTLI->GetTmpOffsetForFI(FI))
118 .addExternalSymbol(tmpName)
119 .addImm(1); // Emit banksel for it.
121 else if (RC == PIC16::FSR16RegisterClass)
122 assert(0 && "Don't know yet how to load an FSR16 from stack slot");
124 assert(0 && "Can't load this register from stack slot");
127 bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB,
128 MachineBasicBlock::iterator I,
129 unsigned DestReg, unsigned SrcReg,
130 const TargetRegisterClass *DestRC,
131 const TargetRegisterClass *SrcRC) const {
132 DebugLoc DL = DebugLoc::getUnknownLoc();
133 if (I != MBB.end()) DL = I->getDebugLoc();
135 if (DestRC == PIC16::FSR16RegisterClass) {
136 BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg);
140 if (DestRC == PIC16::GPRRegisterClass) {
141 BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg);
145 // Not yet supported.
149 bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
150 unsigned &SrcReg, unsigned &DestReg,
151 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
152 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
154 if (MI.getOpcode() == PIC16::copy_fsr
155 || MI.getOpcode() == PIC16::copy_w) {
156 DestReg = MI.getOperand(0).getReg();
157 SrcReg = MI.getOperand(1).getReg();