1 //===- PIC16InstrInfo.h - PIC16 Instruction Information----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the niversity of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PIC16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef PIC16INSTRUCTIONINFO_H
15 #define PIC16INSTRUCTIONINFO_H
18 #include "PIC16RegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
24 class PIC16InstrInfo : public TargetInstrInfoImpl
26 PIC16TargetMachine &TM;
27 const PIC16RegisterInfo RI;
29 explicit PIC16InstrInfo(PIC16TargetMachine &TM);
31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32 /// such, whenever a client has an instance of instruction info, it should
33 /// always be able to get register info as well (through this method).
35 virtual const PIC16RegisterInfo &getRegisterInfo() const { return RI; }
38 /// isLoadFromStackSlot - If the specified machine instruction is a direct
39 /// load from a stack slot, return the virtual or physical register number of
40 /// the destination along with the FrameIndex of the loaded stack slot. If
41 /// not, return 0. This predicate must return 0 if the instruction has
42 /// any side effects other than loading from the stack slot.
43 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
45 /// isStoreToStackSlot - If the specified machine instruction is a direct
46 /// store to a stack slot, return the virtual or physical register number of
47 /// the source reg along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than storing to the stack slot.
50 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
52 /// Used for spilling a register
53 void storeRegToStackSlot(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MI,
55 unsigned SrcReg, bool isKill, int FrameIndex,
56 const TargetRegisterClass *RC) const;
59 void loadRegFromStackSlot(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MI,
61 unsigned DestReg, int FrameIndex,
62 const TargetRegisterClass *RC) const;
64 /// InsertBranch - Insert a branch into the end of the specified
65 /// MachineBasicBlock. This operands to this method are the same as those
66 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
67 /// returns success and when an unconditional branch (TBB is non-null, FBB is
68 /// null, Cond is empty) needs to be inserted. It returns the number of
69 /// instructions inserted.
70 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
71 MachineBasicBlock *FBB,
72 const std::vector<MachineOperand> &Cond) const ;