1 //===- PIC16InstrInfo.td - PIC16 Instruction defs -------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // PIC16 Specific Type Constraints.
16 //===----------------------------------------------------------------------===//
17 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
18 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
20 //===----------------------------------------------------------------------===//
21 // PIC16 Specific Type Profiles.
22 //===----------------------------------------------------------------------===//
24 // Generic type profiles for i8/i16 unary/binary operations.
25 // Taking one i8 or i16 and producing void.
26 def SDTI8VoidOp : SDTypeProfile<0, 1, [SDTCisI8<0>]>;
27 def SDTI16VoidOp : SDTypeProfile<0, 1, [SDTCisI16<0>]>;
29 // Taking one value and producing an output of same type.
30 def SDTI8UnaryOp : SDTypeProfile<1, 1, [SDTCisI8<0>, SDTCisI8<1>]>;
31 def SDTI16UnaryOp : SDTypeProfile<1, 1, [SDTCisI16<0>, SDTCisI16<1>]>;
33 // Taking two values and producing an output of same type.
34 def SDTI8BinOp : SDTypeProfile<1, 2, [SDTCisI8<0>, SDTCisI8<1>, SDTCisI8<2>]>;
35 def SDTI16BinOp : SDTypeProfile<1, 2, [SDTCisI16<0>, SDTCisI16<1>,
38 // Node specific type profiles.
39 def SDT_PIC16Load : SDTypeProfile<1, 3, [SDTCisI8<0>, SDTCisI8<1>,
40 SDTCisI8<2>, SDTCisI8<3>]>;
42 def SDT_PIC16Store : SDTypeProfile<0, 4, [SDTCisI8<0>, SDTCisI8<1>,
43 SDTCisI8<2>, SDTCisI8<3>]>;
45 // PIC16ISD::CALL type prorile
46 def SDT_PIC16call : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
49 def SDT_PIC16Brcond: SDTypeProfile<0, 2,
50 [SDTCisVT<0, OtherVT>, SDTCisI8<1>]>;
53 def SDT_PIC16Selecticc: SDTypeProfile<1, 3,
54 [SDTCisI8<0>, SDTCisI8<1>, SDTCisI8<2>,
57 //===----------------------------------------------------------------------===//
58 // PIC16 addressing modes matching via DAG.
59 //===----------------------------------------------------------------------===//
60 def diraddr : ComplexPattern<i8, 1, "SelectDirectAddr", [], []>;
62 //===----------------------------------------------------------------------===//
63 // PIC16 Specific Node Definitions.
64 //===----------------------------------------------------------------------===//
65 def PIC16callseq_start : SDNode<"ISD::CALLSEQ_START", SDTI8VoidOp,
66 [SDNPHasChain, SDNPOutFlag]>;
67 def PIC16callseq_end : SDNode<"ISD::CALLSEQ_END", SDTI8VoidOp,
68 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
70 // Low 8-bits of GlobalAddress.
71 def PIC16Lo : SDNode<"PIC16ISD::Lo", SDTI8UnaryOp>;
73 // High 8-bits of GlobalAddress.
74 def PIC16Hi : SDNode<"PIC16ISD::Hi", SDTI8UnaryOp>;
76 // The MTHI and MTLO nodes are used only to match them in the incoming
77 // DAG for replacement by corresponding set_fsrhi, set_fsrlo insntructions.
78 // These nodes are not used for defining any instructions.
79 def MTLO : SDNode<"PIC16ISD::MTLO", SDTI8UnaryOp>;
80 def MTHI : SDNode<"PIC16ISD::MTHI", SDTI8UnaryOp>;
82 // Node to generate Bank Select for a GlobalAddress.
83 def Banksel : SDNode<"PIC16ISD::Banksel", SDTI8UnaryOp>;
85 // Node to match a direct store operation.
86 def PIC16Store : SDNode<"PIC16ISD::PIC16Store", SDT_PIC16Store, [SDNPHasChain]>;
87 def PIC16StWF : SDNode<"PIC16ISD::PIC16StWF", SDT_PIC16Store,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
90 // Node to match a direct load operation.
91 def PIC16Load : SDNode<"PIC16ISD::PIC16Load", SDT_PIC16Load, [SDNPHasChain]>;
92 def PIC16LdWF : SDNode<"PIC16ISD::PIC16LdWF", SDT_PIC16Load,
93 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
95 // Node to match PIC16 call
96 def PIC16call : SDNode<"PIC16ISD::CALL", SDT_PIC16call,
97 [SDNPHasChain , SDNPOptInFlag, SDNPOutFlag]>;
99 // Node to match a comparison instruction.
100 def PIC16Subcc : SDNode<"PIC16ISD::SUBCC", SDTI8BinOp, [SDNPOutFlag]>;
102 // Node to match a conditional branch.
103 def PIC16Brcond : SDNode<"PIC16ISD::BRCOND", SDT_PIC16Brcond,
104 [SDNPHasChain, SDNPInFlag]>;
106 def PIC16Selecticc : SDNode<"PIC16ISD::SELECT_ICC", SDT_PIC16Selecticc,
109 //===----------------------------------------------------------------------===//
110 // PIC16 Operand Definitions.
111 //===----------------------------------------------------------------------===//
112 def i8mem : Operand<i8>;
113 def brtarget: Operand<OtherVT>;
115 // Operand for printing out a condition code.
116 let PrintMethod = "printCCOperand" in
117 def CCOp : Operand<i8>;
119 include "PIC16InstrFormats.td"
121 //===----------------------------------------------------------------------===//
122 // PIC16 Common Classes.
123 //===----------------------------------------------------------------------===//
125 // W = W Op F : Load the value from F and do Op to W.
126 class BinOpFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
127 ByteFormat<OpCode, (outs GPR:$dst),
128 (ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
129 !strconcat(OpcStr, " $ptrlo + $offset, W"),
130 [(set GPR:$dst, (OpNode GPR:$src, (PIC16Load diraddr:$ptrlo,
132 (i8 imm:$offset))))]>;
134 // F = F Op W : Load the value from F, do op with W and store in F.
135 class BinOpWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
136 ByteFormat<OpCode, (outs),
137 (ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
138 !strconcat(OpcStr, " $ptrlo + $offset"),
139 [(PIC16Store (OpNode GPR:$src, (PIC16Load diraddr:$ptrlo,
143 (i8 imm:$ptrhi), (i8 imm:$offset)
146 // W = W Op L : Do Op of L with W and place result in W.
147 class BinOpLW<bits<6> opcode, string OpcStr, SDNode OpNode> :
148 LiteralFormat<opcode, (outs GPR:$dst),
149 (ins GPR:$src, i8imm:$literal),
150 !strconcat(OpcStr, " $literal"),
151 [(set GPR:$dst, (OpNode GPR:$src, (i8 imm:$literal)))]>;
153 //===----------------------------------------------------------------------===//
154 // PIC16 Instructions.
155 //===----------------------------------------------------------------------===//
157 // Pseudo-instructions.
158 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i8imm:$amt),
159 "!ADJCALLSTACKDOWN $amt",
160 [(PIC16callseq_start imm:$amt)]>;
162 def ADJCALLSTACKUP : Pseudo<(outs), (ins i8imm:$amt),
163 "!ADJCALLSTACKUP $amt",
164 [(PIC16callseq_end imm:$amt)]>;
166 //-----------------------------------
167 // Vaious movlw insn patterns.
168 //-----------------------------------
169 let isReMaterializable = 1 in {
170 // Move 8-bit literal to W.
171 def movlw : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
173 [(set GPR:$dst, (i8 imm:$src))]>;
175 // Move a Lo(TGA) to W.
176 def movlw_lo : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
178 [(set GPR:$dst, (PIC16Lo tglobaladdr:$src))]>;
180 // Move a Hi(TGA) to W.
181 def movlw_hi : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
182 "movlw HIGH(${src})",
183 [(set GPR:$dst, (PIC16Hi tglobaladdr:$src))]>;
186 //-------------------
187 // FSR setting insns.
188 //-------------------
189 // These insns are matched via a DAG replacement pattern.
191 ByteFormat<0, (outs FSR16:$fsr),
196 let isTwoAddress = 1 in
198 ByteFormat<0, (outs FSR16:$dst),
199 (ins FSR16:$src, GPR:$val),
204 Pseudo<(outs FSR16:$dst), (ins FSR16:$src), "copy_fsr $dst, $src", []>;
207 Pseudo<(outs GPR:$dst), (ins GPR:$src), "copy_w $dst, $src", []>;
209 //--------------------------
211 //-------------------------
214 ByteFormat<0, (outs),
215 (ins GPR:$val, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
216 "movwf ${ptrlo} + ${offset}",
217 [(PIC16Store GPR:$val, tglobaladdr:$ptrlo, (i8 imm:$ptrhi),
221 ByteFormat<0, (outs),
222 (ins GPR:$val, i8mem:$ptrlo, i8imm:$ptrhi, i8imm:$offset),
223 "movwf ${ptrlo} + ${offset}",
224 [(PIC16Store GPR:$val, texternalsym:$ptrlo, (i8 imm:$ptrhi),
227 // Store with InFlag and OutFlag
229 ByteFormat<0, (outs),
230 (ins GPR:$val, i8mem:$ptrlo, i8imm:$ptrhi, i8imm:$offset),
231 "movwf ${ptrlo} + ${offset}",
232 [(PIC16StWF GPR:$val, texternalsym:$ptrlo, (i8 imm:$ptrhi),
235 // Indirect store. Matched via a DAG replacement pattern.
237 ByteFormat<0, (outs),
238 (ins GPR:$val, FSR16:$fsr, i8imm:$offset),
239 "movwi $offset[$fsr]",
242 //----------------------------
244 //----------------------------
247 ByteFormat<0, (outs GPR:$dst),
248 (ins i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
249 "movf ${ptrlo} + ${offset}, W",
251 (PIC16Load tglobaladdr:$ptrlo, (i8 imm:$ptrhi),
252 (i8 imm:$offset)))]>;
255 ByteFormat<0, (outs GPR:$dst),
256 (ins i8mem:$ptrlo, i8imm:$ptrhi, i8imm:$offset),
257 "movf ${ptrlo} + ${offset}, W",
259 (PIC16Load texternalsym:$ptrlo, (i8 imm:$ptrhi),
260 (i8 imm:$offset)))]>;
262 // Load with InFlag and OutFlag
264 ByteFormat<0, (outs GPR:$dst),
265 (ins i8mem:$ptrlo, i8imm:$ptrhi, i8imm:$offset),
266 "movf ${ptrlo} + ${offset}, W",
268 (PIC16LdWF texternalsym:$ptrlo, (i8 imm:$ptrhi),
269 (i8 imm:$offset)))]>;
272 // Indirect load. Matched via a DAG replacement pattern.
274 ByteFormat<0, (outs GPR:$dst),
275 (ins FSR16:$fsr, i8imm:$offset),
276 "moviw $offset[$fsr]",
279 //-------------------------
280 // Bitwise operations patterns
281 //--------------------------
282 let isTwoAddress = 1 in {
283 def OrFW : BinOpFW<0, "iorwf", or>;
284 def XOrFW : BinOpFW<0, "xorwf", xor>;
285 def AndFW : BinOpFW<0, "andwf", and>;
288 def OrWF : BinOpWF<0, "iorwf", or>;
289 def XOrWF : BinOpWF<0, "xorwf", xor>;
290 def AndWF : BinOpWF<0, "andwf", and>;
292 //-------------------------
293 // Various add/sub patterns.
294 //-------------------------
296 let isTwoAddress = 1 in {
297 def addfw_1: BinOpFW<0, "addwf", add>;
298 def addfw_2: BinOpFW<0, "addwf", addc>;
299 def addfwc: BinOpFW<0, "addwfc", adde>; // With Carry.
302 def addwf_1: BinOpWF<0, "addwf", add>;
303 def addwf_2: BinOpWF<0, "addwf", addc>;
304 def addwfc: BinOpWF<0, "addwfc", adde>; // With Carry.
306 // W -= [F] ; load from F and sub the value from W.
307 class SUBFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
308 ByteFormat<OpCode, (outs GPR:$dst),
309 (ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
310 !strconcat(OpcStr, " $ptrlo + $offset, W"),
311 [(set GPR:$dst, (OpNode (PIC16Load diraddr:$ptrlo,
312 (i8 imm:$ptrhi), (i8 imm:$offset)),
314 let isTwoAddress = 1 in {
315 def subfw_1: SUBFW<0, "subwf", sub>;
316 def subfw_2: SUBFW<0, "subwf", subc>;
317 def subfwb: SUBFW<0, "subwfb", sube>; // With Borrow.
318 def subfw_cc: SUBFW<0, "subwf", PIC16Subcc>;
322 class SUBWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
323 ByteFormat<OpCode, (outs),
324 (ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
325 !strconcat(OpcStr, " $ptrlo + $offset"),
326 [(PIC16Store (OpNode (PIC16Load diraddr:$ptrlo,
327 (i8 imm:$ptrhi), (i8 imm:$offset)),
328 GPR:$src), diraddr:$ptrlo,
329 (i8 imm:$ptrhi), (i8 imm:$offset))]>;
331 def subwf_1: SUBWF<0, "subwf", sub>;
332 def subwf_2: SUBWF<0, "subwf", subc>;
333 def subwfb: SUBWF<0, "subwfb", sube>; // With Borrow.
334 def subwf_cc: SUBWF<0, "subwf", PIC16Subcc>;
337 let isTwoAddress = 1 in {
338 def addlw_1 : BinOpLW<0, "addlw", add>;
339 def addlw_2 : BinOpLW<0, "addlw", addc>;
340 def addlwc : BinOpLW<0, "addlwc", adde>; // With Carry. (Assembler macro).
343 // bitwise operations involving a literal and w.
344 let isTwoAddress = 1 in {
345 def andlw : BinOpLW<0, "andlw", and>;
346 def xorlw : BinOpLW<0, "xorlw", xor>;
347 def orlw : BinOpLW<0, "iorlw", or>;
351 // W = C - W ; sub W from literal. (Without borrow).
352 class SUBLW<bits<6> opcode, SDNode OpNode> :
353 LiteralFormat<opcode, (outs GPR:$dst),
354 (ins GPR:$src, i8imm:$literal),
356 [(set GPR:$dst, (OpNode (i8 imm:$literal), GPR:$src))]>;
358 let isTwoAddress = 1 in {
359 def sublw_1 : SUBLW<0, sub>;
360 def sublw_2 : SUBLW<0, subc>;
361 def sublw_cc : SUBLW<0, PIC16Subcc>;
366 def CALL: LiteralFormat<0x1, (outs), (ins i8imm:$func),
368 [(PIC16call diraddr:$func)]>;
371 def pic16brcond: ControlFormat<0x0, (outs), (ins brtarget:$dst, CCOp:$cc),
373 [(PIC16Brcond bb:$dst, imm:$cc)]>;
375 // Unconditional branch.
376 def br_uncond: ControlFormat<0x0, (outs), (ins brtarget:$dst),
380 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
381 // scheduler into a branch sequence.
382 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
383 def SELECT_CC_Int_ICC
384 : Pseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, i8imm:$Cond),
385 "; SELECT_CC_Int_ICC PSEUDO!",
386 [(set GPR:$dst, (PIC16Selecticc GPR:$T, GPR:$F,
392 let isReMaterializable = 1 in {
394 Pseudo<(outs BSR:$dst),
397 [(set BSR:$dst, (Banksel tglobaladdr:$ptr))]>;
402 ControlFormat<0, (outs), (ins), "return", [(ret)]>;
404 //===----------------------------------------------------------------------===//
405 // PIC16 Replacment Patterns.
406 //===----------------------------------------------------------------------===//
408 // Identify an indirect store and select insns for it.
409 def : Pat<(PIC16Store GPR:$val, (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
411 (store_indirect GPR:$val,
412 (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
415 // Identify an indirect load and select insns for it.
416 def : Pat<(PIC16Load (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
418 (load_indirect (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),