1 //===- PIC16RegisterInfo.td - PIC16 Register defs ------------*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the PIC16 register file
12 //===----------------------------------------------------------------------===//
14 // We have banks of 32 registers each.
15 class PIC16Reg<string n> : Register<n> {
17 let Namespace = "PIC16";
20 // PIC16 CPU Registers
21 class PIC16GPRReg<bits<5> num, string n> : PIC16Reg<n> {
26 def FSR0 : PIC16GPRReg< 0, "FSR0">, DwarfRegNum<[0]>;
27 def FSR1 : PIC16GPRReg< 1, "FSR1">, DwarfRegNum<[1]>;
29 // CPU Registers Class
30 def PTRRegs : RegisterClass<"PIC16", [i16], 8,
34 iterator allocation_order_end(const MachineFunction &MF) const;
37 PTRRegsClass::iterator
38 PTRRegsClass::allocation_order_end(const MachineFunction &MF) const {
44 def WREG : PIC16GPRReg< 0, "WREG">, DwarfRegNum<[0]>;
46 // CPU Registers Class
47 def CPURegs : RegisterClass<"PIC16", [i8], 8,
51 iterator allocation_order_end(const MachineFunction &MF) const;
54 CPURegsClass::iterator
55 CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
61 def STATUSREG : PIC16GPRReg<2, "STATUS">, DwarfRegNum<[0]>;
63 // STATUS Registers Class
64 def STATUSRegs : RegisterClass<"PIC16", [i8], 8,
68 // Dummy stack pointer.
69 def STKPTR : PIC16GPRReg< 0, "SP">, DwarfRegNum<[0]>;
71 // CPU Registers Class
72 def STKRegs : RegisterClass<"PIC16", [i8], 8,
76 iterator allocation_order_end(const MachineFunction &MF) const;
79 STKRegsClass::iterator
80 STKRegsClass::allocation_order_end(const MachineFunction &MF) const {