1 //===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PTXTargetLowering class.
12 //===----------------------------------------------------------------------===//
15 #include "PTXISelLowering.h"
16 #include "PTXMachineFunctionInfo.h"
17 #include "PTXRegisterInfo.h"
18 #include "PTXSubtarget.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/Support/raw_ostream.h"
29 //===----------------------------------------------------------------------===//
30 // Calling Convention Implementation
31 //===----------------------------------------------------------------------===//
33 #include "PTXGenCallingConv.inc"
35 //===----------------------------------------------------------------------===//
36 // TargetLowering Implementation
37 //===----------------------------------------------------------------------===//
39 PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
40 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
41 // Set up the register classes.
42 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
43 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
44 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
45 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
46 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
47 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
49 setBooleanContents(ZeroOrOneBooleanContent);
51 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
53 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
54 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
56 // Turn i16 (z)extload into load + (z)extend
57 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
58 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
60 // Turn f32 extload into load + fextend
61 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
63 // Turn f64 truncstore into trunc + store.
64 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
66 // Customize translation of memory addresses
67 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
68 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
70 // Expand BR_CC into BRCOND
71 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
73 // Expand SELECT_CC into SETCC
74 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
75 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
76 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
78 // need to lower SETCC of RegPred into bitwise logic
79 setOperationAction(ISD::SETCC, MVT::i1, Custom);
81 setMinFunctionAlignment(2);
83 // Compute derived properties from the register classes
84 computeRegisterProperties();
87 MVT::SimpleValueType PTXTargetLowering::getSetCCResultType(EVT VT) const {
91 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
92 switch (Op.getOpcode()) {
94 llvm_unreachable("Unimplemented operand");
96 return LowerSETCC(Op, DAG);
97 case ISD::GlobalAddress:
98 return LowerGlobalAddress(Op, DAG);
102 const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
105 llvm_unreachable("Unknown opcode");
106 case PTXISD::COPY_ADDRESS:
107 return "PTXISD::COPY_ADDRESS";
108 case PTXISD::LOAD_PARAM:
109 return "PTXISD::LOAD_PARAM";
110 case PTXISD::STORE_PARAM:
111 return "PTXISD::STORE_PARAM";
113 return "PTXISD::EXIT";
115 return "PTXISD::RET";
119 //===----------------------------------------------------------------------===//
120 // Custom Lower Operation
121 //===----------------------------------------------------------------------===//
123 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
124 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
125 SDValue Op0 = Op.getOperand(0);
126 SDValue Op1 = Op.getOperand(1);
127 SDValue Op2 = Op.getOperand(2);
128 DebugLoc dl = Op.getDebugLoc();
129 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
131 // Look for X == 0, X == 1, X != 0, or X != 1
132 // We can simplify these to bitwise logic
134 if (Op1.getOpcode() == ISD::Constant &&
135 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
136 cast<ConstantSDNode>(Op1)->isNullValue()) &&
137 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
139 return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
142 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
145 SDValue PTXTargetLowering::
146 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
147 EVT PtrVT = getPointerTy();
148 DebugLoc dl = Op.getDebugLoc();
149 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
151 assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
153 SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
154 SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
162 //===----------------------------------------------------------------------===//
163 // Calling Convention Implementation
164 //===----------------------------------------------------------------------===//
167 struct argmap_entry {
168 MVT::SimpleValueType VT;
169 TargetRegisterClass *RC;
170 TargetRegisterClass::iterator loc;
172 argmap_entry(MVT::SimpleValueType _VT, TargetRegisterClass *_RC)
173 : VT(_VT), RC(_RC), loc(_RC->begin()) {}
175 void reset() { loc = RC->begin(); }
176 bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
178 argmap_entry(MVT::i1, PTX::RegPredRegisterClass),
179 argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
180 argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
181 argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
182 argmap_entry(MVT::f32, PTX::RegF32RegisterClass),
183 argmap_entry(MVT::f64, PTX::RegF64RegisterClass)
185 } // end anonymous namespace
187 SDValue PTXTargetLowering::
188 LowerFormalArguments(SDValue Chain,
189 CallingConv::ID CallConv,
191 const SmallVectorImpl<ISD::InputArg> &Ins,
194 SmallVectorImpl<SDValue> &InVals) const {
195 if (isVarArg) llvm_unreachable("PTX does not support varargs");
197 MachineFunction &MF = DAG.getMachineFunction();
198 const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
199 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
203 llvm_unreachable("Unsupported calling convention");
205 case CallingConv::PTX_Kernel:
206 MFI->setKernel(true);
208 case CallingConv::PTX_Device:
209 MFI->setKernel(false);
213 // We do one of two things here:
214 // IsKernel || SM >= 2.0 -> Use param space for arguments
215 // SM < 2.0 -> Use registers for arguments
217 if (MFI->isKernel() || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
218 // We just need to emit the proper LOAD_PARAM ISDs
219 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
221 assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
222 "Kernels cannot take pred operands");
224 SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
225 DAG.getTargetConstant(i, MVT::i32));
226 InVals.push_back(ArgValue);
228 // Instead of storing a physical register in our argument list, we just
229 // store the total size of the parameter, in bits. The ASM printer
230 // knows how to process this.
231 MFI->addArgReg(Ins[i].VT.getStoreSizeInBits());
235 // For device functions, we use the PTX calling convention to do register
236 // assignments then create CopyFromReg ISDs for the allocated registers
238 SmallVector<CCValAssign, 16> ArgLocs;
239 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), ArgLocs,
242 CCInfo.AnalyzeFormalArguments(Ins, CC_PTX);
244 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
246 CCValAssign& VA = ArgLocs[i];
247 EVT RegVT = VA.getLocVT();
248 TargetRegisterClass* TRC = 0;
250 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
252 // Determine which register class we need
253 if (RegVT == MVT::i1) {
254 TRC = PTX::RegPredRegisterClass;
256 else if (RegVT == MVT::i16) {
257 TRC = PTX::RegI16RegisterClass;
259 else if (RegVT == MVT::i32) {
260 TRC = PTX::RegI32RegisterClass;
262 else if (RegVT == MVT::i64) {
263 TRC = PTX::RegI64RegisterClass;
265 else if (RegVT == MVT::f32) {
266 TRC = PTX::RegF32RegisterClass;
268 else if (RegVT == MVT::f64) {
269 TRC = PTX::RegF64RegisterClass;
272 llvm_unreachable("Unknown parameter type");
275 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
276 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
278 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
279 InVals.push_back(ArgValue);
281 MFI->addArgReg(VA.getLocReg());
288 SDValue PTXTargetLowering::
289 LowerReturn(SDValue Chain,
290 CallingConv::ID CallConv,
292 const SmallVectorImpl<ISD::OutputArg> &Outs,
293 const SmallVectorImpl<SDValue> &OutVals,
295 SelectionDAG &DAG) const {
296 if (isVarArg) llvm_unreachable("PTX does not support varargs");
300 llvm_unreachable("Unsupported calling convention.");
301 case CallingConv::PTX_Kernel:
302 assert(Outs.size() == 0 && "Kernel must return void.");
303 return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
304 case CallingConv::PTX_Device:
305 //assert(Outs.size() <= 1 && "Can at most return one value.");
309 MachineFunction& MF = DAG.getMachineFunction();
310 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
311 const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
315 if (ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
316 // For SM 2.0+, we return arguments in the param space
317 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
318 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
319 SDValue ParamIndex = DAG.getTargetConstant(i, MVT::i32);
320 SDValue Ops[] = { Chain, ParamIndex, OutVals[i], Flag };
321 Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, VTs, Ops,
322 Flag.getNode() ? 4 : 3);
323 Flag = Chain.getValue(1);
324 // Instead of storing a physical register in our argument list, we just
325 // store the total size of the parameter, in bits. The ASM printer
326 // knows how to process this.
327 MFI->addRetReg(Outs[i].VT.getStoreSizeInBits());
330 // For SM < 2.0, we return arguments in registers
331 SmallVector<CCValAssign, 16> RVLocs;
332 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
333 getTargetMachine(), RVLocs, *DAG.getContext());
335 CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
337 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
338 CCValAssign& VA = RVLocs[i];
340 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
342 unsigned Reg = VA.getLocReg();
344 DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
346 Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
348 // Guarantee that all emitted copies are stuck together,
349 // avoiding something bad
350 Flag = Chain.getValue(1);
356 if (Flag.getNode() == 0) {
357 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
360 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);