1 //===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PTXTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PTXISelLowering.h"
16 #include "PTXMachineFunctionInfo.h"
17 #include "PTXRegisterInfo.h"
18 #include "PTXSubtarget.h"
19 #include "llvm/Function.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
32 //===----------------------------------------------------------------------===//
33 // TargetLowering Implementation
34 //===----------------------------------------------------------------------===//
36 PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
37 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
38 // Set up the register classes.
39 addRegisterClass(MVT::i1, &PTX::RegPredRegClass);
40 addRegisterClass(MVT::i16, &PTX::RegI16RegClass);
41 addRegisterClass(MVT::i32, &PTX::RegI32RegClass);
42 addRegisterClass(MVT::i64, &PTX::RegI64RegClass);
43 addRegisterClass(MVT::f32, &PTX::RegF32RegClass);
44 addRegisterClass(MVT::f64, &PTX::RegF64RegClass);
46 setBooleanContents(ZeroOrOneBooleanContent);
47 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
48 setMinFunctionAlignment(2);
50 // Let LLVM use loads/stores for all mem* operations
51 maxStoresPerMemcpy = 4096;
52 maxStoresPerMemmove = 4096;
53 maxStoresPerMemset = 4096;
55 ////////////////////////////////////
56 /////////// Expansion //////////////
57 ////////////////////////////////////
59 // (any/zero/sign) extload => load + (any/zero/sign) extend
61 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
62 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
63 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
65 // f32 extload => load + fextend
67 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
69 // f64 truncstore => trunc + store
71 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
73 // sign_extend_inreg => sign_extend
75 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
79 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
83 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
84 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
85 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
87 ////////////////////////////////////
88 //////////// Legal /////////////////
89 ////////////////////////////////////
91 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
92 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
94 ////////////////////////////////////
95 //////////// Custom ////////////////
96 ////////////////////////////////////
98 // customise setcc to use bitwise logic if possible
100 //setOperationAction(ISD::SETCC, MVT::i1, Custom);
101 setOperationAction(ISD::SETCC, MVT::i1, Legal);
103 // customize translation of memory addresses
105 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
106 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
108 // Compute derived properties from the register classes
109 computeRegisterProperties();
112 EVT PTXTargetLowering::getSetCCResultType(EVT VT) const {
116 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
117 switch (Op.getOpcode()) {
119 llvm_unreachable("Unimplemented operand");
121 return LowerSETCC(Op, DAG);
122 case ISD::GlobalAddress:
123 return LowerGlobalAddress(Op, DAG);
127 const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
130 llvm_unreachable("Unknown opcode");
131 case PTXISD::COPY_ADDRESS:
132 return "PTXISD::COPY_ADDRESS";
133 case PTXISD::LOAD_PARAM:
134 return "PTXISD::LOAD_PARAM";
135 case PTXISD::STORE_PARAM:
136 return "PTXISD::STORE_PARAM";
137 case PTXISD::READ_PARAM:
138 return "PTXISD::READ_PARAM";
139 case PTXISD::WRITE_PARAM:
140 return "PTXISD::WRITE_PARAM";
142 return "PTXISD::EXIT";
144 return "PTXISD::RET";
146 return "PTXISD::CALL";
150 //===----------------------------------------------------------------------===//
151 // Custom Lower Operation
152 //===----------------------------------------------------------------------===//
154 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
155 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
156 SDValue Op0 = Op.getOperand(0);
157 SDValue Op1 = Op.getOperand(1);
158 SDValue Op2 = Op.getOperand(2);
159 DebugLoc dl = Op.getDebugLoc();
160 //ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
162 // Look for X == 0, X == 1, X != 0, or X != 1
163 // We can simplify these to bitwise logic
165 //if (Op1.getOpcode() == ISD::Constant &&
166 // (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
167 // cast<ConstantSDNode>(Op1)->isNullValue()) &&
168 // (CC == ISD::SETEQ || CC == ISD::SETNE)) {
170 // return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
173 //ConstantSDNode* COp1 = cast<ConstantSDNode>(Op1);
174 //if(COp1 && COp1->getZExtValue() == 1) {
175 // if(CC == ISD::SETNE) {
176 // return DAG.getNode(PTX::XORripreds, dl, MVT::i1, Op0);
180 llvm_unreachable("setcc was not matched by a pattern!");
182 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
185 SDValue PTXTargetLowering::
186 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
187 EVT PtrVT = getPointerTy();
188 DebugLoc dl = Op.getDebugLoc();
189 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
191 assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
193 SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
194 SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
202 //===----------------------------------------------------------------------===//
203 // Calling Convention Implementation
204 //===----------------------------------------------------------------------===//
206 SDValue PTXTargetLowering::
207 LowerFormalArguments(SDValue Chain,
208 CallingConv::ID CallConv,
210 const SmallVectorImpl<ISD::InputArg> &Ins,
213 SmallVectorImpl<SDValue> &InVals) const {
214 if (isVarArg) llvm_unreachable("PTX does not support varargs");
216 MachineFunction &MF = DAG.getMachineFunction();
217 const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
218 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
219 PTXParamManager &PM = MFI->getParamManager();
223 llvm_unreachable("Unsupported calling convention");
224 case CallingConv::PTX_Kernel:
225 MFI->setKernel(true);
227 case CallingConv::PTX_Device:
228 MFI->setKernel(false);
232 // We do one of two things here:
233 // IsKernel || SM >= 2.0 -> Use param space for arguments
234 // SM < 2.0 -> Use registers for arguments
235 if (MFI->isKernel() || ST.useParamSpaceForDeviceArgs()) {
236 // We just need to emit the proper LOAD_PARAM ISDs
237 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
238 assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
239 "Kernels cannot take pred operands");
241 unsigned ParamSize = Ins[i].VT.getStoreSizeInBits();
242 unsigned Param = PM.addArgumentParam(ParamSize);
243 const std::string &ParamName = PM.getParamName(Param);
244 SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(),
246 SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
248 InVals.push_back(ArgValue);
252 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
253 EVT RegVT = Ins[i].VT;
254 const TargetRegisterClass* TRC = getRegClassFor(RegVT);
257 // Determine which register class we need
258 if (RegVT == MVT::i1)
259 RegType = PTXRegisterType::Pred;
260 else if (RegVT == MVT::i16)
261 RegType = PTXRegisterType::B16;
262 else if (RegVT == MVT::i32)
263 RegType = PTXRegisterType::B32;
264 else if (RegVT == MVT::i64)
265 RegType = PTXRegisterType::B64;
266 else if (RegVT == MVT::f32)
267 RegType = PTXRegisterType::F32;
268 else if (RegVT == MVT::f64)
269 RegType = PTXRegisterType::F64;
271 llvm_unreachable("Unknown parameter type");
273 // Use a unique index in the instruction to prevent instruction folding.
274 // Yes, this is a hack.
275 SDValue Index = DAG.getTargetConstant(i, MVT::i32);
276 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
277 SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, RegVT, Chain,
280 InVals.push_back(ArgValue);
282 MFI->addRegister(Reg, RegType, PTXRegisterSpace::Argument);
289 SDValue PTXTargetLowering::
290 LowerReturn(SDValue Chain,
291 CallingConv::ID CallConv,
293 const SmallVectorImpl<ISD::OutputArg> &Outs,
294 const SmallVectorImpl<SDValue> &OutVals,
296 SelectionDAG &DAG) const {
297 if (isVarArg) llvm_unreachable("PTX does not support varargs");
301 llvm_unreachable("Unsupported calling convention.");
302 case CallingConv::PTX_Kernel:
303 assert(Outs.size() == 0 && "Kernel must return void.");
304 return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
305 case CallingConv::PTX_Device:
306 assert(Outs.size() <= 1 && "Can at most return one value.");
310 MachineFunction& MF = DAG.getMachineFunction();
311 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
312 PTXParamManager &PM = MFI->getParamManager();
315 const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
317 if (ST.useParamSpaceForDeviceArgs()) {
318 assert(Outs.size() < 2 && "Device functions can return at most one value");
320 if (Outs.size() == 1) {
321 unsigned ParamSize = OutVals[0].getValueType().getSizeInBits();
322 unsigned Param = PM.addReturnParam(ParamSize);
323 const std::string &ParamName = PM.getParamName(Param);
324 SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(),
326 Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain,
327 ParamValue, OutVals[0]);
330 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
331 EVT RegVT = Outs[i].VT;
332 const TargetRegisterClass* TRC;
335 // Determine which register class we need
336 if (RegVT == MVT::i1) {
337 TRC = &PTX::RegPredRegClass;
338 RegType = PTXRegisterType::Pred;
339 } else if (RegVT == MVT::i16) {
340 TRC = &PTX::RegI16RegClass;
341 RegType = PTXRegisterType::B16;
342 } else if (RegVT == MVT::i32) {
343 TRC = &PTX::RegI32RegClass;
344 RegType = PTXRegisterType::B32;
345 } else if (RegVT == MVT::i64) {
346 TRC = &PTX::RegI64RegClass;
347 RegType = PTXRegisterType::B64;
348 } else if (RegVT == MVT::f32) {
349 TRC = &PTX::RegF32RegClass;
350 RegType = PTXRegisterType::F32;
351 } else if (RegVT == MVT::f64) {
352 TRC = &PTX::RegF64RegClass;
353 RegType = PTXRegisterType::F64;
355 llvm_unreachable("Unknown parameter type");
358 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
360 SDValue Copy = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i]/*, Flag*/);
361 SDValue OutReg = DAG.getRegister(Reg, RegVT);
363 Chain = DAG.getNode(PTXISD::WRITE_PARAM, dl, MVT::Other, Copy, OutReg);
365 MFI->addRegister(Reg, RegType, PTXRegisterSpace::Return);
369 if (Flag.getNode() == 0) {
370 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
373 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
378 PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
379 CallingConv::ID CallConv, bool isVarArg,
380 bool doesNotRet, bool &isTailCall,
381 const SmallVectorImpl<ISD::OutputArg> &Outs,
382 const SmallVectorImpl<SDValue> &OutVals,
383 const SmallVectorImpl<ISD::InputArg> &Ins,
384 DebugLoc dl, SelectionDAG &DAG,
385 SmallVectorImpl<SDValue> &InVals) const {
387 MachineFunction& MF = DAG.getMachineFunction();
388 PTXMachineFunctionInfo *PTXMFI = MF.getInfo<PTXMachineFunctionInfo>();
389 PTXParamManager &PM = PTXMFI->getParamManager();
390 MachineFrameInfo *MFI = MF.getFrameInfo();
392 assert(getTargetMachine().getSubtarget<PTXSubtarget>().callsAreHandled() &&
393 "Calls are not handled for the target device");
395 // Identify the callee function
396 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
397 const Function *function = cast<Function>(GV);
399 // allow non-device calls only for printf
400 bool isPrintf = function->getName() == "printf" || function->getName() == "puts";
402 assert((isPrintf || function->getCallingConv() == CallingConv::PTX_Device) &&
403 "PTX function calls must be to PTX device functions");
405 unsigned outSize = isPrintf ? 2 : Outs.size();
407 std::vector<SDValue> Ops;
408 // The layout of the ops will be [Chain, #Ins, Ins, Callee, #Outs, Outs]
409 Ops.resize(outSize + Ins.size() + 4);
413 // Identify the callee function
414 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
415 Ops[Ins.size()+2] = Callee;
418 Ops[Ins.size()+3] = DAG.getTargetConstant(outSize, MVT::i32);
421 // first argument is the address of the global string variable in memory
422 unsigned Param0 = PM.addLocalParam(getPointerTy().getSizeInBits());
423 SDValue ParamValue0 = DAG.getTargetExternalSymbol(PM.getParamName(Param0).c_str(),
425 Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain,
426 ParamValue0, OutVals[0]);
427 Ops[Ins.size()+4] = ParamValue0;
429 // alignment is the maximum size of all the arguments
430 unsigned alignment = 0;
431 for (unsigned i = 1; i < OutVals.size(); ++i) {
432 alignment = std::max(alignment,
433 OutVals[i].getValueType().getSizeInBits());
436 // size is the alignment multiplied by the number of arguments
437 unsigned size = alignment * (OutVals.size() - 1);
439 // second argument is the address of the stack object (unless no arguments)
440 unsigned Param1 = PM.addLocalParam(getPointerTy().getSizeInBits());
441 SDValue ParamValue1 = DAG.getTargetExternalSymbol(PM.getParamName(Param1).c_str(),
443 Ops[Ins.size()+5] = ParamValue1;
447 // create a local stack object to store the arguments
448 unsigned StackObject = MFI->CreateStackObject(size / 8, alignment / 8, false);
449 SDValue FrameIndex = DAG.getFrameIndex(StackObject, getPointerTy());
451 // store each of the arguments to the stack in turn
452 for (unsigned int i = 1; i != OutVals.size(); i++) {
453 SDValue FrameAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FrameIndex, DAG.getTargetConstant((i - 1) * 8, getPointerTy()));
454 Chain = DAG.getStore(Chain, dl, OutVals[i], FrameAddr,
455 MachinePointerInfo(),
459 // copy the address of the local frame index to get the address in non-local space
460 SDValue genericAddr = DAG.getNode(PTXISD::COPY_ADDRESS, dl, getPointerTy(), FrameIndex);
462 // store this address in the second argument
463 Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain, ParamValue1, genericAddr);
468 // Generate STORE_PARAM nodes for each function argument. In PTX, function
469 // arguments are explicitly stored into .param variables and passed as
470 // arguments. There is no register/stack-based calling convention in PTX.
471 for (unsigned i = 0; i != OutVals.size(); ++i) {
472 unsigned Size = OutVals[i].getValueType().getSizeInBits();
473 unsigned Param = PM.addLocalParam(Size);
474 const std::string &ParamName = PM.getParamName(Param);
475 SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(),
477 Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain,
478 ParamValue, OutVals[i]);
479 Ops[i+Ins.size()+4] = ParamValue;
483 std::vector<SDValue> InParams;
485 // Generate list of .param variables to hold the return value(s).
486 Ops[1] = DAG.getTargetConstant(Ins.size(), MVT::i32);
487 for (unsigned i = 0; i < Ins.size(); ++i) {
488 unsigned Size = Ins[i].VT.getStoreSizeInBits();
489 unsigned Param = PM.addLocalParam(Size);
490 const std::string &ParamName = PM.getParamName(Param);
491 SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(),
493 Ops[i+2] = ParamValue;
494 InParams.push_back(ParamValue);
499 // Create the CALL node.
500 Chain = DAG.getNode(PTXISD::CALL, dl, MVT::Other, &Ops[0], Ops.size());
502 // Create the LOAD_PARAM nodes that retrieve the function return value(s).
503 for (unsigned i = 0; i < Ins.size(); ++i) {
504 SDValue Load = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
506 InVals.push_back(Load);
512 unsigned PTXTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT) {
513 // All arguments consist of one "register," regardless of the type.