1 //===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PTXTargetLowering class.
12 //===----------------------------------------------------------------------===//
15 #include "PTXISelLowering.h"
16 #include "PTXMachineFunctionInfo.h"
17 #include "PTXRegisterInfo.h"
18 #include "PTXSubtarget.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Calling Convention Implementation
32 //===----------------------------------------------------------------------===//
34 #include "PTXGenCallingConv.inc"
36 //===----------------------------------------------------------------------===//
37 // TargetLowering Implementation
38 //===----------------------------------------------------------------------===//
40 PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
41 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
42 // Set up the register classes.
43 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
44 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
45 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
46 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
47 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
48 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
50 setBooleanContents(ZeroOrOneBooleanContent);
51 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
52 setMinFunctionAlignment(2);
54 ////////////////////////////////////
55 /////////// Expansion //////////////
56 ////////////////////////////////////
58 // (any/zero/sign) extload => load + (any/zero/sign) extend
60 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
61 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
62 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
64 // f32 extload => load + fextend
66 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
68 // f64 truncstore => trunc + store
70 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
72 // sign_extend_inreg => sign_extend
74 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
78 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
82 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
83 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
84 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
86 ////////////////////////////////////
87 //////////// Legal /////////////////
88 ////////////////////////////////////
90 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
91 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
93 ////////////////////////////////////
94 //////////// Custom ////////////////
95 ////////////////////////////////////
97 // customise setcc to use bitwise logic if possible
99 setOperationAction(ISD::SETCC, MVT::i1, Custom);
101 // customize translation of memory addresses
103 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
104 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
106 // Compute derived properties from the register classes
107 computeRegisterProperties();
110 EVT PTXTargetLowering::getSetCCResultType(EVT VT) const {
114 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
115 switch (Op.getOpcode()) {
117 llvm_unreachable("Unimplemented operand");
119 return LowerSETCC(Op, DAG);
120 case ISD::GlobalAddress:
121 return LowerGlobalAddress(Op, DAG);
125 const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
128 llvm_unreachable("Unknown opcode");
129 case PTXISD::COPY_ADDRESS:
130 return "PTXISD::COPY_ADDRESS";
131 case PTXISD::LOAD_PARAM:
132 return "PTXISD::LOAD_PARAM";
133 case PTXISD::STORE_PARAM:
134 return "PTXISD::STORE_PARAM";
136 return "PTXISD::EXIT";
138 return "PTXISD::RET";
140 return "PTXISD::CALL";
144 //===----------------------------------------------------------------------===//
145 // Custom Lower Operation
146 //===----------------------------------------------------------------------===//
148 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
149 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
150 SDValue Op0 = Op.getOperand(0);
151 SDValue Op1 = Op.getOperand(1);
152 SDValue Op2 = Op.getOperand(2);
153 DebugLoc dl = Op.getDebugLoc();
154 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
156 // Look for X == 0, X == 1, X != 0, or X != 1
157 // We can simplify these to bitwise logic
159 if (Op1.getOpcode() == ISD::Constant &&
160 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
161 cast<ConstantSDNode>(Op1)->isNullValue()) &&
162 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
164 return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
167 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
170 SDValue PTXTargetLowering::
171 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
172 EVT PtrVT = getPointerTy();
173 DebugLoc dl = Op.getDebugLoc();
174 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
176 assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
178 SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
179 SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
187 //===----------------------------------------------------------------------===//
188 // Calling Convention Implementation
189 //===----------------------------------------------------------------------===//
191 SDValue PTXTargetLowering::
192 LowerFormalArguments(SDValue Chain,
193 CallingConv::ID CallConv,
195 const SmallVectorImpl<ISD::InputArg> &Ins,
198 SmallVectorImpl<SDValue> &InVals) const {
199 if (isVarArg) llvm_unreachable("PTX does not support varargs");
201 MachineFunction &MF = DAG.getMachineFunction();
202 const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
203 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
207 llvm_unreachable("Unsupported calling convention");
209 case CallingConv::PTX_Kernel:
210 MFI->setKernel(true);
212 case CallingConv::PTX_Device:
213 MFI->setKernel(false);
217 // We do one of two things here:
218 // IsKernel || SM >= 2.0 -> Use param space for arguments
219 // SM < 2.0 -> Use registers for arguments
220 if (MFI->isKernel() || ST.useParamSpaceForDeviceArgs()) {
221 // We just need to emit the proper LOAD_PARAM ISDs
222 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
224 assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
225 "Kernels cannot take pred operands");
227 SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
228 DAG.getTargetConstant(i, MVT::i32));
229 InVals.push_back(ArgValue);
231 // Instead of storing a physical register in our argument list, we just
232 // store the total size of the parameter, in bits. The ASM printer
233 // knows how to process this.
234 MFI->addArgReg(Ins[i].VT.getStoreSizeInBits());
238 // For device functions, we use the PTX calling convention to do register
239 // assignments then create CopyFromReg ISDs for the allocated registers
241 SmallVector<CCValAssign, 16> ArgLocs;
242 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), ArgLocs,
245 CCInfo.AnalyzeFormalArguments(Ins, CC_PTX);
247 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
249 CCValAssign& VA = ArgLocs[i];
250 EVT RegVT = VA.getLocVT();
251 TargetRegisterClass* TRC = 0;
253 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
255 // Determine which register class we need
256 if (RegVT == MVT::i1) {
257 TRC = PTX::RegPredRegisterClass;
259 else if (RegVT == MVT::i16) {
260 TRC = PTX::RegI16RegisterClass;
262 else if (RegVT == MVT::i32) {
263 TRC = PTX::RegI32RegisterClass;
265 else if (RegVT == MVT::i64) {
266 TRC = PTX::RegI64RegisterClass;
268 else if (RegVT == MVT::f32) {
269 TRC = PTX::RegF32RegisterClass;
271 else if (RegVT == MVT::f64) {
272 TRC = PTX::RegF64RegisterClass;
275 llvm_unreachable("Unknown parameter type");
278 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
279 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
281 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
282 InVals.push_back(ArgValue);
284 MFI->addArgReg(VA.getLocReg());
291 SDValue PTXTargetLowering::
292 LowerReturn(SDValue Chain,
293 CallingConv::ID CallConv,
295 const SmallVectorImpl<ISD::OutputArg> &Outs,
296 const SmallVectorImpl<SDValue> &OutVals,
298 SelectionDAG &DAG) const {
299 if (isVarArg) llvm_unreachable("PTX does not support varargs");
303 llvm_unreachable("Unsupported calling convention.");
304 case CallingConv::PTX_Kernel:
305 assert(Outs.size() == 0 && "Kernel must return void.");
306 return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
307 case CallingConv::PTX_Device:
308 //assert(Outs.size() <= 1 && "Can at most return one value.");
312 MachineFunction& MF = DAG.getMachineFunction();
313 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
317 // Even though we could use the .param space for return arguments for
318 // device functions if SM >= 2.0 and the number of return arguments is
319 // only 1, we just always use registers since this makes the codegen
321 SmallVector<CCValAssign, 16> RVLocs;
322 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
323 getTargetMachine(), RVLocs, *DAG.getContext());
325 CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
327 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
328 CCValAssign& VA = RVLocs[i];
330 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
332 unsigned Reg = VA.getLocReg();
334 DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
336 Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
338 // Guarantee that all emitted copies are stuck together,
339 // avoiding something bad
340 Flag = Chain.getValue(1);
345 if (Flag.getNode() == 0) {
346 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
349 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
354 PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
355 CallingConv::ID CallConv, bool isVarArg,
357 const SmallVectorImpl<ISD::OutputArg> &Outs,
358 const SmallVectorImpl<SDValue> &OutVals,
359 const SmallVectorImpl<ISD::InputArg> &Ins,
360 DebugLoc dl, SelectionDAG &DAG,
361 SmallVectorImpl<SDValue> &InVals) const {
363 MachineFunction& MF = DAG.getMachineFunction();
364 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
366 assert(getTargetMachine().getSubtarget<PTXSubtarget>().callsAreHandled() &&
367 "Calls are not handled for the target device");
369 // Is there a more "LLVM"-way to create a variable-length array of values?
370 SDValue* ops = new SDValue[OutVals.size() + 2];
374 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
375 const GlobalValue *GV = G->getGlobal();
376 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
379 assert(false && "Function must be a GlobalAddressSDNode");
382 for (unsigned i = 0; i != OutVals.size(); ++i) {
383 unsigned Size = OutVals[i].getValueType().getSizeInBits();
384 SDValue Index = DAG.getTargetConstant(MFI->getNextParam(Size), MVT::i32);
385 Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain,
392 Chain = DAG.getNode(PTXISD::CALL, dl, MVT::Other, ops, OutVals.size()+2);