1 //===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PTXTargetLowering class.
12 //===----------------------------------------------------------------------===//
15 #include "PTXISelLowering.h"
16 #include "PTXMachineFunctionInfo.h"
17 #include "PTXRegisterInfo.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/Support/raw_ostream.h"
27 PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
28 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
29 // Set up the register classes.
30 addRegisterClass(MVT::i1, PTX::PredsRegisterClass);
31 addRegisterClass(MVT::i16, PTX::RRegu16RegisterClass);
32 addRegisterClass(MVT::i32, PTX::RRegu32RegisterClass);
33 addRegisterClass(MVT::i64, PTX::RRegu64RegisterClass);
34 addRegisterClass(MVT::f32, PTX::RRegf32RegisterClass);
35 addRegisterClass(MVT::f64, PTX::RRegf64RegisterClass);
37 setBooleanContents(ZeroOrOneBooleanContent);
39 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
41 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
42 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
44 // Turn i16 (z)extload into load + (z)extend
45 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
46 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
48 // Turn f32 extload into load + fextend
49 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
51 // Turn f64 truncstore into trunc + store.
52 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
54 // Customize translation of memory addresses
55 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
56 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
58 // Expand BR_CC into BRCOND
59 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
61 // Expand SELECT_CC into SETCC
62 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
63 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
64 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
66 // need to lower SETCC of Preds into bitwise logic
67 setOperationAction(ISD::SETCC, MVT::i1, Custom);
69 setMinFunctionAlignment(2);
71 // Compute derived properties from the register classes
72 computeRegisterProperties();
75 MVT::SimpleValueType PTXTargetLowering::getSetCCResultType(EVT VT) const {
79 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
80 switch (Op.getOpcode()) {
82 llvm_unreachable("Unimplemented operand");
84 return LowerSETCC(Op, DAG);
85 case ISD::GlobalAddress:
86 return LowerGlobalAddress(Op, DAG);
90 const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
93 llvm_unreachable("Unknown opcode");
94 case PTXISD::COPY_ADDRESS:
95 return "PTXISD::COPY_ADDRESS";
96 case PTXISD::READ_PARAM:
97 return "PTXISD::READ_PARAM";
99 return "PTXISD::EXIT";
101 return "PTXISD::RET";
105 //===----------------------------------------------------------------------===//
106 // Custom Lower Operation
107 //===----------------------------------------------------------------------===//
109 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
110 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
111 SDValue Op0 = Op.getOperand(0);
112 SDValue Op1 = Op.getOperand(1);
113 SDValue Op2 = Op.getOperand(2);
114 DebugLoc dl = Op.getDebugLoc();
115 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
117 // Look for X == 0, X == 1, X != 0, or X != 1
118 // We can simplify these to bitwise logic
120 if (Op1.getOpcode() == ISD::Constant &&
121 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
122 cast<ConstantSDNode>(Op1)->isNullValue()) &&
123 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
125 return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
128 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
131 SDValue PTXTargetLowering::
132 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
133 EVT PtrVT = getPointerTy();
134 DebugLoc dl = Op.getDebugLoc();
135 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
137 assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
139 SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
140 SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
148 //===----------------------------------------------------------------------===//
149 // Calling Convention Implementation
150 //===----------------------------------------------------------------------===//
153 struct argmap_entry {
154 MVT::SimpleValueType VT;
155 TargetRegisterClass *RC;
156 TargetRegisterClass::iterator loc;
158 argmap_entry(MVT::SimpleValueType _VT, TargetRegisterClass *_RC)
159 : VT(_VT), RC(_RC), loc(_RC->begin()) {}
161 void reset() { loc = RC->begin(); }
162 bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
164 argmap_entry(MVT::i1, PTX::PredsRegisterClass),
165 argmap_entry(MVT::i16, PTX::RRegu16RegisterClass),
166 argmap_entry(MVT::i32, PTX::RRegu32RegisterClass),
167 argmap_entry(MVT::i64, PTX::RRegu64RegisterClass),
168 argmap_entry(MVT::f32, PTX::RRegf32RegisterClass),
169 argmap_entry(MVT::f64, PTX::RRegf64RegisterClass)
171 } // end anonymous namespace
173 SDValue PTXTargetLowering::
174 LowerFormalArguments(SDValue Chain,
175 CallingConv::ID CallConv,
177 const SmallVectorImpl<ISD::InputArg> &Ins,
180 SmallVectorImpl<SDValue> &InVals) const {
181 if (isVarArg) llvm_unreachable("PTX does not support varargs");
183 MachineFunction &MF = DAG.getMachineFunction();
184 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
188 llvm_unreachable("Unsupported calling convention");
190 case CallingConv::PTX_Kernel:
191 MFI->setKernel(true);
193 case CallingConv::PTX_Device:
194 MFI->setKernel(false);
198 // Make sure we don't add argument registers twice
199 if (MFI->isDoneAddArg())
200 llvm_unreachable("cannot add argument registers twice");
202 // Reset argmap before allocation
203 for (struct argmap_entry *i = argmap, *e = argmap + array_lengthof(argmap);
207 for (int i = 0, e = Ins.size(); i != e; ++ i) {
208 MVT::SimpleValueType VT = Ins[i].VT.SimpleTy;
210 struct argmap_entry *entry = std::find(argmap,
211 argmap + array_lengthof(argmap), VT);
212 if (entry == argmap + array_lengthof(argmap))
213 llvm_unreachable("Type of argument is not supported");
215 if (MFI->isKernel() && entry->RC == PTX::PredsRegisterClass)
216 llvm_unreachable("cannot pass preds to kernel");
218 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
220 unsigned preg = *++(entry->loc); // allocate start from register 1
221 unsigned vreg = RegInfo.createVirtualRegister(entry->RC);
222 RegInfo.addLiveIn(preg, vreg);
224 MFI->addArgReg(preg);
228 inval = DAG.getNode(PTXISD::READ_PARAM, dl, VT, Chain,
229 DAG.getTargetConstant(i, MVT::i32));
231 inval = DAG.getCopyFromReg(Chain, dl, vreg, VT);
232 InVals.push_back(inval);
240 SDValue PTXTargetLowering::
241 LowerReturn(SDValue Chain,
242 CallingConv::ID CallConv,
244 const SmallVectorImpl<ISD::OutputArg> &Outs,
245 const SmallVectorImpl<SDValue> &OutVals,
247 SelectionDAG &DAG) const {
248 if (isVarArg) llvm_unreachable("PTX does not support varargs");
252 llvm_unreachable("Unsupported calling convention.");
253 case CallingConv::PTX_Kernel:
254 assert(Outs.size() == 0 && "Kernel must return void.");
255 return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
256 case CallingConv::PTX_Device:
257 assert(Outs.size() <= 1 && "Can at most return one value.");
264 if (Outs.size() == 0)
265 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
270 if (Outs[0].VT == MVT::i16) {
273 else if (Outs[0].VT == MVT::i32) {
276 else if (Outs[0].VT == MVT::i64) {
279 else if (Outs[0].VT == MVT::f32) {
283 assert(Outs[0].VT == MVT::f64 && "Can return only basic types");
287 MachineFunction &MF = DAG.getMachineFunction();
288 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
291 // If this is the first return lowered for this function, add the regs to the
292 // liveout set for the function
293 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
294 DAG.getMachineFunction().getRegInfo().addLiveOut(reg);
296 // Copy the result values into the output registers
297 Chain = DAG.getCopyToReg(Chain, dl, reg, OutVals[0], Flag);
299 // Guarantee that all emitted copies are stuck together,
300 // avoiding something bad
301 Flag = Chain.getValue(1);
303 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);