1 //===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PTXTargetLowering class.
12 //===----------------------------------------------------------------------===//
15 #include "PTXISelLowering.h"
16 #include "PTXMachineFunctionInfo.h"
17 #include "PTXRegisterInfo.h"
18 #include "PTXSubtarget.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Calling Convention Implementation
32 //===----------------------------------------------------------------------===//
34 #include "PTXGenCallingConv.inc"
36 //===----------------------------------------------------------------------===//
37 // TargetLowering Implementation
38 //===----------------------------------------------------------------------===//
40 PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
41 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
42 // Set up the register classes.
43 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
44 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
45 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
46 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
47 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
48 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
50 setBooleanContents(ZeroOrOneBooleanContent);
51 setMinFunctionAlignment(2);
53 ////////////////////////////////////
54 /////////// Expansion //////////////
55 ////////////////////////////////////
57 // (any/zero/sign) extload => load + (any/zero/sign) extend
59 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
60 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
61 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
63 // f32 extload => load + fextend
65 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
67 // f64 truncstore => trunc + store
69 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
71 // sign_extend_inreg => sign_extend
73 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
77 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
81 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
82 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
83 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
85 ////////////////////////////////////
86 //////////// Legal /////////////////
87 ////////////////////////////////////
89 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
90 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
92 ////////////////////////////////////
93 //////////// Custom ////////////////
94 ////////////////////////////////////
96 // customise setcc to use bitwise logic if possible
98 setOperationAction(ISD::SETCC, MVT::i1, Custom);
100 // customize translation of memory addresses
102 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
103 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
105 // Compute derived properties from the register classes
106 computeRegisterProperties();
109 MVT::SimpleValueType PTXTargetLowering::getSetCCResultType(EVT VT) const {
113 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
114 switch (Op.getOpcode()) {
116 llvm_unreachable("Unimplemented operand");
118 return LowerSETCC(Op, DAG);
119 case ISD::GlobalAddress:
120 return LowerGlobalAddress(Op, DAG);
124 const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
127 llvm_unreachable("Unknown opcode");
128 case PTXISD::COPY_ADDRESS:
129 return "PTXISD::COPY_ADDRESS";
130 case PTXISD::LOAD_PARAM:
131 return "PTXISD::LOAD_PARAM";
132 case PTXISD::STORE_PARAM:
133 return "PTXISD::STORE_PARAM";
135 return "PTXISD::EXIT";
137 return "PTXISD::RET";
139 return "PTXISD::CALL";
143 //===----------------------------------------------------------------------===//
144 // Custom Lower Operation
145 //===----------------------------------------------------------------------===//
147 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
148 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
149 SDValue Op0 = Op.getOperand(0);
150 SDValue Op1 = Op.getOperand(1);
151 SDValue Op2 = Op.getOperand(2);
152 DebugLoc dl = Op.getDebugLoc();
153 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
155 // Look for X == 0, X == 1, X != 0, or X != 1
156 // We can simplify these to bitwise logic
158 if (Op1.getOpcode() == ISD::Constant &&
159 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
160 cast<ConstantSDNode>(Op1)->isNullValue()) &&
161 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
163 return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
169 SDValue PTXTargetLowering::
170 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
171 EVT PtrVT = getPointerTy();
172 DebugLoc dl = Op.getDebugLoc();
173 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
175 assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
177 SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
178 SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
186 //===----------------------------------------------------------------------===//
187 // Calling Convention Implementation
188 //===----------------------------------------------------------------------===//
190 SDValue PTXTargetLowering::
191 LowerFormalArguments(SDValue Chain,
192 CallingConv::ID CallConv,
194 const SmallVectorImpl<ISD::InputArg> &Ins,
197 SmallVectorImpl<SDValue> &InVals) const {
198 if (isVarArg) llvm_unreachable("PTX does not support varargs");
200 MachineFunction &MF = DAG.getMachineFunction();
201 const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
202 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
206 llvm_unreachable("Unsupported calling convention");
208 case CallingConv::PTX_Kernel:
209 MFI->setKernel(true);
211 case CallingConv::PTX_Device:
212 MFI->setKernel(false);
216 // We do one of two things here:
217 // IsKernel || SM >= 2.0 -> Use param space for arguments
218 // SM < 2.0 -> Use registers for arguments
219 if (MFI->isKernel() || ST.useParamSpaceForDeviceArgs()) {
220 // We just need to emit the proper LOAD_PARAM ISDs
221 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
223 assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
224 "Kernels cannot take pred operands");
226 SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
227 DAG.getTargetConstant(i, MVT::i32));
228 InVals.push_back(ArgValue);
230 // Instead of storing a physical register in our argument list, we just
231 // store the total size of the parameter, in bits. The ASM printer
232 // knows how to process this.
233 MFI->addArgReg(Ins[i].VT.getStoreSizeInBits());
237 // For device functions, we use the PTX calling convention to do register
238 // assignments then create CopyFromReg ISDs for the allocated registers
240 SmallVector<CCValAssign, 16> ArgLocs;
241 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), ArgLocs,
244 CCInfo.AnalyzeFormalArguments(Ins, CC_PTX);
246 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
248 CCValAssign& VA = ArgLocs[i];
249 EVT RegVT = VA.getLocVT();
250 TargetRegisterClass* TRC = 0;
252 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
254 // Determine which register class we need
255 if (RegVT == MVT::i1) {
256 TRC = PTX::RegPredRegisterClass;
258 else if (RegVT == MVT::i16) {
259 TRC = PTX::RegI16RegisterClass;
261 else if (RegVT == MVT::i32) {
262 TRC = PTX::RegI32RegisterClass;
264 else if (RegVT == MVT::i64) {
265 TRC = PTX::RegI64RegisterClass;
267 else if (RegVT == MVT::f32) {
268 TRC = PTX::RegF32RegisterClass;
270 else if (RegVT == MVT::f64) {
271 TRC = PTX::RegF64RegisterClass;
274 llvm_unreachable("Unknown parameter type");
277 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
278 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
280 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
281 InVals.push_back(ArgValue);
283 MFI->addArgReg(VA.getLocReg());
290 SDValue PTXTargetLowering::
291 LowerReturn(SDValue Chain,
292 CallingConv::ID CallConv,
294 const SmallVectorImpl<ISD::OutputArg> &Outs,
295 const SmallVectorImpl<SDValue> &OutVals,
297 SelectionDAG &DAG) const {
298 if (isVarArg) llvm_unreachable("PTX does not support varargs");
302 llvm_unreachable("Unsupported calling convention.");
303 case CallingConv::PTX_Kernel:
304 assert(Outs.size() == 0 && "Kernel must return void.");
305 return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
306 case CallingConv::PTX_Device:
307 //assert(Outs.size() <= 1 && "Can at most return one value.");
311 MachineFunction& MF = DAG.getMachineFunction();
312 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
316 // Even though we could use the .param space for return arguments for
317 // device functions if SM >= 2.0 and the number of return arguments is
318 // only 1, we just always use registers since this makes the codegen
320 SmallVector<CCValAssign, 16> RVLocs;
321 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
322 getTargetMachine(), RVLocs, *DAG.getContext());
324 CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
326 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
327 CCValAssign& VA = RVLocs[i];
329 assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
331 unsigned Reg = VA.getLocReg();
333 DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
335 Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
337 // Guarantee that all emitted copies are stuck together,
338 // avoiding something bad
339 Flag = Chain.getValue(1);
344 if (Flag.getNode() == 0) {
345 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
348 return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
353 PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
354 CallingConv::ID CallConv, bool isVarArg,
356 const SmallVectorImpl<ISD::OutputArg> &Outs,
357 const SmallVectorImpl<SDValue> &OutVals,
358 const SmallVectorImpl<ISD::InputArg> &Ins,
359 DebugLoc dl, SelectionDAG &DAG,
360 SmallVectorImpl<SDValue> &InVals) const {
362 MachineFunction& MF = DAG.getMachineFunction();
363 PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
365 assert(getTargetMachine().getSubtarget<PTXSubtarget>().callsAreHandled() &&
366 "Calls are not handled for the target device");
368 // Is there a more "LLVM"-way to create a variable-length array of values?
369 SDValue* ops = new SDValue[OutVals.size() + 2];
373 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
374 const GlobalValue *GV = G->getGlobal();
375 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
378 assert(false && "Function must be a GlobalAddressSDNode");
381 for (unsigned i = 0; i != OutVals.size(); ++i) {
382 unsigned Size = OutVals[i].getValueType().getSizeInBits();
383 SDValue Index = DAG.getTargetConstant(MFI->getNextParam(Size), MVT::i32);
384 Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain,
391 Chain = DAG.getNode(PTXISD::CALL, dl, MVT::Other, ops, OutVals.size()+2);