1 //===- PTXInstrInfo.cpp - PTX Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "PTXInstrInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "PTXGenInstrInfo.inc"
22 PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
23 : TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
24 RI(_TM, *this), TM(_TM) {}
26 static const struct map_entry {
27 const TargetRegisterClass *cls;
30 { &PTX::RRegu16RegClass, PTX::MOVU16rr },
31 { &PTX::RRegu32RegClass, PTX::MOVU32rr },
32 { &PTX::RRegu64RegClass, PTX::MOVU64rr },
33 { &PTX::RRegf32RegClass, PTX::MOVF32rr },
34 { &PTX::RRegf64RegClass, PTX::MOVF64rr },
35 { &PTX::PredsRegClass, PTX::MOVPREDrr }
38 void PTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator I, DebugLoc DL,
40 unsigned DstReg, unsigned SrcReg,
42 for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i) {
43 if (map[i].cls->contains(DstReg, SrcReg)) {
45 get(map[i].opcode), DstReg).addReg(SrcReg,
46 Getkillregstate(KillSrc));
51 llvm_unreachable("Impossible reg-to-reg copy");
54 bool PTXInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator I,
56 unsigned DstReg, unsigned SrcReg,
57 const TargetRegisterClass *DstRC,
58 const TargetRegisterClass *SrcRC,
63 for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i)
64 if (DstRC == map[i].cls) {
65 MachineInstr *MI = BuildMI(MBB, I, DL, get(map[i].opcode),
66 DstReg).addReg(SrcReg);
67 if (MI->findFirstPredOperandIdx() == -1) {
68 MI->addOperand(MachineOperand::CreateReg(0, false));
69 MI->addOperand(MachineOperand::CreateImm(/*IsInv=*/0));
77 bool PTXInstrInfo::isMoveInstr(const MachineInstr& MI,
78 unsigned &SrcReg, unsigned &DstReg,
79 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
80 switch (MI.getOpcode()) {
89 assert(MI.getNumOperands() >= 2 &&
90 MI.getOperand(0).isReg() && MI.getOperand(1).isReg() &&
91 "Invalid register-register move instruction");
92 SrcSubIdx = DstSubIdx = 0; // No sub-registers
93 DstReg = MI.getOperand(0).getReg();
94 SrcReg = MI.getOperand(1).getReg();