1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
28 // Shader Model Support
29 def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">;
30 def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">;
31 def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">;
32 def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
39 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
40 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
43 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
44 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
46 //===----------------------------------------------------------------------===//
47 // Instruction Pattern Stuff
48 //===----------------------------------------------------------------------===//
50 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
52 const PointerType *PT;
53 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
54 (PT = dyn_cast<PointerType>(Src->getType())))
55 return PT->getAddressSpace() == PTX::GLOBAL;
59 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
61 const PointerType *PT;
62 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
63 (PT = dyn_cast<PointerType>(Src->getType())))
64 return PT->getAddressSpace() == PTX::CONSTANT;
68 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
70 const PointerType *PT;
71 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
72 (PT = dyn_cast<PointerType>(Src->getType())))
73 return PT->getAddressSpace() == PTX::LOCAL;
77 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
79 const PointerType *PT;
80 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
81 (PT = dyn_cast<PointerType>(Src->getType())))
82 return PT->getAddressSpace() == PTX::PARAMETER;
86 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
88 const PointerType *PT;
89 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
90 (PT = dyn_cast<PointerType>(Src->getType())))
91 return PT->getAddressSpace() == PTX::SHARED;
96 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
98 const PointerType *PT;
99 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
100 (PT = dyn_cast<PointerType>(Src->getType())))
101 return PT->getAddressSpace() == PTX::GLOBAL;
106 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
108 const PointerType *PT;
109 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
110 (PT = dyn_cast<PointerType>(Src->getType())))
111 return PT->getAddressSpace() == PTX::LOCAL;
116 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
118 const PointerType *PT;
119 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
120 (PT = dyn_cast<PointerType>(Src->getType())))
121 return PT->getAddressSpace() == PTX::PARAMETER;
126 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
128 const PointerType *PT;
129 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
130 (PT = dyn_cast<PointerType>(Src->getType())))
131 return PT->getAddressSpace() == PTX::SHARED;
136 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
137 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
138 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
139 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
140 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
141 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
144 def MEMri32 : Operand<i32> {
145 let PrintMethod = "printMemOperand";
146 let MIOperandInfo = (ops RegI32, i32imm);
148 def MEMri64 : Operand<i64> {
149 let PrintMethod = "printMemOperand";
150 let MIOperandInfo = (ops RegI64, i64imm);
152 def MEMii32 : Operand<i32> {
153 let PrintMethod = "printMemOperand";
154 let MIOperandInfo = (ops i32imm, i32imm);
156 def MEMii64 : Operand<i64> {
157 let PrintMethod = "printMemOperand";
158 let MIOperandInfo = (ops i64imm, i64imm);
160 // The operand here does not correspond to an actual address, so we
161 // can use i32 in 64-bit address modes.
162 def MEMpi : Operand<i32> {
163 let PrintMethod = "printParamOperand";
164 let MIOperandInfo = (ops i32imm);
166 def MEMret : Operand<i32> {
167 let PrintMethod = "printReturnOperand";
168 let MIOperandInfo = (ops i32imm);
171 // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
172 // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
174 // def PTXcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PTXCallSeqStart,
175 // [SDNPHasChain, SDNPOutGlue]>;
176 // def PTXcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PTXCallSeqEnd,
177 // [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
179 def PTXcall : SDNode<"PTXISD::CALL", SDTNone,
180 [SDNPHasChain, SDNPVariadic, SDNPOptInGlue, SDNPOutGlue]>;
183 // Branch & call targets have OtherVT type.
184 def brtarget : Operand<OtherVT>;
185 def calltarget : Operand<i32>;
187 //===----------------------------------------------------------------------===//
188 // PTX Specific Node Definitions
189 //===----------------------------------------------------------------------===//
191 // PTX allow generic 3-reg shifts like shl r0, r1, r2
192 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
193 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
194 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
197 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
199 : SDNode<"PTXISD::RET", SDTNone,
200 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
202 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
204 // Load/store .param space
206 : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>,
207 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
209 : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>,
210 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
212 //===----------------------------------------------------------------------===//
213 // Instruction Class Templates
214 //===----------------------------------------------------------------------===//
216 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
217 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
218 def rr32 : InstPTX<(outs RegF32:$d),
220 !strconcat(opcstr, ".f32\t$d, $a"),
221 [(set RegF32:$d, (opnode RegF32:$a))]>;
222 def ri32 : InstPTX<(outs RegF32:$d),
224 !strconcat(opcstr, ".f32\t$d, $a"),
225 [(set RegF32:$d, (opnode fpimm:$a))]>;
226 def rr64 : InstPTX<(outs RegF64:$d),
228 !strconcat(opcstr, ".f64\t$d, $a"),
229 [(set RegF64:$d, (opnode RegF64:$a))]>;
230 def ri64 : InstPTX<(outs RegF64:$d),
232 !strconcat(opcstr, ".f64\t$d, $a"),
233 [(set RegF64:$d, (opnode fpimm:$a))]>;
236 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
237 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
238 def rr32 : InstPTX<(outs RegF32:$d),
239 (ins RegF32:$a, RegF32:$b),
240 !strconcat(opcstr, ".f32\t$d, $a, $b"),
241 [(set RegF32:$d, (opnode RegF32:$a, RegF32:$b))]>;
242 def ri32 : InstPTX<(outs RegF32:$d),
243 (ins RegF32:$a, f32imm:$b),
244 !strconcat(opcstr, ".f32\t$d, $a, $b"),
245 [(set RegF32:$d, (opnode RegF32:$a, fpimm:$b))]>;
246 def rr64 : InstPTX<(outs RegF64:$d),
247 (ins RegF64:$a, RegF64:$b),
248 !strconcat(opcstr, ".f64\t$d, $a, $b"),
249 [(set RegF64:$d, (opnode RegF64:$a, RegF64:$b))]>;
250 def ri64 : InstPTX<(outs RegF64:$d),
251 (ins RegF64:$a, f64imm:$b),
252 !strconcat(opcstr, ".f64\t$d, $a, $b"),
253 [(set RegF64:$d, (opnode RegF64:$a, fpimm:$b))]>;
256 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
257 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
258 def rrr32 : InstPTX<(outs RegF32:$d),
259 (ins RegF32:$a, RegF32:$b, RegF32:$c),
260 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
261 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
264 def rri32 : InstPTX<(outs RegF32:$d),
265 (ins RegF32:$a, RegF32:$b, f32imm:$c),
266 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
267 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
270 def rrr64 : InstPTX<(outs RegF64:$d),
271 (ins RegF64:$a, RegF64:$b, RegF64:$c),
272 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
273 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
276 def rri64 : InstPTX<(outs RegF64:$d),
277 (ins RegF64:$a, RegF64:$b, f64imm:$c),
278 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
279 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
284 multiclass INT3<string opcstr, SDNode opnode> {
285 def rr16 : InstPTX<(outs RegI16:$d),
286 (ins RegI16:$a, RegI16:$b),
287 !strconcat(opcstr, ".u16\t$d, $a, $b"),
288 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
289 def ri16 : InstPTX<(outs RegI16:$d),
290 (ins RegI16:$a, i16imm:$b),
291 !strconcat(opcstr, ".u16\t$d, $a, $b"),
292 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
293 def rr32 : InstPTX<(outs RegI32:$d),
294 (ins RegI32:$a, RegI32:$b),
295 !strconcat(opcstr, ".u32\t$d, $a, $b"),
296 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
297 def ri32 : InstPTX<(outs RegI32:$d),
298 (ins RegI32:$a, i32imm:$b),
299 !strconcat(opcstr, ".u32\t$d, $a, $b"),
300 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
301 def rr64 : InstPTX<(outs RegI64:$d),
302 (ins RegI64:$a, RegI64:$b),
303 !strconcat(opcstr, ".u64\t$d, $a, $b"),
304 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
305 def ri64 : InstPTX<(outs RegI64:$d),
306 (ins RegI64:$a, i64imm:$b),
307 !strconcat(opcstr, ".u64\t$d, $a, $b"),
308 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
311 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
312 def ripreds : InstPTX<(outs RegPred:$d),
313 (ins RegPred:$a, i1imm:$b),
314 !strconcat(opcstr, ".pred\t$d, $a, $b"),
315 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
316 def rrpreds : InstPTX<(outs RegPred:$d),
317 (ins RegPred:$a, RegPred:$b),
318 !strconcat(opcstr, ".pred\t$d, $a, $b"),
319 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
320 def rr16 : InstPTX<(outs RegI16:$d),
321 (ins RegI16:$a, RegI16:$b),
322 !strconcat(opcstr, ".b16\t$d, $a, $b"),
323 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
324 def ri16 : InstPTX<(outs RegI16:$d),
325 (ins RegI16:$a, i16imm:$b),
326 !strconcat(opcstr, ".b16\t$d, $a, $b"),
327 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
328 def rr32 : InstPTX<(outs RegI32:$d),
329 (ins RegI32:$a, RegI32:$b),
330 !strconcat(opcstr, ".b32\t$d, $a, $b"),
331 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
332 def ri32 : InstPTX<(outs RegI32:$d),
333 (ins RegI32:$a, i32imm:$b),
334 !strconcat(opcstr, ".b32\t$d, $a, $b"),
335 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
336 def rr64 : InstPTX<(outs RegI64:$d),
337 (ins RegI64:$a, RegI64:$b),
338 !strconcat(opcstr, ".b64\t$d, $a, $b"),
339 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
340 def ri64 : InstPTX<(outs RegI64:$d),
341 (ins RegI64:$a, i64imm:$b),
342 !strconcat(opcstr, ".b64\t$d, $a, $b"),
343 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
346 multiclass INT3ntnc<string opcstr, SDNode opnode> {
347 def rr16 : InstPTX<(outs RegI16:$d),
348 (ins RegI16:$a, RegI16:$b),
349 !strconcat(opcstr, "16\t$d, $a, $b"),
350 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
351 def rr32 : InstPTX<(outs RegI32:$d),
352 (ins RegI32:$a, RegI32:$b),
353 !strconcat(opcstr, "32\t$d, $a, $b"),
354 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
355 def rr64 : InstPTX<(outs RegI64:$d),
356 (ins RegI64:$a, RegI64:$b),
357 !strconcat(opcstr, "64\t$d, $a, $b"),
358 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
359 def ri16 : InstPTX<(outs RegI16:$d),
360 (ins RegI16:$a, i16imm:$b),
361 !strconcat(opcstr, "16\t$d, $a, $b"),
362 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
363 def ri32 : InstPTX<(outs RegI32:$d),
364 (ins RegI32:$a, i32imm:$b),
365 !strconcat(opcstr, "32\t$d, $a, $b"),
366 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
367 def ri64 : InstPTX<(outs RegI64:$d),
368 (ins RegI64:$a, i64imm:$b),
369 !strconcat(opcstr, "64\t$d, $a, $b"),
370 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
371 def ir16 : InstPTX<(outs RegI16:$d),
372 (ins i16imm:$a, RegI16:$b),
373 !strconcat(opcstr, "16\t$d, $a, $b"),
374 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
375 def ir32 : InstPTX<(outs RegI32:$d),
376 (ins i32imm:$a, RegI32:$b),
377 !strconcat(opcstr, "32\t$d, $a, $b"),
378 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
379 def ir64 : InstPTX<(outs RegI64:$d),
380 (ins i64imm:$a, RegI64:$b),
381 !strconcat(opcstr, "64\t$d, $a, $b"),
382 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
385 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
386 CondCode cmp, string cmpstr> {
387 // TODO support 5-operand format: p|q, a, b, c
390 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
391 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
392 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
394 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
395 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
396 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
399 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
400 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
401 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
403 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
404 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
405 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
407 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
408 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
409 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
411 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
412 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
413 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
415 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
416 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
417 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
419 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
420 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
421 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
424 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
425 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
426 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
428 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
429 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
430 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
432 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
433 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
434 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
436 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
437 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
438 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
440 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
441 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
442 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
444 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
445 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
446 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
449 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
450 CondCode ucmp, CondCode ocmp, string cmpstr> {
451 // TODO support 5-operand format: p|q, a, b, c
454 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
455 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
456 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
458 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
459 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
460 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
463 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
464 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
465 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
467 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
468 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
469 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
472 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
473 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
474 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
476 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
477 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
478 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
481 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
482 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
483 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
485 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
486 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
487 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
490 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
491 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
492 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
494 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
495 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
496 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
499 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
500 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
501 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
503 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
504 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
505 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
508 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
509 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
510 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
512 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
513 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
514 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
517 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
519 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
520 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
521 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
524 multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
525 def rr32 : InstPTX<(outs RC:$d),
527 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
528 [(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
529 def rr64 : InstPTX<(outs RC:$d),
531 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
532 [(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
533 def ri32 : InstPTX<(outs RC:$d),
535 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
536 [(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
537 def ri64 : InstPTX<(outs RC:$d),
539 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
540 [(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
541 def ii32 : InstPTX<(outs RC:$d),
543 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
544 [(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
545 def ii64 : InstPTX<(outs RC:$d),
547 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
548 [(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
551 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
552 defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
553 defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
554 defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
555 defm f32 : PTX_LD<opstr, ".f32", RegF32, pat_load>;
556 defm f64 : PTX_LD<opstr, ".f64", RegF64, pat_load>;
559 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
560 def rr32 : InstPTX<(outs),
561 (ins RC:$d, MEMri32:$a),
562 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
563 [(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
564 def rr64 : InstPTX<(outs),
565 (ins RC:$d, MEMri64:$a),
566 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
567 [(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
568 def ri32 : InstPTX<(outs),
569 (ins RC:$d, MEMri32:$a),
570 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
571 [(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
572 def ri64 : InstPTX<(outs),
573 (ins RC:$d, MEMri64:$a),
574 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
575 [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
576 def ii32 : InstPTX<(outs),
577 (ins RC:$d, MEMii32:$a),
578 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
579 [(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
580 def ii64 : InstPTX<(outs),
581 (ins RC:$d, MEMii64:$a),
582 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
583 [(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
586 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
587 defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
588 defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
589 defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
590 defm f32 : PTX_ST<opstr, ".f32", RegF32, pat_store>;
591 defm f64 : PTX_ST<opstr, ".f64", RegF64, pat_store>;
594 //===----------------------------------------------------------------------===//
596 //===----------------------------------------------------------------------===//
598 ///===- Integer Arithmetic Instructions -----------------------------------===//
600 defm ADD : INT3<"add", add>;
601 defm SUB : INT3<"sub", sub>;
602 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
603 defm DIV : INT3<"div", udiv>;
604 defm REM : INT3<"rem", urem>;
606 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
608 // Standard Unary Operations
609 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
611 // Standard Binary Operations
612 defm FADD : PTX_FLOAT_3OP<"add.rn", fadd>;
613 defm FSUB : PTX_FLOAT_3OP<"sub.rn", fsub>;
614 defm FMUL : PTX_FLOAT_3OP<"mul.rn", fmul>;
616 // For floating-point division:
617 // SM_13+ defaults to .rn for f32 and f64,
618 // SM10 must *not* provide a rounding
621 // - Allow user selection of rounding modes for fdiv
622 // - Add support for -prec-div=false (.approx)
624 def FDIVrr32SM13 : InstPTX<(outs RegF32:$d),
625 (ins RegF32:$a, RegF32:$b),
626 "div.rn.f32\t$d, $a, $b",
627 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
628 Requires<[FDivNeedsRoundingMode]>;
629 def FDIVri32SM13 : InstPTX<(outs RegF32:$d),
630 (ins RegF32:$a, f32imm:$b),
631 "div.rn.f32\t$d, $a, $b",
632 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
633 Requires<[FDivNeedsRoundingMode]>;
634 def FDIVrr32SM10 : InstPTX<(outs RegF32:$d),
635 (ins RegF32:$a, RegF32:$b),
636 "div.f32\t$d, $a, $b",
637 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
638 Requires<[FDivNoRoundingMode]>;
639 def FDIVri32SM10 : InstPTX<(outs RegF32:$d),
640 (ins RegF32:$a, f32imm:$b),
641 "div.f32\t$d, $a, $b",
642 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
643 Requires<[FDivNoRoundingMode]>;
645 def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
646 (ins RegF64:$a, RegF64:$b),
647 "div.rn.f64\t$d, $a, $b",
648 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
649 Requires<[FDivNeedsRoundingMode]>;
650 def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
651 (ins RegF64:$a, f64imm:$b),
652 "div.rn.f64\t$d, $a, $b",
653 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
654 Requires<[FDivNeedsRoundingMode]>;
655 def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
656 (ins RegF64:$a, RegF64:$b),
657 "div.f64\t$d, $a, $b",
658 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
659 Requires<[FDivNoRoundingMode]>;
660 def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
661 (ins RegF64:$a, f64imm:$b),
662 "div.f64\t$d, $a, $b",
663 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
664 Requires<[FDivNoRoundingMode]>;
668 // Multi-operation hybrid instructions
670 // The selection of mad/fma is tricky. In some cases, they are the *same*
671 // instruction, but in other cases we may prefer one or the other. Also,
672 // different PTX versions differ on whether rounding mode flags are required.
673 // In the short term, mad is supported on all PTX versions and we use a
674 // default rounding mode no matter what shader model or PTX version.
675 // TODO: Allow the rounding mode to be selectable through llc.
676 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>,
677 Requires<[FMadNeedsRoundingMode, SupportsFMA]>;
678 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>,
679 Requires<[FMadNoRoundingMode, SupportsFMA]>;
681 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
683 def FSQRT32 : InstPTX<(outs RegF32:$d),
685 "sqrt.rn.f32\t$d, $a",
686 [(set RegF32:$d, (fsqrt RegF32:$a))]>;
688 def FSQRT64 : InstPTX<(outs RegF64:$d),
690 "sqrt.rn.f64\t$d, $a",
691 [(set RegF64:$d, (fsqrt RegF64:$a))]>;
693 def FSIN32 : InstPTX<(outs RegF32:$d),
695 "sin.approx.f32\t$d, $a",
696 [(set RegF32:$d, (fsin RegF32:$a))]>;
698 def FSIN64 : InstPTX<(outs RegF64:$d),
700 "sin.approx.f64\t$d, $a",
701 [(set RegF64:$d, (fsin RegF64:$a))]>;
703 def FCOS32 : InstPTX<(outs RegF32:$d),
705 "cos.approx.f32\t$d, $a",
706 [(set RegF32:$d, (fcos RegF32:$a))]>;
708 def FCOS64 : InstPTX<(outs RegF64:$d),
710 "cos.approx.f64\t$d, $a",
711 [(set RegF64:$d, (fcos RegF64:$a))]>;
714 ///===- Comparison and Selection Instructions -----------------------------===//
720 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
721 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
722 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
723 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
724 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
725 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
726 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">;
727 defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE, "le">;
728 defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT, "gt">;
729 defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE, "ge">;
733 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
734 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
735 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
736 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
737 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
738 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
739 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">;
740 defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE, "le">;
741 defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT, "gt">;
742 defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE, "ge">;
746 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
747 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
748 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
749 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
750 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
751 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
752 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">;
753 defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE, "le">;
754 defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT, "gt">;
755 defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">;
759 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", SETUEQ, SETOEQ, "eq">;
760 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", SETUNE, SETONE, "ne">;
761 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
762 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", SETULE, SETOLE, "le">;
763 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", SETUGT, SETOGT, "gt">;
764 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", SETUGE, SETOGE, "ge">;
768 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", SETUEQ, SETOEQ, "eq">;
769 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", SETUNE, SETONE, "ne">;
770 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
771 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", SETULE, SETOLE, "le">;
772 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", SETUGT, SETOGT, "gt">;
773 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", SETUGE, SETOGE, "ge">;
777 defm PTX_SELPu16 : PTX_SELP<RegI16, "u16">;
778 defm PTX_SELPu32 : PTX_SELP<RegI32, "u32">;
779 defm PTX_SELPu64 : PTX_SELP<RegI64, "u64">;
780 defm PTX_SELPf32 : PTX_SELP<RegF32, "f32">;
781 defm PTX_SELPf64 : PTX_SELP<RegF64, "f64">;
783 ///===- Logic and Shift Instructions --------------------------------------===//
785 defm SHL : INT3ntnc<"shl.b", PTXshl>;
786 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
787 defm SRA : INT3ntnc<"shr.s", PTXsra>;
789 defm AND : PTX_LOGIC<"and", and>;
790 defm OR : PTX_LOGIC<"or", or>;
791 defm XOR : PTX_LOGIC<"xor", xor>;
793 ///===- Data Movement and Conversion Instructions -------------------------===//
795 let neverHasSideEffects = 1 in {
797 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
799 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
801 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
803 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
805 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
807 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
810 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
812 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
813 [(set RegPred:$d, imm:$a)]>;
815 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
816 [(set RegI16:$d, imm:$a)]>;
818 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
819 [(set RegI32:$d, imm:$a)]>;
821 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
822 [(set RegI64:$d, imm:$a)]>;
824 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
825 [(set RegF32:$d, fpimm:$a)]>;
827 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
828 [(set RegF64:$d, fpimm:$a)]>;
831 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
833 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
834 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
836 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
837 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
841 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
842 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
843 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
844 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
846 // These instructions are used to load/store from the .param space for
847 // device and kernel parameters
849 let hasSideEffects = 1 in {
850 def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
851 "ld.param.pred\t$d, [$a]",
852 [(set RegPred:$d, (PTXloadparam timm:$a))]>;
853 def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
854 "ld.param.u16\t$d, [$a]",
855 [(set RegI16:$d, (PTXloadparam timm:$a))]>;
856 def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
857 "ld.param.u32\t$d, [$a]",
858 [(set RegI32:$d, (PTXloadparam timm:$a))]>;
859 def LDpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
860 "ld.param.u64\t$d, [$a]",
861 [(set RegI64:$d, (PTXloadparam timm:$a))]>;
862 def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
863 "ld.param.f32\t$d, [$a]",
864 [(set RegF32:$d, (PTXloadparam timm:$a))]>;
865 def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
866 "ld.param.f64\t$d, [$a]",
867 [(set RegF64:$d, (PTXloadparam timm:$a))]>;
869 def STpiPred : InstPTX<(outs), (ins MEMret:$d, RegPred:$a),
870 "st.param.pred\t[$d], $a",
871 [(PTXstoreparam timm:$d, RegPred:$a)]>;
872 def STpiU16 : InstPTX<(outs), (ins MEMret:$d, RegI16:$a),
873 "st.param.u16\t[$d], $a",
874 [(PTXstoreparam timm:$d, RegI16:$a)]>;
875 def STpiU32 : InstPTX<(outs), (ins MEMret:$d, RegI32:$a),
876 "st.param.u32\t[$d], $a",
877 [(PTXstoreparam timm:$d, RegI32:$a)]>;
878 def STpiU64 : InstPTX<(outs), (ins MEMret:$d, RegI64:$a),
879 "st.param.u64\t[$d], $a",
880 [(PTXstoreparam timm:$d, RegI64:$a)]>;
881 def STpiF32 : InstPTX<(outs), (ins MEMret:$d, RegF32:$a),
882 "st.param.f32\t[$d], $a",
883 [(PTXstoreparam timm:$d, RegF32:$a)]>;
884 def STpiF64 : InstPTX<(outs), (ins MEMret:$d, RegF64:$a),
885 "st.param.f64\t[$d], $a",
886 [(PTXstoreparam timm:$d, RegF64:$a)]>;
890 defm STg : PTX_ST_ALL<"st.global", store_global>;
891 defm STl : PTX_ST_ALL<"st.local", store_local>;
892 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
894 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
895 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
896 // TODO: Do something with st.param if/when it is needed.
898 // Conversion to pred
899 // PTX does not directly support converting to a predicate type, so we fake it
900 // by performing a greater-than test between the value and zero. This follows
901 // the C convention that any non-zero value is equivalent to 'true'.
903 : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
904 [(set RegPred:$d, (trunc RegI16:$a))]>;
907 : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
908 [(set RegPred:$d, (trunc RegI32:$a))]>;
911 : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
912 [(set RegPred:$d, (trunc RegI64:$a))]>;
915 : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
916 [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
919 : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
920 [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
923 // PTX does not directly support converting a predicate to a value, so we
924 // use a select instruction to select either 0 or 1 (integer or fp) based
925 // on the truth value of the predicate.
927 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
928 [(set RegI16:$d, (anyext RegPred:$a))]>;
931 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
932 [(set RegI16:$d, (zext RegPred:$a))]>;
935 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
936 [(set RegI16:$d, (sext RegPred:$a))]>;
939 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
940 [(set RegI16:$d, (trunc RegI32:$a))]>;
943 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a",
944 [(set RegI16:$d, (trunc RegI64:$a))]>;
947 : InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a",
948 [(set RegI16:$d, (fp_to_uint RegF32:$a))]>;
951 : InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a",
952 [(set RegI16:$d, (fp_to_uint RegF64:$a))]>;
957 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
958 [(set RegI32:$d, (zext RegPred:$a))]>;
961 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
962 [(set RegI32:$d, (anyext RegI16:$a))]>;
965 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
966 [(set RegI32:$d, (zext RegI16:$a))]>;
969 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
970 [(set RegI32:$d, (sext RegPred:$a))]>;
973 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
974 [(set RegI32:$d, (sext RegI16:$a))]>;
977 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
978 [(set RegI32:$d, (trunc RegI64:$a))]>;
981 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a",
982 [(set RegI32:$d, (fp_to_uint RegF32:$a))]>;
985 : InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a",
986 [(set RegI32:$d, (fp_to_uint RegF64:$a))]>;
991 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
992 [(set RegI64:$d, (zext RegPred:$a))]>;
995 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
996 [(set RegI64:$d, (sext RegPred:$a))]>;
999 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
1000 [(set RegI64:$d, (zext RegI16:$a))]>;
1003 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
1004 [(set RegI64:$d, (sext RegI16:$a))]>;
1007 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
1008 [(set RegI64:$d, (zext RegI32:$a))]>;
1011 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
1012 [(set RegI64:$d, (sext RegI32:$a))]>;
1015 : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a",
1016 [(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
1019 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a",
1020 [(set RegI64:$d, (fp_to_uint RegF64:$a))]>;
1022 // Conversion to f32
1025 : InstPTX<(outs RegF32:$d), (ins RegPred:$a),
1026 "selp.f32\t$d, 0F3F800000, 0F00000000, $a", // 1.0
1027 [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
1030 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
1031 [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
1034 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a",
1035 [(set RegF32:$d, (uint_to_fp RegI32:$a))]>;
1038 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a",
1039 [(set RegF32:$d, (uint_to_fp RegI64:$a))]>;
1042 : InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
1043 [(set RegF32:$d, (fround RegF64:$a))]>;
1045 // Conversion to f64
1048 : InstPTX<(outs RegF64:$d), (ins RegPred:$a),
1049 "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a", // 1.0
1050 [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
1053 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
1054 [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
1057 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a",
1058 [(set RegF64:$d, (uint_to_fp RegI32:$a))]>;
1061 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a",
1062 [(set RegF64:$d, (uint_to_fp RegI64:$a))]>;
1065 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
1066 [(set RegF64:$d, (fextend RegF32:$a))]>;
1068 ///===- Control Flow Instructions -----------------------------------------===//
1070 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1072 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
1075 let isBranch = 1, isTerminator = 1 in {
1076 // FIXME: The pattern part is blank because I cannot (or do not yet know
1077 // how to) use the first operand of PredicateOperand (a RegPred register) here
1079 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
1080 [/*(brcond pred:$_p, bb:$d)*/]>;
1083 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1084 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
1085 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
1088 let hasSideEffects = 1 in {
1089 def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>;
1093 ///===- Spill Instructions ------------------------------------------------===//
1094 // Special instructions used for stack spilling
1095 def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
1096 "mov.u16\ts$d, $a", []>;
1097 def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
1098 "mov.u32\ts$d, $a", []>;
1099 def STACKSTOREI64 : InstPTX<(outs), (ins i32imm:$d, RegI64:$a),
1100 "mov.u64\ts$d, $a", []>;
1101 def STACKSTOREF32 : InstPTX<(outs), (ins i32imm:$d, RegF32:$a),
1102 "mov.f32\ts$d, $a", []>;
1103 def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
1104 "mov.f64\ts$d, $a", []>;
1106 def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
1107 "mov.u16\t$d, s$a", []>;
1108 def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),
1109 "mov.u32\t$d, s$a", []>;
1110 def STACKLOADI64 : InstPTX<(outs), (ins RegI64:$d, i32imm:$a),
1111 "mov.u64\t$d, s$a", []>;
1112 def STACKLOADF32 : InstPTX<(outs), (ins RegF32:$d, i32imm:$a),
1113 "mov.f32\t$d, s$a", []>;
1114 def STACKLOADF64 : InstPTX<(outs), (ins RegF64:$d, i32imm:$a),
1115 "mov.f64\t$d, s$a", []>;
1119 // def ADJCALLSTACKUP :
1120 // InstPTX<(outs), (ins i32imm:$amt1, i32imm:$amt2), "",
1121 // [(PTXcallseq_end timm:$amt1, timm:$amt2)]>;
1122 // def ADJCALLSTACKDOWN :
1123 // InstPTX<(outs), (ins i32imm:$amt), "",
1124 // [(PTXcallseq_start timm:$amt)]>;
1126 ///===- Intrinsic Instructions --------------------------------------------===//
1128 include "PTXIntrinsicInstrInfo.td"