1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
24 // Shader Model Support
25 def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">;
26 def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">;
27 def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">;
28 def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">;
30 // PTX Version Support
31 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
32 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
33 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
34 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
35 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
36 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
39 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
40 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
44 // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
45 // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
47 // def PTXcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PTXCallSeqStart,
48 // [SDNPHasChain, SDNPOutGlue]>;
49 // def PTXcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PTXCallSeqEnd,
50 // [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
52 def PTXcall : SDNode<"PTXISD::CALL", SDTNone,
53 [SDNPHasChain, SDNPVariadic, SDNPOptInGlue, SDNPOutGlue]>;
56 // Branch & call targets have OtherVT type.
57 def brtarget : Operand<OtherVT>;
58 def calltarget : Operand<i32>;
60 //===----------------------------------------------------------------------===//
61 // PTX Specific Node Definitions
62 //===----------------------------------------------------------------------===//
64 // PTX allow generic 3-reg shifts like shl r0, r1, r2
65 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
66 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
67 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
70 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
72 : SDNode<"PTXISD::RET", SDTNone,
73 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
75 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
79 //===----------------------------------------------------------------------===//
80 // Instruction Class Templates
81 //===----------------------------------------------------------------------===//
83 // For floating-point instructions, we cannot just embed the pattern into the
84 // instruction definition since we need to muck around with the rounding mode,
85 // and I do not know how to insert constants into instructions directly from
88 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
89 multiclass PTX_FLOAT_2OP<string opcstr> {
90 def rr32 : InstPTX<(outs RegF32:$d),
91 (ins RndMode:$r, RegF32:$a),
92 !strconcat(opcstr, "$r.f32\t$d, $a"), []>;
93 def ri32 : InstPTX<(outs RegF32:$d),
94 (ins RndMode:$r, f32imm:$a),
95 !strconcat(opcstr, "$r.f32\t$d, $a"), []>;
96 def rr64 : InstPTX<(outs RegF64:$d),
97 (ins RndMode:$r, RegF64:$a),
98 !strconcat(opcstr, "$r.f64\t$d, $a"), []>;
99 def ri64 : InstPTX<(outs RegF64:$d),
100 (ins RndMode:$r, f64imm:$a),
101 !strconcat(opcstr, "$r.f64\t$d, $a"), []>;
104 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
105 multiclass PTX_FLOAT_3OP<string opcstr> {
106 def rr32 : InstPTX<(outs RegF32:$d),
107 (ins RndMode:$r, RegF32:$a, RegF32:$b),
108 !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>;
109 def ri32 : InstPTX<(outs RegF32:$d),
110 (ins RndMode:$r, RegF32:$a, f32imm:$b),
111 !strconcat(opcstr, "$r.f32\t$d, $a, $b"), []>;
112 def rr64 : InstPTX<(outs RegF64:$d),
113 (ins RndMode:$r, RegF64:$a, RegF64:$b),
114 !strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>;
115 def ri64 : InstPTX<(outs RegF64:$d),
116 (ins RndMode:$r, RegF64:$a, f64imm:$b),
117 !strconcat(opcstr, "$r.f64\t$d, $a, $b"), []>;
120 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
121 multiclass PTX_FLOAT_4OP<string opcstr> {
122 def rrr32 : InstPTX<(outs RegF32:$d),
123 (ins RndMode:$r, RegF32:$a, RegF32:$b, RegF32:$c),
124 !strconcat(opcstr, "$r.f32\t$d, $a, $b, $c"), []>;
125 def rri32 : InstPTX<(outs RegF32:$d),
126 (ins RndMode:$r, RegF32:$a, RegF32:$b, f32imm:$c),
127 !strconcat(opcstr, "$r.f32\t$d, $a, $b, $c"), []>;
128 def rii32 : InstPTX<(outs RegF32:$d),
129 (ins RndMode:$r, RegF32:$a, f32imm:$b, f32imm:$c),
130 !strconcat(opcstr, "$r.f32\t$d, $a, $b, $c"), []>;
131 def rrr64 : InstPTX<(outs RegF64:$d),
132 (ins RndMode:$r, RegF64:$a, RegF64:$b, RegF64:$c),
133 !strconcat(opcstr, "$r.f64\t$d, $a, $b, $c"), []>;
134 def rri64 : InstPTX<(outs RegF64:$d),
135 (ins RndMode:$r, RegF64:$a, RegF64:$b, f64imm:$c),
136 !strconcat(opcstr, "$r.f64\t$d, $a, $b, $c"), []>;
137 def rii64 : InstPTX<(outs RegF64:$d),
138 (ins RndMode:$r, RegF64:$a, f64imm:$b, f64imm:$c),
139 !strconcat(opcstr, "$r.f64\t$d, $a, $b, $c"), []>;
142 //===- Integer Instructions - 3 Operand Form ------------------------------===//
143 multiclass PTX_INT3<string opcstr, SDNode opnode> {
144 def rr16 : InstPTX<(outs RegI16:$d),
145 (ins RegI16:$a, RegI16:$b),
146 !strconcat(opcstr, ".u16\t$d, $a, $b"),
147 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
148 def ri16 : InstPTX<(outs RegI16:$d),
149 (ins RegI16:$a, i16imm:$b),
150 !strconcat(opcstr, ".u16\t$d, $a, $b"),
151 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
152 def rr32 : InstPTX<(outs RegI32:$d),
153 (ins RegI32:$a, RegI32:$b),
154 !strconcat(opcstr, ".u32\t$d, $a, $b"),
155 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
156 def ri32 : InstPTX<(outs RegI32:$d),
157 (ins RegI32:$a, i32imm:$b),
158 !strconcat(opcstr, ".u32\t$d, $a, $b"),
159 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
160 def rr64 : InstPTX<(outs RegI64:$d),
161 (ins RegI64:$a, RegI64:$b),
162 !strconcat(opcstr, ".u64\t$d, $a, $b"),
163 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
164 def ri64 : InstPTX<(outs RegI64:$d),
165 (ins RegI64:$a, i64imm:$b),
166 !strconcat(opcstr, ".u64\t$d, $a, $b"),
167 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
170 //===- Integer Instructions - 3 Operand Form (Signed) ---------------------===//
171 multiclass PTX_INT3_SIGNED<string opcstr, SDNode opnode> {
172 def rr16 : InstPTX<(outs RegI16:$d),
173 (ins RegI16:$a, RegI16:$b),
174 !strconcat(opcstr, ".s16\t$d, $a, $b"),
175 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
176 def ri16 : InstPTX<(outs RegI16:$d),
177 (ins RegI16:$a, i16imm:$b),
178 !strconcat(opcstr, ".s16\t$d, $a, $b"),
179 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
180 def rr32 : InstPTX<(outs RegI32:$d),
181 (ins RegI32:$a, RegI32:$b),
182 !strconcat(opcstr, ".s32\t$d, $a, $b"),
183 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
184 def ri32 : InstPTX<(outs RegI32:$d),
185 (ins RegI32:$a, i32imm:$b),
186 !strconcat(opcstr, ".s32\t$d, $a, $b"),
187 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
188 def rr64 : InstPTX<(outs RegI64:$d),
189 (ins RegI64:$a, RegI64:$b),
190 !strconcat(opcstr, ".s64\t$d, $a, $b"),
191 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
192 def ri64 : InstPTX<(outs RegI64:$d),
193 (ins RegI64:$a, i64imm:$b),
194 !strconcat(opcstr, ".s64\t$d, $a, $b"),
195 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
198 //===- Bitwise Logic Instructions - 3 Operand Form ------------------------===//
199 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
200 def ripreds : InstPTX<(outs RegPred:$d),
201 (ins RegPred:$a, i1imm:$b),
202 !strconcat(opcstr, ".pred\t$d, $a, $b"),
203 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
204 def rrpreds : InstPTX<(outs RegPred:$d),
205 (ins RegPred:$a, RegPred:$b),
206 !strconcat(opcstr, ".pred\t$d, $a, $b"),
207 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
208 def rr16 : InstPTX<(outs RegI16:$d),
209 (ins RegI16:$a, RegI16:$b),
210 !strconcat(opcstr, ".b16\t$d, $a, $b"),
211 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
212 def ri16 : InstPTX<(outs RegI16:$d),
213 (ins RegI16:$a, i16imm:$b),
214 !strconcat(opcstr, ".b16\t$d, $a, $b"),
215 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
216 def rr32 : InstPTX<(outs RegI32:$d),
217 (ins RegI32:$a, RegI32:$b),
218 !strconcat(opcstr, ".b32\t$d, $a, $b"),
219 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
220 def ri32 : InstPTX<(outs RegI32:$d),
221 (ins RegI32:$a, i32imm:$b),
222 !strconcat(opcstr, ".b32\t$d, $a, $b"),
223 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
224 def rr64 : InstPTX<(outs RegI64:$d),
225 (ins RegI64:$a, RegI64:$b),
226 !strconcat(opcstr, ".b64\t$d, $a, $b"),
227 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
228 def ri64 : InstPTX<(outs RegI64:$d),
229 (ins RegI64:$a, i64imm:$b),
230 !strconcat(opcstr, ".b64\t$d, $a, $b"),
231 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
234 //===- Integer Shift Instructions - 3 Operand Form ------------------------===//
235 multiclass PTX_INT3ntnc<string opcstr, SDNode opnode> {
236 def rr16 : InstPTX<(outs RegI16:$d),
237 (ins RegI16:$a, RegI16:$b),
238 !strconcat(opcstr, "16\t$d, $a, $b"),
239 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
240 def rr32 : InstPTX<(outs RegI32:$d),
241 (ins RegI32:$a, RegI32:$b),
242 !strconcat(opcstr, "32\t$d, $a, $b"),
243 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
244 def rr64 : InstPTX<(outs RegI64:$d),
245 (ins RegI64:$a, RegI64:$b),
246 !strconcat(opcstr, "64\t$d, $a, $b"),
247 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
248 def ri16 : InstPTX<(outs RegI16:$d),
249 (ins RegI16:$a, i16imm:$b),
250 !strconcat(opcstr, "16\t$d, $a, $b"),
251 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
252 def ri32 : InstPTX<(outs RegI32:$d),
253 (ins RegI32:$a, i32imm:$b),
254 !strconcat(opcstr, "32\t$d, $a, $b"),
255 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
256 def ri64 : InstPTX<(outs RegI64:$d),
257 (ins RegI64:$a, i64imm:$b),
258 !strconcat(opcstr, "64\t$d, $a, $b"),
259 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
260 def ir16 : InstPTX<(outs RegI16:$d),
261 (ins i16imm:$a, RegI16:$b),
262 !strconcat(opcstr, "16\t$d, $a, $b"),
263 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
264 def ir32 : InstPTX<(outs RegI32:$d),
265 (ins i32imm:$a, RegI32:$b),
266 !strconcat(opcstr, "32\t$d, $a, $b"),
267 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
268 def ir64 : InstPTX<(outs RegI64:$d),
269 (ins i64imm:$a, RegI64:$b),
270 !strconcat(opcstr, "64\t$d, $a, $b"),
271 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
274 //===- Set Predicate Instructions (Int) - 3/4 Operand Forms ---------------===//
275 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
276 CondCode cmp, string cmpstr> {
277 // TODO support 5-operand format: p|q, a, b, c
280 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
281 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
282 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
284 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
285 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
286 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
289 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
290 !strconcat("setp.", cmpstr, ".and.", regclsname,
292 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
294 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
295 !strconcat("setp.", cmpstr, ".and.", regclsname,
297 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
300 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
301 !strconcat("setp.", cmpstr, ".or.", regclsname,
303 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
305 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
306 !strconcat("setp.", cmpstr, ".or.", regclsname,
308 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
310 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
311 !strconcat("setp.", cmpstr, ".xor.", regclsname,
313 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
315 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
316 !strconcat("setp.", cmpstr, ".xor.", regclsname,
318 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
322 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
323 !strconcat("setp.", cmpstr, ".and.", regclsname,
324 "\t$p, $a, $b, !$c"),
325 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp),
326 (not RegPred:$c)))]>;
328 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
329 !strconcat("setp.", cmpstr, ".and.", regclsname,
330 "\t$p, $a, $b, !$c"),
331 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
332 (not RegPred:$c)))]>;
334 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
335 !strconcat("setp.", cmpstr, ".or.", regclsname,
336 "\t$p, $a, $b, !$c"),
337 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp),
338 (not RegPred:$c)))]>;
340 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
341 !strconcat("setp.", cmpstr, ".or.", regclsname,
342 "\t$p, $a, $b, !$c"),
343 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp),
344 (not RegPred:$c)))]>;
346 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
347 !strconcat("setp.", cmpstr, ".xor.", regclsname,
348 "\t$p, $a, $b, !$c"),
349 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp),
350 (not RegPred:$c)))]>;
352 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
353 !strconcat("setp.", cmpstr, ".xor.", regclsname,
354 "\t$p, $a, $b, !$c"),
355 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
356 (not RegPred:$c)))]>;
359 //===- Set Predicate Instructions (FP) - 3/4 Operand Form -----------------===//
360 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname, Operand immcls,
361 CondCode ucmp, CondCode ocmp, string cmpstr> {
362 // TODO support 5-operand format: p|q, a, b, c
365 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
366 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
367 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
369 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
370 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
371 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
374 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
375 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
376 [(set RegPred:$p, (setcc RC:$a, fpimm:$b, ucmp))]>;
378 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
379 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
380 [(set RegPred:$p, (setcc RC:$a, fpimm:$b, ocmp))]>;
383 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
384 !strconcat("setp.", cmpstr, "u.and.", regclsname,
386 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
389 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
390 !strconcat("setp.", cmpstr, ".and.", regclsname,
392 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
396 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
397 !strconcat("setp.", cmpstr, "u.or.", regclsname,
399 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
401 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
402 !strconcat("setp.", cmpstr, ".or.", regclsname,
404 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
407 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
408 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
410 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
413 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
414 !strconcat("setp.", cmpstr, ".xor.", regclsname,
416 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
420 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
421 !strconcat("setp.", cmpstr, "u.and.", regclsname,
422 "\t$p, $a, $b, !$c"),
423 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
424 (not RegPred:$c)))]>;
426 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
427 !strconcat("setp.", cmpstr, ".and.", regclsname,
428 "\t$p, $a, $b, !$c"),
429 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
430 (not RegPred:$c)))]>;
433 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
434 !strconcat("setp.", cmpstr, "u.or.", regclsname,
435 "\t$p, $a, $b, !$c"),
436 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp),
437 (not RegPred:$c)))]>;
439 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
440 !strconcat("setp.", cmpstr, ".or.", regclsname,
441 "\t$p, $a, $b, !$c"),
442 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp),
443 (not RegPred:$c)))]>;
446 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
447 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
448 "\t$p, $a, $b, !$c"),
449 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
450 (not RegPred:$c)))]>;
452 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
453 !strconcat("setp.", cmpstr, ".xor.", regclsname,
454 "\t$p, $a, $b, !$c"),
455 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
456 (not RegPred:$c)))]>;
459 //===- Select Predicate Instructions - 4 Operand Form ---------------------===//
460 multiclass PTX_SELP<RegisterClass RC, string regclsname, Operand immcls,
463 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
464 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
465 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
467 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, immcls:$c),
468 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
469 [(set RC:$r, (select RegPred:$a, RC:$b, immnode:$c))]>;
471 : InstPTX<(outs RC:$r), (ins RegPred:$a, immcls:$b, immcls:$c),
472 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
473 [(set RC:$r, (select RegPred:$a, immnode:$b, immnode:$c))]>;
478 //===----------------------------------------------------------------------===//
480 //===----------------------------------------------------------------------===//
482 ///===- Integer Arithmetic Instructions -----------------------------------===//
484 defm ADD : PTX_INT3<"add", add>;
485 defm SUB : PTX_INT3<"sub", sub>;
486 defm MUL : PTX_INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
487 defm DIV : PTX_INT3<"div", udiv>;
488 defm SDIV : PTX_INT3_SIGNED<"div", sdiv>;
489 defm REM : PTX_INT3<"rem", urem>;
491 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
494 defm FNEG : PTX_FLOAT_2OP<"neg">;
496 // Standard Binary Operations
497 defm FADD : PTX_FLOAT_3OP<"add">;
498 defm FSUB : PTX_FLOAT_3OP<"sub">;
499 defm FMUL : PTX_FLOAT_3OP<"mul">;
500 defm FDIV : PTX_FLOAT_3OP<"div">;
502 // Multi-operation hybrid instructions
503 defm FMAD : PTX_FLOAT_4OP<"mad">, Requires<[SupportsFMA]>;
506 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
509 def FSQRTrr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a),
510 "sqrt$r.f32\t$d, $a", []>;
511 def FSQRTri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, f32imm:$a),
512 "sqrt$r.f32\t$d, $a", []>;
513 def FSQRTrr64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegF64:$a),
514 "sqrt$r.f64\t$d, $a", []>;
515 def FSQRTri64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, f64imm:$a),
516 "sqrt$r.f64\t$d, $a", []>;
519 def FSINrr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a),
520 "sin$r.f32\t$d, $a", []>;
521 def FSINri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, f32imm:$a),
522 "sin$r.f32\t$d, $a", []>;
523 def FSINrr64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegF64:$a),
524 "sin$r.f64\t$d, $a", []>;
525 def FSINri64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, f64imm:$a),
526 "sin$r.f64\t$d, $a", []>;
529 def FCOSrr32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF32:$a),
530 "cos$r.f32\t$d, $a", []>;
531 def FCOSri32 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, f32imm:$a),
532 "cos$r.f32\t$d, $a", []>;
533 def FCOSrr64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegF64:$a),
534 "cos$r.f64\t$d, $a", []>;
535 def FCOSri64 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, f64imm:$a),
536 "cos$r.f64\t$d, $a", []>;
541 ///===- Comparison and Selection Instructions -----------------------------===//
547 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
548 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
549 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
550 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
551 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
552 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
553 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">;
554 defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE, "le">;
555 defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT, "gt">;
556 defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE, "ge">;
560 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
561 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
562 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
563 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
564 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
565 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
566 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">;
567 defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE, "le">;
568 defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT, "gt">;
569 defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE, "ge">;
573 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
574 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
575 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
576 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
577 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
578 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
579 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">;
580 defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE, "le">;
581 defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT, "gt">;
582 defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">;
586 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUEQ, SETOEQ, "eq">;
587 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUNE, SETONE, "ne">;
588 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULT, SETOLT, "lt">;
589 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULE, SETOLE, "le">;
590 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGT, SETOGT, "gt">;
591 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGE, SETOGE, "ge">;
595 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUEQ, SETOEQ, "eq">;
596 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUNE, SETONE, "ne">;
597 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULT, SETOLT, "lt">;
598 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULE, SETOLE, "le">;
599 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGT, SETOGT, "gt">;
600 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGE, SETOGE, "ge">;
604 defm SELPi16 : PTX_SELP<RegI16, "u16", i16imm, imm>;
605 defm SELPi32 : PTX_SELP<RegI32, "u32", i32imm, imm>;
606 defm SELPi64 : PTX_SELP<RegI64, "u64", i64imm, imm>;
607 defm SELPf32 : PTX_SELP<RegF32, "f32", f32imm, fpimm>;
608 defm SELPf64 : PTX_SELP<RegF64, "f64", f64imm, fpimm>;
610 ///===- Logic and Shift Instructions --------------------------------------===//
612 defm SHL : PTX_INT3ntnc<"shl.b", PTXshl>;
613 defm SRL : PTX_INT3ntnc<"shr.u", PTXsrl>;
614 defm SRA : PTX_INT3ntnc<"shr.s", PTXsra>;
616 defm AND : PTX_LOGIC<"and", and>;
617 defm OR : PTX_LOGIC<"or", or>;
618 defm XOR : PTX_LOGIC<"xor", xor>;
620 ///===- Data Movement and Conversion Instructions -------------------------===//
623 // Implement the anyext instruction in terms of the PTX cvt instructions.
624 //def : Pat<(i32 (anyext RegI16:$a)), (CVT_u32_u16 RegI16:$a)>;
625 //def : Pat<(i64 (anyext RegI16:$a)), (CVT_u64_u16 RegI16:$a)>;
626 //def : Pat<(i64 (anyext RegI32:$a)), (CVT_u64_u32 RegI32:$a)>;
629 // These instructions implement the bit-wise conversion between integer and
630 // floating-point types.
632 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a", []>;
634 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "mov.b32\t$d, $a", []>;
636 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "mov.b64\t$d, $a", []>;
638 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "mov.b64\t$d, $a", []>;
640 let neverHasSideEffects = 1 in {
642 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
644 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
646 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
648 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
650 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
652 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
655 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
657 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
658 [(set RegPred:$d, imm:$a)]>;
660 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
661 [(set RegI16:$d, imm:$a)]>;
663 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
664 [(set RegI32:$d, imm:$a)]>;
666 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
667 [(set RegI64:$d, imm:$a)]>;
669 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
670 [(set RegF32:$d, fpimm:$a)]>;
672 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
673 [(set RegF64:$d, fpimm:$a)]>;
676 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
678 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
679 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
681 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
682 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
684 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "cvta.local.u32\t$d, $a",
685 [(set RegI32:$d, (PTXcopyaddress frameindex:$a))]>;
687 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "cvta.local.u64\t$d, $a",
688 [(set RegI64:$d, (PTXcopyaddress frameindex:$a))]>;
691 // PTX cvt instructions
692 // Note all of these may actually be used, we just define all possible patterns
693 // here (that make sense).
694 // FIXME: Can we collapse this somehow into a multiclass def?
698 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a", []>;
700 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a", []>;
702 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF32:$a),
703 "cvt$r.u16.f32\t$d, $a", []>;
705 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF32:$a),
706 "cvt$r.s16.f32\t$d, $a", []>;
708 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF64:$a),
709 "cvt$r.u16.f64\t$d, $a", []>;
711 : InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF64:$a),
712 "cvt$r.s16.f64\t$d, $a", []>;
716 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a", []>;
718 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.s32.s16\t$d, $a", []>;
720 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a", []>;
722 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF32:$a),
723 "cvt$r.u32.f32\t$d, $a", []>;
725 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF32:$a),
726 "cvt$r.s32.f32\t$d, $a", []>;
728 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF64:$a),
729 "cvt$r.u32.f64\t$d, $a", []>;
731 : InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF64:$a),
732 "cvt$r.s32.f64\t$d, $a", []>;
736 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a", []>;
738 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.s64.s16\t$d, $a", []>;
740 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a", []>;
742 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.s64.s32\t$d, $a", []>;
744 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF32:$a),
745 "cvt$r.u64.f32\t$d, $a", []>;
747 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF32:$a),
748 "cvt$r.s64.f32\t$d, $a", []>;
750 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF64:$a),
751 "cvt$r.u64.f64\t$d, $a", []>;
753 : InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF64:$a),
754 "cvt$r.s64.f64\t$d, $a", []>;
758 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI16:$a),
759 "cvt$r.f32.u16\t$d, $a", []>;
761 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI16:$a),
762 "cvt$r.f32.s16\t$d, $a", []>;
764 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI32:$a),
765 "cvt$r.f32.u32\t$d, $a", []>;
767 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI32:$a),
768 "cvt$r.f32.s32\t$d, $a", []>;
770 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI64:$a),
771 "cvt$r.f32.u64\t$d, $a", []>;
773 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI64:$a),
774 "cvt$r.f32.s64\t$d, $a", []>;
776 : InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF64:$a),
777 "cvt$r.f32.f64\t$d, $a", []>;
781 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI16:$a),
782 "cvt$r.f64.u16\t$d, $a", []>;
784 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI16:$a),
785 "cvt$r.f64.s16\t$d, $a", []>;
787 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI32:$a),
788 "cvt$r.f64.u32\t$d, $a", []>;
790 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI32:$a),
791 "cvt$r.f64.s32\t$d, $a", []>;
793 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI64:$a),
794 "cvt$r.f64.u64\t$d, $a", []>;
796 : InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI64:$a),
797 "cvt$r.f64.s64\t$d, $a", []>;
799 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", []>;
801 ///===- Control Flow Instructions -----------------------------------------===//
803 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
805 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
808 let isBranch = 1, isTerminator = 1 in {
809 // FIXME: The pattern part is blank because I cannot (or do not yet know
810 // how to) use the first operand of PredicateOperand (a RegPred register) here
812 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
813 [/*(brcond pred:$_p, bb:$d)*/]>;
816 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
817 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
818 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
821 let hasSideEffects = 1 in {
822 def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>;
825 ///===- Parameter Passing Pseudo-Instructions -----------------------------===//
827 def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b),
828 "mov.pred\t$a, %arg$b", []>;
829 def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b),
830 "mov.b16\t$a, %arg$b", []>;
831 def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b),
832 "mov.b32\t$a, %arg$b", []>;
833 def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b),
834 "mov.b64\t$a, %arg$b", []>;
835 def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b),
836 "mov.f32\t$a, %arg$b", []>;
837 def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b),
838 "mov.f64\t$a, %arg$b", []>;
840 def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>;
841 def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>;
842 def WRITEPARAMI32 : InstPTX<(outs), (ins RegI32:$a), "//w", []>;
843 def WRITEPARAMI64 : InstPTX<(outs), (ins RegI64:$a), "//w", []>;
844 def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>;
845 def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>;
848 //===----------------------------------------------------------------------===//
849 // Instruction Selection Patterns
850 //===----------------------------------------------------------------------===//
853 def : Pat<(f32 (fadd RegF32:$a, RegF32:$b)),
854 (FADDrr32 RndDefault, RegF32:$a, RegF32:$b)>;
855 def : Pat<(f32 (fadd RegF32:$a, fpimm:$b)),
856 (FADDri32 RndDefault, RegF32:$a, fpimm:$b)>;
857 def : Pat<(f64 (fadd RegF64:$a, RegF64:$b)),
858 (FADDrr64 RndDefault, RegF64:$a, RegF64:$b)>;
859 def : Pat<(f64 (fadd RegF64:$a, fpimm:$b)),
860 (FADDri64 RndDefault, RegF64:$a, fpimm:$b)>;
863 def : Pat<(f32 (fsub RegF32:$a, RegF32:$b)),
864 (FSUBrr32 RndDefault, RegF32:$a, RegF32:$b)>;
865 def : Pat<(f32 (fsub RegF32:$a, fpimm:$b)),
866 (FSUBri32 RndDefault, RegF32:$a, fpimm:$b)>;
867 def : Pat<(f64 (fsub RegF64:$a, RegF64:$b)),
868 (FSUBrr64 RndDefault, RegF64:$a, RegF64:$b)>;
869 def : Pat<(f64 (fsub RegF64:$a, fpimm:$b)),
870 (FSUBri64 RndDefault, RegF64:$a, fpimm:$b)>;
873 def : Pat<(f32 (fmul RegF32:$a, RegF32:$b)),
874 (FMULrr32 RndDefault, RegF32:$a, RegF32:$b)>;
875 def : Pat<(f32 (fmul RegF32:$a, fpimm:$b)),
876 (FMULri32 RndDefault, RegF32:$a, fpimm:$b)>;
877 def : Pat<(f64 (fmul RegF64:$a, RegF64:$b)),
878 (FMULrr64 RndDefault, RegF64:$a, RegF64:$b)>;
879 def : Pat<(f64 (fmul RegF64:$a, fpimm:$b)),
880 (FMULri64 RndDefault, RegF64:$a, fpimm:$b)>;
883 def : Pat<(f32 (fdiv RegF32:$a, RegF32:$b)),
884 (FDIVrr32 RndDefault, RegF32:$a, RegF32:$b)>;
885 def : Pat<(f32 (fdiv RegF32:$a, fpimm:$b)),
886 (FDIVri32 RndDefault, RegF32:$a, fpimm:$b)>;
887 def : Pat<(f64 (fdiv RegF64:$a, RegF64:$b)),
888 (FDIVrr64 RndDefault, RegF64:$a, RegF64:$b)>;
889 def : Pat<(f64 (fdiv RegF64:$a, fpimm:$b)),
890 (FDIVri64 RndDefault, RegF64:$a, fpimm:$b)>;
893 def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), RegF32:$c)),
894 (FMADrrr32 RndDefault, RegF32:$a, RegF32:$b, RegF32:$c)>,
895 Requires<[SupportsFMA]>;
896 def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), fpimm:$c)),
897 (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>,
898 Requires<[SupportsFMA]>;
899 def : Pat<(f32 (fadd (fmul RegF32:$a, fpimm:$b), fpimm:$c)),
900 (FMADrrr32 RndDefault, RegF32:$a, fpimm:$b, fpimm:$c)>,
901 Requires<[SupportsFMA]>;
902 def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), fpimm:$c)),
903 (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>,
904 Requires<[SupportsFMA]>;
905 def : Pat<(f64 (fadd (fmul RegF64:$a, RegF64:$b), RegF64:$c)),
906 (FMADrrr64 RndDefault, RegF64:$a, RegF64:$b, RegF64:$c)>,
907 Requires<[SupportsFMA]>;
908 def : Pat<(f64 (fadd (fmul RegF64:$a, RegF64:$b), fpimm:$c)),
909 (FMADrri64 RndDefault, RegF64:$a, RegF64:$b, fpimm:$c)>,
910 Requires<[SupportsFMA]>;
911 def : Pat<(f64 (fadd (fmul RegF64:$a, fpimm:$b), fpimm:$c)),
912 (FMADrri64 RndDefault, RegF64:$a, fpimm:$b, fpimm:$c)>,
913 Requires<[SupportsFMA]>;
916 def : Pat<(f32 (fneg RegF32:$a)), (FNEGrr32 RndDefault, RegF32:$a)>;
917 def : Pat<(f32 (fneg fpimm:$a)), (FNEGri32 RndDefault, fpimm:$a)>;
918 def : Pat<(f64 (fneg RegF64:$a)), (FNEGrr64 RndDefault, RegF64:$a)>;
919 def : Pat<(f64 (fneg fpimm:$a)), (FNEGri64 RndDefault, fpimm:$a)>;
922 def : Pat<(f32 (fsqrt RegF32:$a)), (FSQRTrr32 RndDefault, RegF32:$a)>;
923 def : Pat<(f32 (fsqrt fpimm:$a)), (FSQRTri32 RndDefault, fpimm:$a)>;
924 def : Pat<(f64 (fsqrt RegF64:$a)), (FSQRTrr64 RndDefault, RegF64:$a)>;
925 def : Pat<(f64 (fsqrt fpimm:$a)), (FSQRTri64 RndDefault, fpimm:$a)>;
928 def : Pat<(f32 (fsin RegF32:$a)), (FSINrr32 RndDefault, RegF32:$a)>;
929 def : Pat<(f32 (fsin fpimm:$a)), (FSINri32 RndDefault, fpimm:$a)>;
930 def : Pat<(f64 (fsin RegF64:$a)), (FSINrr64 RndDefault, RegF64:$a)>;
931 def : Pat<(f64 (fsin fpimm:$a)), (FSINri64 RndDefault, fpimm:$a)>;
934 def : Pat<(f32 (fcos RegF32:$a)), (FCOSrr32 RndDefault, RegF32:$a)>;
935 def : Pat<(f32 (fcos fpimm:$a)), (FCOSri32 RndDefault, fpimm:$a)>;
936 def : Pat<(f64 (fcos RegF64:$a)), (FCOSrr64 RndDefault, RegF64:$a)>;
937 def : Pat<(f64 (fcos fpimm:$a)), (FCOSri64 RndDefault, fpimm:$a)>;
939 // Type conversion notes:
940 // - PTX does not directly support converting a predicate to a value, so we
941 // use a select instruction to select either 0 or 1 (integer or fp) based
942 // on the truth value of the predicate.
943 // - PTX does not directly support converting to a predicate type, so we fake it
944 // by performing a greater-than test between the value and zero. This follows
945 // the C convention that any non-zero value is equivalent to 'true'.
947 // Conversion to pred
948 def : Pat<(i1 (trunc RegI16:$a)), (SETPGTu16ri RegI16:$a, 0)>;
949 def : Pat<(i1 (trunc RegI32:$a)), (SETPGTu32ri RegI32:$a, 0)>;
950 def : Pat<(i1 (trunc RegI64:$a)), (SETPGTu64ri RegI64:$a, 0)>;
951 def : Pat<(i1 (fp_to_uint RegF32:$a)), (SETPGTu32ri (MOVi32f32 RegF32:$a), 0)>;
952 def : Pat<(i1 (fp_to_uint RegF64:$a)), (SETPGTu64ri (MOVi64f64 RegF64:$a), 0)>;
955 def : Pat<(i16 (anyext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>;
956 def : Pat<(i16 (sext RegPred:$a)), (SELPi16ii RegPred:$a, 0xFFFF, 0)>;
957 def : Pat<(i16 (zext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>;
958 def : Pat<(i16 (trunc RegI32:$a)), (CVTu16u32 RegI32:$a)>;
959 def : Pat<(i16 (trunc RegI64:$a)), (CVTu16u64 RegI64:$a)>;
960 def : Pat<(i16 (fp_to_uint RegF32:$a)), (CVTu16f32 RndDefault, RegF32:$a)>;
961 def : Pat<(i16 (fp_to_sint RegF32:$a)), (CVTs16f32 RndDefault, RegF32:$a)>;
962 def : Pat<(i16 (fp_to_uint RegF64:$a)), (CVTu16f64 RndDefault, RegF64:$a)>;
963 def : Pat<(i16 (fp_to_sint RegF64:$a)), (CVTs16f64 RndDefault, RegF64:$a)>;
966 def : Pat<(i32 (anyext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>;
967 def : Pat<(i32 (sext RegPred:$a)), (SELPi32ii RegPred:$a, 0xFFFFFFFF, 0)>;
968 def : Pat<(i32 (zext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>;
969 def : Pat<(i32 (anyext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
970 def : Pat<(i32 (sext RegI16:$a)), (CVTs32s16 RegI16:$a)>;
971 def : Pat<(i32 (zext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
972 def : Pat<(i32 (trunc RegI64:$a)), (CVTu32u64 RegI64:$a)>;
973 def : Pat<(i32 (fp_to_uint RegF32:$a)), (CVTu32f32 RndDefault, RegF32:$a)>;
974 def : Pat<(i32 (fp_to_sint RegF32:$a)), (CVTs32f32 RndDefault, RegF32:$a)>;
975 def : Pat<(i32 (fp_to_uint RegF64:$a)), (CVTu32f64 RndDefault, RegF64:$a)>;
976 def : Pat<(i32 (fp_to_sint RegF64:$a)), (CVTs32f64 RndDefault, RegF64:$a)>;
977 def : Pat<(i32 (bitconvert RegF32:$a)), (MOVi32f32 RegF32:$a)>;
980 def : Pat<(i64 (anyext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>;
981 def : Pat<(i64 (sext RegPred:$a)), (SELPi64ii RegPred:$a,
982 0xFFFFFFFFFFFFFFFF, 0)>;
983 def : Pat<(i64 (zext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>;
984 def : Pat<(i64 (anyext RegI16:$a)), (CVTu64u16 RegI16:$a)>;
985 def : Pat<(i64 (sext RegI16:$a)), (CVTs64s16 RegI16:$a)>;
986 def : Pat<(i64 (zext RegI16:$a)), (CVTu64u16 RegI16:$a)>;
987 def : Pat<(i64 (anyext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
988 def : Pat<(i64 (sext RegI32:$a)), (CVTs64s32 RegI32:$a)>;
989 def : Pat<(i64 (zext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
990 def : Pat<(i64 (fp_to_uint RegF32:$a)), (CVTu64f32 RndDefault, RegF32:$a)>;
991 def : Pat<(i64 (fp_to_sint RegF32:$a)), (CVTs64f32 RndDefault, RegF32:$a)>;
992 def : Pat<(i64 (fp_to_uint RegF64:$a)), (CVTu64f64 RndDefault, RegF64:$a)>;
993 def : Pat<(i64 (fp_to_sint RegF64:$a)), (CVTs64f64 RndDefault, RegF64:$a)>;
994 def : Pat<(i64 (bitconvert RegF64:$a)), (MOVi64f64 RegF64:$a)>;
997 def : Pat<(f32 (uint_to_fp RegPred:$a)), (SELPf32rr RegPred:$a,
998 (MOVf32i32 0x3F800000), (MOVf32i32 0))>;
999 def : Pat<(f32 (uint_to_fp RegI16:$a)), (CVTf32u16 RndDefault, RegI16:$a)>;
1000 def : Pat<(f32 (sint_to_fp RegI16:$a)), (CVTf32s16 RndDefault, RegI16:$a)>;
1001 def : Pat<(f32 (uint_to_fp RegI32:$a)), (CVTf32u32 RndDefault, RegI32:$a)>;
1002 def : Pat<(f32 (sint_to_fp RegI32:$a)), (CVTf32s32 RndDefault, RegI32:$a)>;
1003 def : Pat<(f32 (uint_to_fp RegI64:$a)), (CVTf32u64 RndDefault, RegI64:$a)>;
1004 def : Pat<(f32 (sint_to_fp RegI64:$a)), (CVTf32s64 RndDefault, RegI64:$a)>;
1005 def : Pat<(f32 (fround RegF64:$a)), (CVTf32f64 RndDefault, RegF64:$a)>;
1006 def : Pat<(f32 (bitconvert RegI32:$a)), (MOVf32i32 RegI32:$a)>;
1008 // Conversion to f64
1009 def : Pat<(f64 (uint_to_fp RegPred:$a)), (SELPf64rr RegPred:$a,
1010 (MOVf64i64 0x3F80000000000000), (MOVf64i64 0))>;
1011 def : Pat<(f64 (uint_to_fp RegI16:$a)), (CVTf64u16 RndDefault, RegI16:$a)>;
1012 def : Pat<(f64 (sint_to_fp RegI16:$a)), (CVTf64s16 RndDefault, RegI16:$a)>;
1013 def : Pat<(f64 (uint_to_fp RegI32:$a)), (CVTf64u32 RndDefault, RegI32:$a)>;
1014 def : Pat<(f64 (sint_to_fp RegI32:$a)), (CVTf64s32 RndDefault, RegI32:$a)>;
1015 def : Pat<(f64 (uint_to_fp RegI64:$a)), (CVTf64u64 RndDefault, RegI64:$a)>;
1016 def : Pat<(f64 (sint_to_fp RegI64:$a)), (CVTf64s64 RndDefault, RegI64:$a)>;
1017 def : Pat<(f64 (fextend RegF32:$a)), (CVTf64f32 RegF32:$a)>;
1018 def : Pat<(f64 (bitconvert RegI64:$a)), (MOVf64i64 RegI64:$a)>;
1021 ///===- Intrinsic Instructions --------------------------------------------===//
1022 include "PTXIntrinsicInstrInfo.td"
1024 ///===- Load/Store Instructions -------------------------------------------===//
1025 include "PTXInstrLoadStore.td"