1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
28 // Shader Model Support
29 def SupportsSM13 : Predicate<"getSubtarget().supportsSM13()">;
30 def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
31 def SupportsSM20 : Predicate<"getSubtarget().supportsSM20()">;
32 def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
39 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
40 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
43 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
44 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
46 //===----------------------------------------------------------------------===//
47 // Instruction Pattern Stuff
48 //===----------------------------------------------------------------------===//
50 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
52 const PointerType *PT;
53 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
54 (PT = dyn_cast<PointerType>(Src->getType())))
55 return PT->getAddressSpace() == PTX::GLOBAL;
59 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
61 const PointerType *PT;
62 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
63 (PT = dyn_cast<PointerType>(Src->getType())))
64 return PT->getAddressSpace() == PTX::CONSTANT;
68 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
70 const PointerType *PT;
71 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
72 (PT = dyn_cast<PointerType>(Src->getType())))
73 return PT->getAddressSpace() == PTX::LOCAL;
77 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
79 const PointerType *PT;
80 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
81 (PT = dyn_cast<PointerType>(Src->getType())))
82 return PT->getAddressSpace() == PTX::PARAMETER;
86 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
88 const PointerType *PT;
89 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
90 (PT = dyn_cast<PointerType>(Src->getType())))
91 return PT->getAddressSpace() == PTX::SHARED;
96 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
98 const PointerType *PT;
99 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
100 (PT = dyn_cast<PointerType>(Src->getType())))
101 return PT->getAddressSpace() == PTX::GLOBAL;
106 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
108 const PointerType *PT;
109 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
110 (PT = dyn_cast<PointerType>(Src->getType())))
111 return PT->getAddressSpace() == PTX::LOCAL;
116 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
118 const PointerType *PT;
119 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
120 (PT = dyn_cast<PointerType>(Src->getType())))
121 return PT->getAddressSpace() == PTX::PARAMETER;
126 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
128 const PointerType *PT;
129 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
130 (PT = dyn_cast<PointerType>(Src->getType())))
131 return PT->getAddressSpace() == PTX::SHARED;
136 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
137 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
138 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
139 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
140 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
141 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
144 def MEMri32 : Operand<i32> {
145 let PrintMethod = "printMemOperand";
146 let MIOperandInfo = (ops RRegu32, i32imm);
148 def MEMri64 : Operand<i64> {
149 let PrintMethod = "printMemOperand";
150 let MIOperandInfo = (ops RRegu64, i64imm);
152 def MEMii32 : Operand<i32> {
153 let PrintMethod = "printMemOperand";
154 let MIOperandInfo = (ops i32imm, i32imm);
156 def MEMii64 : Operand<i64> {
157 let PrintMethod = "printMemOperand";
158 let MIOperandInfo = (ops i64imm, i64imm);
160 // The operand here does not correspond to an actual address, so we
161 // can use i32 in 64-bit address modes.
162 def MEMpi : Operand<i32> {
163 let PrintMethod = "printParamOperand";
164 let MIOperandInfo = (ops i32imm);
167 // Branch & call targets have OtherVT type.
168 def brtarget : Operand<OtherVT>;
169 def calltarget : Operand<i32>;
171 //===----------------------------------------------------------------------===//
172 // PTX Specific Node Definitions
173 //===----------------------------------------------------------------------===//
175 // PTX allow generic 3-reg shifts like shl r0, r1, r2
176 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
177 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
178 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
181 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
183 : SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
185 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
187 //===----------------------------------------------------------------------===//
188 // Instruction Class Templates
189 //===----------------------------------------------------------------------===//
191 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
192 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
193 def rr32 : InstPTX<(outs RRegf32:$d),
195 !strconcat(opcstr, ".f32\t$d, $a"),
196 [(set RRegf32:$d, (opnode RRegf32:$a))]>;
197 def ri32 : InstPTX<(outs RRegf32:$d),
199 !strconcat(opcstr, ".f32\t$d, $a"),
200 [(set RRegf32:$d, (opnode fpimm:$a))]>;
201 def rr64 : InstPTX<(outs RRegf64:$d),
203 !strconcat(opcstr, ".f64\t$d, $a"),
204 [(set RRegf64:$d, (opnode RRegf64:$a))]>;
205 def ri64 : InstPTX<(outs RRegf64:$d),
207 !strconcat(opcstr, ".f64\t$d, $a"),
208 [(set RRegf64:$d, (opnode fpimm:$a))]>;
211 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
212 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
213 def rr32 : InstPTX<(outs RRegf32:$d),
214 (ins RRegf32:$a, RRegf32:$b),
215 !strconcat(opcstr, ".f32\t$d, $a, $b"),
216 [(set RRegf32:$d, (opnode RRegf32:$a, RRegf32:$b))]>;
217 def ri32 : InstPTX<(outs RRegf32:$d),
218 (ins RRegf32:$a, f32imm:$b),
219 !strconcat(opcstr, ".f32\t$d, $a, $b"),
220 [(set RRegf32:$d, (opnode RRegf32:$a, fpimm:$b))]>;
221 def rr64 : InstPTX<(outs RRegf64:$d),
222 (ins RRegf64:$a, RRegf64:$b),
223 !strconcat(opcstr, ".f64\t$d, $a, $b"),
224 [(set RRegf64:$d, (opnode RRegf64:$a, RRegf64:$b))]>;
225 def ri64 : InstPTX<(outs RRegf64:$d),
226 (ins RRegf64:$a, f64imm:$b),
227 !strconcat(opcstr, ".f64\t$d, $a, $b"),
228 [(set RRegf64:$d, (opnode RRegf64:$a, fpimm:$b))]>;
231 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
232 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
233 def rrr32 : InstPTX<(outs RRegf32:$d),
234 (ins RRegf32:$a, RRegf32:$b, RRegf32:$c),
235 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
236 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
239 def rri32 : InstPTX<(outs RRegf32:$d),
240 (ins RRegf32:$a, RRegf32:$b, f32imm:$c),
241 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
242 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
245 def rrr64 : InstPTX<(outs RRegf64:$d),
246 (ins RRegf64:$a, RRegf64:$b, RRegf64:$c),
247 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
248 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
251 def rri64 : InstPTX<(outs RRegf64:$d),
252 (ins RRegf64:$a, RRegf64:$b, f64imm:$c),
253 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
254 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
259 multiclass INT3<string opcstr, SDNode opnode> {
260 def rr16 : InstPTX<(outs RRegu16:$d),
261 (ins RRegu16:$a, RRegu16:$b),
262 !strconcat(opcstr, ".u16\t$d, $a, $b"),
263 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
264 def ri16 : InstPTX<(outs RRegu16:$d),
265 (ins RRegu16:$a, i16imm:$b),
266 !strconcat(opcstr, ".u16\t$d, $a, $b"),
267 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
268 def rr32 : InstPTX<(outs RRegu32:$d),
269 (ins RRegu32:$a, RRegu32:$b),
270 !strconcat(opcstr, ".u32\t$d, $a, $b"),
271 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
272 def ri32 : InstPTX<(outs RRegu32:$d),
273 (ins RRegu32:$a, i32imm:$b),
274 !strconcat(opcstr, ".u32\t$d, $a, $b"),
275 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
276 def rr64 : InstPTX<(outs RRegu64:$d),
277 (ins RRegu64:$a, RRegu64:$b),
278 !strconcat(opcstr, ".u64\t$d, $a, $b"),
279 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
280 def ri64 : InstPTX<(outs RRegu64:$d),
281 (ins RRegu64:$a, i64imm:$b),
282 !strconcat(opcstr, ".u64\t$d, $a, $b"),
283 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
286 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
287 def ripreds : InstPTX<(outs Preds:$d),
288 (ins Preds:$a, i1imm:$b),
289 !strconcat(opcstr, ".pred\t$d, $a, $b"),
290 [(set Preds:$d, (opnode Preds:$a, imm:$b))]>;
291 def rrpreds : InstPTX<(outs Preds:$d),
292 (ins Preds:$a, Preds:$b),
293 !strconcat(opcstr, ".pred\t$d, $a, $b"),
294 [(set Preds:$d, (opnode Preds:$a, Preds:$b))]>;
295 def rr16 : InstPTX<(outs RRegu16:$d),
296 (ins RRegu16:$a, RRegu16:$b),
297 !strconcat(opcstr, ".b16\t$d, $a, $b"),
298 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
299 def ri16 : InstPTX<(outs RRegu16:$d),
300 (ins RRegu16:$a, i16imm:$b),
301 !strconcat(opcstr, ".b16\t$d, $a, $b"),
302 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
303 def rr32 : InstPTX<(outs RRegu32:$d),
304 (ins RRegu32:$a, RRegu32:$b),
305 !strconcat(opcstr, ".b32\t$d, $a, $b"),
306 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
307 def ri32 : InstPTX<(outs RRegu32:$d),
308 (ins RRegu32:$a, i32imm:$b),
309 !strconcat(opcstr, ".b32\t$d, $a, $b"),
310 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
311 def rr64 : InstPTX<(outs RRegu64:$d),
312 (ins RRegu64:$a, RRegu64:$b),
313 !strconcat(opcstr, ".b64\t$d, $a, $b"),
314 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
315 def ri64 : InstPTX<(outs RRegu64:$d),
316 (ins RRegu64:$a, i64imm:$b),
317 !strconcat(opcstr, ".b64\t$d, $a, $b"),
318 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
321 multiclass INT3ntnc<string opcstr, SDNode opnode> {
322 def rr16 : InstPTX<(outs RRegu16:$d),
323 (ins RRegu16:$a, RRegu16:$b),
324 !strconcat(opcstr, "16\t$d, $a, $b"),
325 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
326 def rr32 : InstPTX<(outs RRegu32:$d),
327 (ins RRegu32:$a, RRegu32:$b),
328 !strconcat(opcstr, "32\t$d, $a, $b"),
329 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
330 def rr64 : InstPTX<(outs RRegu64:$d),
331 (ins RRegu64:$a, RRegu64:$b),
332 !strconcat(opcstr, "64\t$d, $a, $b"),
333 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
334 def ri16 : InstPTX<(outs RRegu16:$d),
335 (ins RRegu16:$a, i16imm:$b),
336 !strconcat(opcstr, "16\t$d, $a, $b"),
337 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
338 def ri32 : InstPTX<(outs RRegu32:$d),
339 (ins RRegu32:$a, i32imm:$b),
340 !strconcat(opcstr, "32\t$d, $a, $b"),
341 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
342 def ri64 : InstPTX<(outs RRegu64:$d),
343 (ins RRegu64:$a, i64imm:$b),
344 !strconcat(opcstr, "64\t$d, $a, $b"),
345 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
346 def ir16 : InstPTX<(outs RRegu16:$d),
347 (ins i16imm:$a, RRegu16:$b),
348 !strconcat(opcstr, "16\t$d, $a, $b"),
349 [(set RRegu16:$d, (opnode imm:$a, RRegu16:$b))]>;
350 def ir32 : InstPTX<(outs RRegu32:$d),
351 (ins i32imm:$a, RRegu32:$b),
352 !strconcat(opcstr, "32\t$d, $a, $b"),
353 [(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
354 def ir64 : InstPTX<(outs RRegu64:$d),
355 (ins i64imm:$a, RRegu64:$b),
356 !strconcat(opcstr, "64\t$d, $a, $b"),
357 [(set RRegu64:$d, (opnode imm:$a, RRegu64:$b))]>;
360 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
361 CondCode cmp, string cmpstr> {
362 // TODO support 5-operand format: p|q, a, b, c
365 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
366 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
367 [(set Preds:$p, (setcc RC:$a, RC:$b, cmp))]>;
369 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b),
370 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
371 [(set Preds:$p, (setcc RC:$a, imm:$b, cmp))]>;
374 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
375 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
376 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
378 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
379 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
380 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
382 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
383 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
384 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
386 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
387 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
388 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
390 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
391 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
392 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
394 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
395 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
396 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
399 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
400 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
401 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
403 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
404 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
405 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
407 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
408 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
409 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
411 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
412 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
413 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
415 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
416 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
417 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
419 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
420 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
421 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
424 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
425 CondCode ucmp, CondCode ocmp, string cmpstr> {
426 // TODO support 5-operand format: p|q, a, b, c
429 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
430 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
431 [(set Preds:$p, (setcc RC:$a, RC:$b, ucmp))]>;
433 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
434 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
435 [(set Preds:$p, (setcc RC:$a, RC:$b, ocmp))]>;
438 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
439 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
440 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
442 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
443 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
444 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
447 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
448 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
449 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
451 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
452 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
453 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
456 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
457 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
458 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
460 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
461 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
462 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
465 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
466 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
467 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
469 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
470 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
471 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
474 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
475 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
476 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
478 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
479 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
480 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
483 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
484 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
485 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
487 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
488 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
489 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
492 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
494 : InstPTX<(outs RC:$r), (ins Preds:$a, RC:$b, RC:$c),
495 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
496 [(set RC:$r, (select Preds:$a, RC:$b, RC:$c))]>;
499 multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
500 def rr32 : InstPTX<(outs RC:$d),
502 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
503 [(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
504 def rr64 : InstPTX<(outs RC:$d),
506 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
507 [(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
508 def ri32 : InstPTX<(outs RC:$d),
510 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
511 [(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
512 def ri64 : InstPTX<(outs RC:$d),
514 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
515 [(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
516 def ii32 : InstPTX<(outs RC:$d),
518 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
519 [(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
520 def ii64 : InstPTX<(outs RC:$d),
522 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
523 [(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
526 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
527 defm u16 : PTX_LD<opstr, ".u16", RRegu16, pat_load>;
528 defm u32 : PTX_LD<opstr, ".u32", RRegu32, pat_load>;
529 defm u64 : PTX_LD<opstr, ".u64", RRegu64, pat_load>;
530 defm f32 : PTX_LD<opstr, ".f32", RRegf32, pat_load>;
531 defm f64 : PTX_LD<opstr, ".f64", RRegf64, pat_load>;
534 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
535 def rr32 : InstPTX<(outs),
536 (ins RC:$d, MEMri32:$a),
537 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
538 [(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
539 def rr64 : InstPTX<(outs),
540 (ins RC:$d, MEMri64:$a),
541 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
542 [(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
543 def ri32 : InstPTX<(outs),
544 (ins RC:$d, MEMri32:$a),
545 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
546 [(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
547 def ri64 : InstPTX<(outs),
548 (ins RC:$d, MEMri64:$a),
549 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
550 [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
551 def ii32 : InstPTX<(outs),
552 (ins RC:$d, MEMii32:$a),
553 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
554 [(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
555 def ii64 : InstPTX<(outs),
556 (ins RC:$d, MEMii64:$a),
557 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
558 [(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
561 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
562 defm u16 : PTX_ST<opstr, ".u16", RRegu16, pat_store>;
563 defm u32 : PTX_ST<opstr, ".u32", RRegu32, pat_store>;
564 defm u64 : PTX_ST<opstr, ".u64", RRegu64, pat_store>;
565 defm f32 : PTX_ST<opstr, ".f32", RRegf32, pat_store>;
566 defm f64 : PTX_ST<opstr, ".f64", RRegf64, pat_store>;
569 //===----------------------------------------------------------------------===//
571 //===----------------------------------------------------------------------===//
573 ///===- Integer Arithmetic Instructions -----------------------------------===//
575 defm ADD : INT3<"add", add>;
576 defm SUB : INT3<"sub", sub>;
577 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
578 defm DIV : INT3<"div", udiv>;
579 defm REM : INT3<"rem", urem>;
581 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
583 // Standard Unary Operations
584 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
586 // Standard Binary Operations
587 defm FADD : PTX_FLOAT_3OP<"add", fadd>;
588 defm FSUB : PTX_FLOAT_3OP<"sub", fsub>;
589 defm FMUL : PTX_FLOAT_3OP<"mul", fmul>;
591 // TODO: Allow user selection of rounding modes for fdiv.
592 // For division, we need to have f32 and f64 differently.
593 // For f32, we just always use .approx since it is supported on all hardware
594 // for PTX 1.4+, which is our minimum target.
595 def FDIVrr32 : InstPTX<(outs RRegf32:$d),
596 (ins RRegf32:$a, RRegf32:$b),
597 "div.approx.f32\t$d, $a, $b",
598 [(set RRegf32:$d, (fdiv RRegf32:$a, RRegf32:$b))]>;
599 def FDIVri32 : InstPTX<(outs RRegf32:$d),
600 (ins RRegf32:$a, f32imm:$b),
601 "div.approx.f32\t$d, $a, $b",
602 [(set RRegf32:$d, (fdiv RRegf32:$a, fpimm:$b))]>;
604 // For f64, we must specify a rounding for sm 1.3+ but *not* for sm 1.0.
605 def FDIVrr64SM13 : InstPTX<(outs RRegf64:$d),
606 (ins RRegf64:$a, RRegf64:$b),
607 "div.rn.f64\t$d, $a, $b",
608 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
609 Requires<[SupportsSM13]>;
610 def FDIVri64SM13 : InstPTX<(outs RRegf64:$d),
611 (ins RRegf64:$a, f64imm:$b),
612 "div.rn.f64\t$d, $a, $b",
613 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
614 Requires<[SupportsSM13]>;
615 def FDIVrr64SM10 : InstPTX<(outs RRegf64:$d),
616 (ins RRegf64:$a, RRegf64:$b),
617 "div.f64\t$d, $a, $b",
618 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
619 Requires<[DoesNotSupportSM13]>;
620 def FDIVri64SM10 : InstPTX<(outs RRegf64:$d),
621 (ins RRegf64:$a, f64imm:$b),
622 "div.f64\t$d, $a, $b",
623 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
624 Requires<[DoesNotSupportSM13]>;
628 // Multi-operation hybrid instructions
630 // The selection of mad/fma is tricky. In some cases, they are the *same*
631 // instruction, but in other cases we may prefer one or the other. Also,
632 // different PTX versions differ on whether rounding mode flags are required.
633 // In the short term, mad is supported on all PTX versions and we use a
634 // default rounding mode no matter what shader model or PTX version.
635 // TODO: Allow the rounding mode to be selectable through llc.
636 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13, SupportsFMA]>;
637 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13, SupportsFMA]>;
639 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
641 def FSQRT32 : InstPTX<(outs RRegf32:$d),
643 "sqrt.rn.f32\t$d, $a",
644 [(set RRegf32:$d, (fsqrt RRegf32:$a))]>;
646 def FSQRT64 : InstPTX<(outs RRegf64:$d),
648 "sqrt.rn.f64\t$d, $a",
649 [(set RRegf64:$d, (fsqrt RRegf64:$a))]>;
651 def FSIN32 : InstPTX<(outs RRegf32:$d),
653 "sin.approx.f32\t$d, $a",
654 [(set RRegf32:$d, (fsin RRegf32:$a))]>;
656 def FSIN64 : InstPTX<(outs RRegf64:$d),
658 "sin.approx.f64\t$d, $a",
659 [(set RRegf64:$d, (fsin RRegf64:$a))]>;
661 def FCOS32 : InstPTX<(outs RRegf32:$d),
663 "cos.approx.f32\t$d, $a",
664 [(set RRegf32:$d, (fcos RRegf32:$a))]>;
666 def FCOS64 : InstPTX<(outs RRegf64:$d),
668 "cos.approx.f64\t$d, $a",
669 [(set RRegf64:$d, (fcos RRegf64:$a))]>;
672 ///===- Comparison and Selection Instructions -----------------------------===//
678 defm SETPEQu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETEQ, "eq">;
679 defm SETPNEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETNE, "ne">;
680 defm SETPLTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULT, "lt">;
681 defm SETPLEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULE, "le">;
682 defm SETPGTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGT, "gt">;
683 defm SETPGEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGE, "ge">;
687 defm SETPEQu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETEQ, "eq">;
688 defm SETPNEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETNE, "ne">;
689 defm SETPLTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULT, "lt">;
690 defm SETPLEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULE, "le">;
691 defm SETPGTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGT, "gt">;
692 defm SETPGEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGE, "ge">;
696 defm SETPEQu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETEQ, "eq">;
697 defm SETPNEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETNE, "ne">;
698 defm SETPLTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULT, "lt">;
699 defm SETPLEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULE, "le">;
700 defm SETPGTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGT, "gt">;
701 defm SETPGEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGE, "ge">;
705 defm SETPEQf32 : PTX_SETP_FP<RRegf32, "f32", SETUEQ, SETOEQ, "eq">;
706 defm SETPNEf32 : PTX_SETP_FP<RRegf32, "f32", SETUNE, SETONE, "ne">;
707 defm SETPLTf32 : PTX_SETP_FP<RRegf32, "f32", SETULT, SETOLT, "lt">;
708 defm SETPLEf32 : PTX_SETP_FP<RRegf32, "f32", SETULE, SETOLE, "le">;
709 defm SETPGTf32 : PTX_SETP_FP<RRegf32, "f32", SETUGT, SETOGT, "gt">;
710 defm SETPGEf32 : PTX_SETP_FP<RRegf32, "f32", SETUGE, SETOGE, "ge">;
714 defm SETPEQf64 : PTX_SETP_FP<RRegf64, "f64", SETUEQ, SETOEQ, "eq">;
715 defm SETPNEf64 : PTX_SETP_FP<RRegf64, "f64", SETUNE, SETONE, "ne">;
716 defm SETPLTf64 : PTX_SETP_FP<RRegf64, "f64", SETULT, SETOLT, "lt">;
717 defm SETPLEf64 : PTX_SETP_FP<RRegf64, "f64", SETULE, SETOLE, "le">;
718 defm SETPGTf64 : PTX_SETP_FP<RRegf64, "f64", SETUGT, SETOGT, "gt">;
719 defm SETPGEf64 : PTX_SETP_FP<RRegf64, "f64", SETUGE, SETOGE, "ge">;
723 defm PTX_SELPu16 : PTX_SELP<RRegu16, "u16">;
724 defm PTX_SELPu32 : PTX_SELP<RRegu32, "u32">;
725 defm PTX_SELPu64 : PTX_SELP<RRegu64, "u64">;
726 defm PTX_SELPf32 : PTX_SELP<RRegf32, "f32">;
727 defm PTX_SELPf64 : PTX_SELP<RRegf64, "f64">;
729 ///===- Logic and Shift Instructions --------------------------------------===//
731 defm SHL : INT3ntnc<"shl.b", PTXshl>;
732 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
733 defm SRA : INT3ntnc<"shr.s", PTXsra>;
735 defm AND : PTX_LOGIC<"and", and>;
736 defm OR : PTX_LOGIC<"or", or>;
737 defm XOR : PTX_LOGIC<"xor", xor>;
739 ///===- Data Movement and Conversion Instructions -------------------------===//
741 let neverHasSideEffects = 1 in {
743 : InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
745 : InstPTX<(outs RRegu16:$d), (ins RRegu16:$a), "mov.u16\t$d, $a", []>;
747 : InstPTX<(outs RRegu32:$d), (ins RRegu32:$a), "mov.u32\t$d, $a", []>;
749 : InstPTX<(outs RRegu64:$d), (ins RRegu64:$a), "mov.u64\t$d, $a", []>;
751 : InstPTX<(outs RRegf32:$d), (ins RRegf32:$a), "mov.f32\t$d, $a", []>;
753 : InstPTX<(outs RRegf64:$d), (ins RRegf64:$a), "mov.f64\t$d, $a", []>;
756 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
758 : InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
759 [(set Preds:$d, imm:$a)]>;
761 : InstPTX<(outs RRegu16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
762 [(set RRegu16:$d, imm:$a)]>;
764 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
765 [(set RRegu32:$d, imm:$a)]>;
767 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
768 [(set RRegu64:$d, imm:$a)]>;
770 : InstPTX<(outs RRegf32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
771 [(set RRegf32:$d, fpimm:$a)]>;
773 : InstPTX<(outs RRegf64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
774 [(set RRegf64:$d, fpimm:$a)]>;
777 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
779 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
780 [(set RRegu32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
782 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
783 [(set RRegu64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
787 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
788 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
789 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
790 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
792 // This is a special instruction that is manually inserted for kernel parameters
793 def LDpiU16 : InstPTX<(outs RRegu16:$d), (ins MEMpi:$a),
794 "ld.param.u16\t$d, [$a]", []>;
795 def LDpiU32 : InstPTX<(outs RRegu32:$d), (ins MEMpi:$a),
796 "ld.param.u32\t$d, [$a]", []>;
797 def LDpiU64 : InstPTX<(outs RRegu64:$d), (ins MEMpi:$a),
798 "ld.param.u64\t$d, [$a]", []>;
799 def LDpiF32 : InstPTX<(outs RRegf32:$d), (ins MEMpi:$a),
800 "ld.param.f32\t$d, [$a]", []>;
801 def LDpiF64 : InstPTX<(outs RRegf64:$d), (ins MEMpi:$a),
802 "ld.param.f64\t$d, [$a]", []>;
805 defm STg : PTX_ST_ALL<"st.global", store_global>;
806 defm STl : PTX_ST_ALL<"st.local", store_local>;
807 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
809 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
810 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
811 // TODO: Do something with st.param if/when it is needed.
813 // Conversion to pred
816 : InstPTX<(outs Preds:$d), (ins RRegu16:$a), "cvt.pred.u16\t$d, $a",
817 [(set Preds:$d, (trunc RRegu16:$a))]>;
820 : InstPTX<(outs Preds:$d), (ins RRegu32:$a), "cvt.pred.u32\t$d, $a",
821 [(set Preds:$d, (trunc RRegu32:$a))]>;
824 : InstPTX<(outs Preds:$d), (ins RRegu64:$a), "cvt.pred.u64\t$d, $a",
825 [(set Preds:$d, (trunc RRegu64:$a))]>;
828 : InstPTX<(outs Preds:$d), (ins RRegf32:$a), "cvt.rni.pred.f32\t$d, $a",
829 [(set Preds:$d, (fp_to_uint RRegf32:$a))]>;
832 : InstPTX<(outs Preds:$d), (ins RRegf64:$a), "cvt.rni.pred.f64\t$d, $a",
833 [(set Preds:$d, (fp_to_uint RRegf64:$a))]>;
838 : InstPTX<(outs RRegu16:$d), (ins Preds:$a), "cvt.u16.pred\t$d, $a",
839 [(set RRegu16:$d, (zext Preds:$a))]>;
842 : InstPTX<(outs RRegu16:$d), (ins RRegu32:$a), "cvt.u16.u32\t$d, $a",
843 [(set RRegu16:$d, (trunc RRegu32:$a))]>;
846 : InstPTX<(outs RRegu16:$d), (ins RRegu64:$a), "cvt.u16.u64\t$d, $a",
847 [(set RRegu16:$d, (trunc RRegu64:$a))]>;
850 : InstPTX<(outs RRegu16:$d), (ins RRegf32:$a), "cvt.rni.u16.f32\t$d, $a",
851 [(set RRegu16:$d, (fp_to_uint RRegf32:$a))]>;
854 : InstPTX<(outs RRegu16:$d), (ins RRegf64:$a), "cvt.rni.u16.f64\t$d, $a",
855 [(set RRegu16:$d, (fp_to_uint RRegf64:$a))]>;
860 : InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
861 [(set RRegu32:$d, (zext Preds:$a))]>;
864 : InstPTX<(outs RRegu32:$d), (ins RRegu16:$a), "cvt.u32.u16\t$d, $a",
865 [(set RRegu32:$d, (zext RRegu16:$a))]>;
868 : InstPTX<(outs RRegu32:$d), (ins RRegu64:$a), "cvt.u32.u64\t$d, $a",
869 [(set RRegu32:$d, (trunc RRegu64:$a))]>;
872 : InstPTX<(outs RRegu32:$d), (ins RRegf32:$a), "cvt.rni.u32.f32\t$d, $a",
873 [(set RRegu32:$d, (fp_to_uint RRegf32:$a))]>;
876 : InstPTX<(outs RRegu32:$d), (ins RRegf64:$a), "cvt.rni.u32.f64\t$d, $a",
877 [(set RRegu32:$d, (fp_to_uint RRegf64:$a))]>;
882 : InstPTX<(outs RRegu64:$d), (ins Preds:$a), "cvt.u64.pred\t$d, $a",
883 [(set RRegu64:$d, (zext Preds:$a))]>;
886 : InstPTX<(outs RRegu64:$d), (ins RRegu16:$a), "cvt.u64.u16\t$d, $a",
887 [(set RRegu64:$d, (zext RRegu16:$a))]>;
890 : InstPTX<(outs RRegu64:$d), (ins RRegu32:$a), "cvt.u64.u32\t$d, $a",
891 [(set RRegu64:$d, (zext RRegu32:$a))]>;
894 : InstPTX<(outs RRegu64:$d), (ins RRegf32:$a), "cvt.rni.u64.f32\t$d, $a",
895 [(set RRegu64:$d, (fp_to_uint RRegf32:$a))]>;
898 : InstPTX<(outs RRegu64:$d), (ins RRegf64:$a), "cvt.rni.u64.f64\t$d, $a",
899 [(set RRegu64:$d, (fp_to_uint RRegf64:$a))]>;
904 : InstPTX<(outs RRegf32:$d), (ins Preds:$a), "cvt.rn.f32.pred\t$d, $a",
905 [(set RRegf32:$d, (uint_to_fp Preds:$a))]>;
908 : InstPTX<(outs RRegf32:$d), (ins RRegu16:$a), "cvt.rn.f32.u16\t$d, $a",
909 [(set RRegf32:$d, (uint_to_fp RRegu16:$a))]>;
912 : InstPTX<(outs RRegf32:$d), (ins RRegu32:$a), "cvt.rn.f32.u32\t$d, $a",
913 [(set RRegf32:$d, (uint_to_fp RRegu32:$a))]>;
916 : InstPTX<(outs RRegf32:$d), (ins RRegu64:$a), "cvt.rn.f32.u64\t$d, $a",
917 [(set RRegf32:$d, (uint_to_fp RRegu64:$a))]>;
920 : InstPTX<(outs RRegf32:$d), (ins RRegf64:$a), "cvt.rn.f32.f64\t$d, $a",
921 [(set RRegf32:$d, (fround RRegf64:$a))]>;
926 : InstPTX<(outs RRegf64:$d), (ins Preds:$a), "cvt.rn.f64.pred\t$d, $a",
927 [(set RRegf64:$d, (uint_to_fp Preds:$a))]>;
930 : InstPTX<(outs RRegf64:$d), (ins RRegu16:$a), "cvt.rn.f64.u16\t$d, $a",
931 [(set RRegf64:$d, (uint_to_fp RRegu16:$a))]>;
934 : InstPTX<(outs RRegf64:$d), (ins RRegu32:$a), "cvt.rn.f64.u32\t$d, $a",
935 [(set RRegf64:$d, (uint_to_fp RRegu32:$a))]>;
938 : InstPTX<(outs RRegf64:$d), (ins RRegu64:$a), "cvt.rn.f64.u64\t$d, $a",
939 [(set RRegf64:$d, (uint_to_fp RRegu64:$a))]>;
942 : InstPTX<(outs RRegf64:$d), (ins RRegf32:$a), "cvt.f64.f32\t$d, $a",
943 [(set RRegf64:$d, (fextend RRegf32:$a))]>;
945 ///===- Control Flow Instructions -----------------------------------------===//
947 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
949 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
952 let isBranch = 1, isTerminator = 1 in {
953 // FIXME: The pattern part is blank because I cannot (or do not yet know
954 // how to) use the first operand of PredicateOperand (a Preds register) here
956 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
957 [/*(brcond pred:$_p, bb:$d)*/]>;
960 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
961 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
962 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
965 ///===- Intrinsic Instructions --------------------------------------------===//
967 include "PTXIntrinsicInstrInfo.td"