1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
24 // Shader Model Support
25 def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">;
26 def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">;
27 def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">;
28 def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">;
30 // PTX Version Support
31 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
32 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
33 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
34 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
35 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
36 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
39 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
40 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
44 // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
45 // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
47 // def PTXcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PTXCallSeqStart,
48 // [SDNPHasChain, SDNPOutGlue]>;
49 // def PTXcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PTXCallSeqEnd,
50 // [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
52 def PTXcall : SDNode<"PTXISD::CALL", SDTNone,
53 [SDNPHasChain, SDNPVariadic, SDNPOptInGlue, SDNPOutGlue]>;
56 // Branch & call targets have OtherVT type.
57 def brtarget : Operand<OtherVT>;
58 def calltarget : Operand<i32>;
60 //===----------------------------------------------------------------------===//
61 // PTX Specific Node Definitions
62 //===----------------------------------------------------------------------===//
64 // PTX allow generic 3-reg shifts like shl r0, r1, r2
65 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
66 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
67 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
70 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
72 : SDNode<"PTXISD::RET", SDTNone,
73 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
75 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
79 //===----------------------------------------------------------------------===//
80 // Instruction Class Templates
81 //===----------------------------------------------------------------------===//
83 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
84 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
85 def rr32 : InstPTX<(outs RegF32:$d),
87 !strconcat(opcstr, ".f32\t$d, $a"),
88 [(set RegF32:$d, (opnode RegF32:$a))]>;
89 def ri32 : InstPTX<(outs RegF32:$d),
91 !strconcat(opcstr, ".f32\t$d, $a"),
92 [(set RegF32:$d, (opnode fpimm:$a))]>;
93 def rr64 : InstPTX<(outs RegF64:$d),
95 !strconcat(opcstr, ".f64\t$d, $a"),
96 [(set RegF64:$d, (opnode RegF64:$a))]>;
97 def ri64 : InstPTX<(outs RegF64:$d),
99 !strconcat(opcstr, ".f64\t$d, $a"),
100 [(set RegF64:$d, (opnode fpimm:$a))]>;
103 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
104 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
105 def rr32 : InstPTX<(outs RegF32:$d),
106 (ins RegF32:$a, RegF32:$b),
107 !strconcat(opcstr, ".f32\t$d, $a, $b"),
108 [(set RegF32:$d, (opnode RegF32:$a, RegF32:$b))]>;
109 def ri32 : InstPTX<(outs RegF32:$d),
110 (ins RegF32:$a, f32imm:$b),
111 !strconcat(opcstr, ".f32\t$d, $a, $b"),
112 [(set RegF32:$d, (opnode RegF32:$a, fpimm:$b))]>;
113 def rr64 : InstPTX<(outs RegF64:$d),
114 (ins RegF64:$a, RegF64:$b),
115 !strconcat(opcstr, ".f64\t$d, $a, $b"),
116 [(set RegF64:$d, (opnode RegF64:$a, RegF64:$b))]>;
117 def ri64 : InstPTX<(outs RegF64:$d),
118 (ins RegF64:$a, f64imm:$b),
119 !strconcat(opcstr, ".f64\t$d, $a, $b"),
120 [(set RegF64:$d, (opnode RegF64:$a, fpimm:$b))]>;
123 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
124 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
125 def rrr32 : InstPTX<(outs RegF32:$d),
126 (ins RegF32:$a, RegF32:$b, RegF32:$c),
127 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
128 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
131 def rri32 : InstPTX<(outs RegF32:$d),
132 (ins RegF32:$a, RegF32:$b, f32imm:$c),
133 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
134 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
137 def rrr64 : InstPTX<(outs RegF64:$d),
138 (ins RegF64:$a, RegF64:$b, RegF64:$c),
139 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
140 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
143 def rri64 : InstPTX<(outs RegF64:$d),
144 (ins RegF64:$a, RegF64:$b, f64imm:$c),
145 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
146 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
151 multiclass INT3<string opcstr, SDNode opnode> {
152 def rr16 : InstPTX<(outs RegI16:$d),
153 (ins RegI16:$a, RegI16:$b),
154 !strconcat(opcstr, ".u16\t$d, $a, $b"),
155 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
156 def ri16 : InstPTX<(outs RegI16:$d),
157 (ins RegI16:$a, i16imm:$b),
158 !strconcat(opcstr, ".u16\t$d, $a, $b"),
159 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
160 def rr32 : InstPTX<(outs RegI32:$d),
161 (ins RegI32:$a, RegI32:$b),
162 !strconcat(opcstr, ".u32\t$d, $a, $b"),
163 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
164 def ri32 : InstPTX<(outs RegI32:$d),
165 (ins RegI32:$a, i32imm:$b),
166 !strconcat(opcstr, ".u32\t$d, $a, $b"),
167 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
168 def rr64 : InstPTX<(outs RegI64:$d),
169 (ins RegI64:$a, RegI64:$b),
170 !strconcat(opcstr, ".u64\t$d, $a, $b"),
171 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
172 def ri64 : InstPTX<(outs RegI64:$d),
173 (ins RegI64:$a, i64imm:$b),
174 !strconcat(opcstr, ".u64\t$d, $a, $b"),
175 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
178 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
179 def ripreds : InstPTX<(outs RegPred:$d),
180 (ins RegPred:$a, i1imm:$b),
181 !strconcat(opcstr, ".pred\t$d, $a, $b"),
182 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
183 def rrpreds : InstPTX<(outs RegPred:$d),
184 (ins RegPred:$a, RegPred:$b),
185 !strconcat(opcstr, ".pred\t$d, $a, $b"),
186 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
187 def rr16 : InstPTX<(outs RegI16:$d),
188 (ins RegI16:$a, RegI16:$b),
189 !strconcat(opcstr, ".b16\t$d, $a, $b"),
190 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
191 def ri16 : InstPTX<(outs RegI16:$d),
192 (ins RegI16:$a, i16imm:$b),
193 !strconcat(opcstr, ".b16\t$d, $a, $b"),
194 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
195 def rr32 : InstPTX<(outs RegI32:$d),
196 (ins RegI32:$a, RegI32:$b),
197 !strconcat(opcstr, ".b32\t$d, $a, $b"),
198 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
199 def ri32 : InstPTX<(outs RegI32:$d),
200 (ins RegI32:$a, i32imm:$b),
201 !strconcat(opcstr, ".b32\t$d, $a, $b"),
202 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
203 def rr64 : InstPTX<(outs RegI64:$d),
204 (ins RegI64:$a, RegI64:$b),
205 !strconcat(opcstr, ".b64\t$d, $a, $b"),
206 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
207 def ri64 : InstPTX<(outs RegI64:$d),
208 (ins RegI64:$a, i64imm:$b),
209 !strconcat(opcstr, ".b64\t$d, $a, $b"),
210 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
213 multiclass INT3ntnc<string opcstr, SDNode opnode> {
214 def rr16 : InstPTX<(outs RegI16:$d),
215 (ins RegI16:$a, RegI16:$b),
216 !strconcat(opcstr, "16\t$d, $a, $b"),
217 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
218 def rr32 : InstPTX<(outs RegI32:$d),
219 (ins RegI32:$a, RegI32:$b),
220 !strconcat(opcstr, "32\t$d, $a, $b"),
221 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
222 def rr64 : InstPTX<(outs RegI64:$d),
223 (ins RegI64:$a, RegI64:$b),
224 !strconcat(opcstr, "64\t$d, $a, $b"),
225 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
226 def ri16 : InstPTX<(outs RegI16:$d),
227 (ins RegI16:$a, i16imm:$b),
228 !strconcat(opcstr, "16\t$d, $a, $b"),
229 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
230 def ri32 : InstPTX<(outs RegI32:$d),
231 (ins RegI32:$a, i32imm:$b),
232 !strconcat(opcstr, "32\t$d, $a, $b"),
233 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
234 def ri64 : InstPTX<(outs RegI64:$d),
235 (ins RegI64:$a, i64imm:$b),
236 !strconcat(opcstr, "64\t$d, $a, $b"),
237 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
238 def ir16 : InstPTX<(outs RegI16:$d),
239 (ins i16imm:$a, RegI16:$b),
240 !strconcat(opcstr, "16\t$d, $a, $b"),
241 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
242 def ir32 : InstPTX<(outs RegI32:$d),
243 (ins i32imm:$a, RegI32:$b),
244 !strconcat(opcstr, "32\t$d, $a, $b"),
245 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
246 def ir64 : InstPTX<(outs RegI64:$d),
247 (ins i64imm:$a, RegI64:$b),
248 !strconcat(opcstr, "64\t$d, $a, $b"),
249 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
252 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
253 CondCode cmp, string cmpstr> {
254 // TODO support 5-operand format: p|q, a, b, c
257 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
258 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
259 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
261 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
262 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
263 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
266 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
267 !strconcat("setp.", cmpstr, ".and.", regclsname,
269 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
271 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
272 !strconcat("setp.", cmpstr, ".and.", regclsname,
274 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
277 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
278 !strconcat("setp.", cmpstr, ".or.", regclsname,
280 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
282 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
283 !strconcat("setp.", cmpstr, ".or.", regclsname,
285 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
287 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
288 !strconcat("setp.", cmpstr, ".xor.", regclsname,
290 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
292 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
293 !strconcat("setp.", cmpstr, ".xor.", regclsname,
295 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
299 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
300 !strconcat("setp.", cmpstr, ".and.", regclsname,
301 "\t$p, $a, $b, !$c"),
302 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp),
303 (not RegPred:$c)))]>;
305 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
306 !strconcat("setp.", cmpstr, ".and.", regclsname,
307 "\t$p, $a, $b, !$c"),
308 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
309 (not RegPred:$c)))]>;
311 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
312 !strconcat("setp.", cmpstr, ".or.", regclsname,
313 "\t$p, $a, $b, !$c"),
314 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp),
315 (not RegPred:$c)))]>;
317 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
318 !strconcat("setp.", cmpstr, ".or.", regclsname,
319 "\t$p, $a, $b, !$c"),
320 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp),
321 (not RegPred:$c)))]>;
323 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
324 !strconcat("setp.", cmpstr, ".xor.", regclsname,
325 "\t$p, $a, $b, !$c"),
326 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp),
327 (not RegPred:$c)))]>;
329 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
330 !strconcat("setp.", cmpstr, ".xor.", regclsname,
331 "\t$p, $a, $b, !$c"),
332 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
333 (not RegPred:$c)))]>;
336 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
337 CondCode ucmp, CondCode ocmp, string cmpstr> {
338 // TODO support 5-operand format: p|q, a, b, c
341 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
342 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
343 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
345 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
346 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
347 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
350 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
351 !strconcat("setp.", cmpstr, "u.and.", regclsname,
353 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
356 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
357 !strconcat("setp.", cmpstr, ".and.", regclsname,
359 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
363 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
364 !strconcat("setp.", cmpstr, "u.or.", regclsname,
366 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
368 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
369 !strconcat("setp.", cmpstr, ".or.", regclsname,
371 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
374 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
375 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
377 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
380 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
381 !strconcat("setp.", cmpstr, ".xor.", regclsname,
383 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
387 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
388 !strconcat("setp.", cmpstr, "u.and.", regclsname,
389 "\t$p, $a, $b, !$c"),
390 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
391 (not RegPred:$c)))]>;
393 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
394 !strconcat("setp.", cmpstr, ".and.", regclsname,
395 "\t$p, $a, $b, !$c"),
396 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
397 (not RegPred:$c)))]>;
400 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
401 !strconcat("setp.", cmpstr, "u.or.", regclsname,
402 "\t$p, $a, $b, !$c"),
403 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp),
404 (not RegPred:$c)))]>;
406 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
407 !strconcat("setp.", cmpstr, ".or.", regclsname,
408 "\t$p, $a, $b, !$c"),
409 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp),
410 (not RegPred:$c)))]>;
413 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
414 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
415 "\t$p, $a, $b, !$c"),
416 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
417 (not RegPred:$c)))]>;
419 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
420 !strconcat("setp.", cmpstr, ".xor.", regclsname,
421 "\t$p, $a, $b, !$c"),
422 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
423 (not RegPred:$c)))]>;
426 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
428 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
429 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
430 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
435 //===----------------------------------------------------------------------===//
437 //===----------------------------------------------------------------------===//
439 ///===- Integer Arithmetic Instructions -----------------------------------===//
441 defm ADD : INT3<"add", add>;
442 defm SUB : INT3<"sub", sub>;
443 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
444 defm DIV : INT3<"div", udiv>;
445 defm REM : INT3<"rem", urem>;
447 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
449 // Standard Unary Operations
450 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
452 // Standard Binary Operations
453 defm FADD : PTX_FLOAT_3OP<"add.rn", fadd>;
454 defm FSUB : PTX_FLOAT_3OP<"sub.rn", fsub>;
455 defm FMUL : PTX_FLOAT_3OP<"mul.rn", fmul>;
457 // For floating-point division:
458 // SM_13+ defaults to .rn for f32 and f64,
459 // SM10 must *not* provide a rounding
462 // - Allow user selection of rounding modes for fdiv
463 // - Add support for -prec-div=false (.approx)
465 def FDIVrr32SM13 : InstPTX<(outs RegF32:$d),
466 (ins RegF32:$a, RegF32:$b),
467 "div.rn.f32\t$d, $a, $b",
468 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
469 Requires<[FDivNeedsRoundingMode]>;
470 def FDIVri32SM13 : InstPTX<(outs RegF32:$d),
471 (ins RegF32:$a, f32imm:$b),
472 "div.rn.f32\t$d, $a, $b",
473 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
474 Requires<[FDivNeedsRoundingMode]>;
475 def FDIVrr32SM10 : InstPTX<(outs RegF32:$d),
476 (ins RegF32:$a, RegF32:$b),
477 "div.f32\t$d, $a, $b",
478 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
479 Requires<[FDivNoRoundingMode]>;
480 def FDIVri32SM10 : InstPTX<(outs RegF32:$d),
481 (ins RegF32:$a, f32imm:$b),
482 "div.f32\t$d, $a, $b",
483 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
484 Requires<[FDivNoRoundingMode]>;
486 def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
487 (ins RegF64:$a, RegF64:$b),
488 "div.rn.f64\t$d, $a, $b",
489 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
490 Requires<[FDivNeedsRoundingMode]>;
491 def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
492 (ins RegF64:$a, f64imm:$b),
493 "div.rn.f64\t$d, $a, $b",
494 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
495 Requires<[FDivNeedsRoundingMode]>;
496 def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
497 (ins RegF64:$a, RegF64:$b),
498 "div.f64\t$d, $a, $b",
499 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
500 Requires<[FDivNoRoundingMode]>;
501 def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
502 (ins RegF64:$a, f64imm:$b),
503 "div.f64\t$d, $a, $b",
504 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
505 Requires<[FDivNoRoundingMode]>;
509 // Multi-operation hybrid instructions
511 // The selection of mad/fma is tricky. In some cases, they are the *same*
512 // instruction, but in other cases we may prefer one or the other. Also,
513 // different PTX versions differ on whether rounding mode flags are required.
514 // In the short term, mad is supported on all PTX versions and we use a
515 // default rounding mode no matter what shader model or PTX version.
516 // TODO: Allow the rounding mode to be selectable through llc.
517 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>,
518 Requires<[FMadNeedsRoundingMode, SupportsFMA]>;
519 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>,
520 Requires<[FMadNoRoundingMode, SupportsFMA]>;
522 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
524 def FSQRT32 : InstPTX<(outs RegF32:$d),
526 "sqrt.rn.f32\t$d, $a",
527 [(set RegF32:$d, (fsqrt RegF32:$a))]>;
529 def FSQRT64 : InstPTX<(outs RegF64:$d),
531 "sqrt.rn.f64\t$d, $a",
532 [(set RegF64:$d, (fsqrt RegF64:$a))]>;
534 def FSIN32 : InstPTX<(outs RegF32:$d),
536 "sin.approx.f32\t$d, $a",
537 [(set RegF32:$d, (fsin RegF32:$a))]>;
539 def FSIN64 : InstPTX<(outs RegF64:$d),
541 "sin.approx.f64\t$d, $a",
542 [(set RegF64:$d, (fsin RegF64:$a))]>;
544 def FCOS32 : InstPTX<(outs RegF32:$d),
546 "cos.approx.f32\t$d, $a",
547 [(set RegF32:$d, (fcos RegF32:$a))]>;
549 def FCOS64 : InstPTX<(outs RegF64:$d),
551 "cos.approx.f64\t$d, $a",
552 [(set RegF64:$d, (fcos RegF64:$a))]>;
555 ///===- Comparison and Selection Instructions -----------------------------===//
561 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
562 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
563 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
564 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
565 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
566 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
567 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">;
568 defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE, "le">;
569 defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT, "gt">;
570 defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE, "ge">;
574 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
575 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
576 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
577 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
578 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
579 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
580 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">;
581 defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE, "le">;
582 defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT, "gt">;
583 defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE, "ge">;
587 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
588 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
589 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
590 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
591 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
592 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
593 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">;
594 defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE, "le">;
595 defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT, "gt">;
596 defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">;
600 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", SETUEQ, SETOEQ, "eq">;
601 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", SETUNE, SETONE, "ne">;
602 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
603 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", SETULE, SETOLE, "le">;
604 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", SETUGT, SETOGT, "gt">;
605 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", SETUGE, SETOGE, "ge">;
609 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", SETUEQ, SETOEQ, "eq">;
610 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", SETUNE, SETONE, "ne">;
611 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
612 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", SETULE, SETOLE, "le">;
613 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", SETUGT, SETOGT, "gt">;
614 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", SETUGE, SETOGE, "ge">;
618 defm PTX_SELPu16 : PTX_SELP<RegI16, "u16">;
619 defm PTX_SELPu32 : PTX_SELP<RegI32, "u32">;
620 defm PTX_SELPu64 : PTX_SELP<RegI64, "u64">;
621 defm PTX_SELPf32 : PTX_SELP<RegF32, "f32">;
622 defm PTX_SELPf64 : PTX_SELP<RegF64, "f64">;
624 ///===- Logic and Shift Instructions --------------------------------------===//
626 defm SHL : INT3ntnc<"shl.b", PTXshl>;
627 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
628 defm SRA : INT3ntnc<"shr.s", PTXsra>;
630 defm AND : PTX_LOGIC<"and", and>;
631 defm OR : PTX_LOGIC<"or", or>;
632 defm XOR : PTX_LOGIC<"xor", xor>;
634 ///===- Data Movement and Conversion Instructions -------------------------===//
636 let neverHasSideEffects = 1 in {
638 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
640 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
642 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
644 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
646 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
648 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
651 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
653 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
654 [(set RegPred:$d, imm:$a)]>;
656 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
657 [(set RegI16:$d, imm:$a)]>;
659 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
660 [(set RegI32:$d, imm:$a)]>;
662 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
663 [(set RegI64:$d, imm:$a)]>;
665 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
666 [(set RegF32:$d, fpimm:$a)]>;
668 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
669 [(set RegF64:$d, fpimm:$a)]>;
672 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
674 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
675 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
677 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
678 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
682 // Conversion to pred
683 // PTX does not directly support converting to a predicate type, so we fake it
684 // by performing a greater-than test between the value and zero. This follows
685 // the C convention that any non-zero value is equivalent to 'true'.
687 : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
688 [(set RegPred:$d, (trunc RegI16:$a))]>;
691 : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
692 [(set RegPred:$d, (trunc RegI32:$a))]>;
695 : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
696 [(set RegPred:$d, (trunc RegI64:$a))]>;
699 : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
700 [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
703 : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
704 [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
707 // PTX does not directly support converting a predicate to a value, so we
708 // use a select instruction to select either 0 or 1 (integer or fp) based
709 // on the truth value of the predicate.
711 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
712 [(set RegI16:$d, (anyext RegPred:$a))]>;
715 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
716 [(set RegI16:$d, (zext RegPred:$a))]>;
719 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
720 [(set RegI16:$d, (sext RegPred:$a))]>;
723 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
724 [(set RegI16:$d, (trunc RegI32:$a))]>;
727 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a",
728 [(set RegI16:$d, (trunc RegI64:$a))]>;
731 : InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a",
732 [(set RegI16:$d, (fp_to_uint RegF32:$a))]>;
735 : InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a",
736 [(set RegI16:$d, (fp_to_uint RegF64:$a))]>;
741 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
742 [(set RegI32:$d, (zext RegPred:$a))]>;
745 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
746 [(set RegI32:$d, (anyext RegI16:$a))]>;
749 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
750 [(set RegI32:$d, (zext RegI16:$a))]>;
753 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
754 [(set RegI32:$d, (sext RegPred:$a))]>;
757 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
758 [(set RegI32:$d, (sext RegI16:$a))]>;
761 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
762 [(set RegI32:$d, (trunc RegI64:$a))]>;
765 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a",
766 [(set RegI32:$d, (fp_to_uint RegF32:$a))]>;
769 : InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a",
770 [(set RegI32:$d, (fp_to_uint RegF64:$a))]>;
775 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
776 [(set RegI64:$d, (zext RegPred:$a))]>;
779 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
780 [(set RegI64:$d, (sext RegPred:$a))]>;
783 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
784 [(set RegI64:$d, (zext RegI16:$a))]>;
787 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
788 [(set RegI64:$d, (sext RegI16:$a))]>;
791 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
792 [(set RegI64:$d, (zext RegI32:$a))]>;
795 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
796 [(set RegI64:$d, (sext RegI32:$a))]>;
799 : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a",
800 [(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
803 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a",
804 [(set RegI64:$d, (fp_to_uint RegF64:$a))]>;
809 : InstPTX<(outs RegF32:$d), (ins RegPred:$a),
810 "selp.f32\t$d, 0F3F800000, 0F00000000, $a", // 1.0
811 [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
814 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
815 [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
818 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a",
819 [(set RegF32:$d, (uint_to_fp RegI32:$a))]>;
822 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a",
823 [(set RegF32:$d, (uint_to_fp RegI64:$a))]>;
826 : InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
827 [(set RegF32:$d, (fround RegF64:$a))]>;
830 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.s16\t$d, $a",
831 [(set RegF32:$d, (sint_to_fp RegI16:$a))]>;
834 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.s32\t$d, $a",
835 [(set RegF32:$d, (sint_to_fp RegI32:$a))]>;
838 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.s64\t$d, $a",
839 [(set RegF32:$d, (sint_to_fp RegI64:$a))]>;
845 : InstPTX<(outs RegF64:$d), (ins RegPred:$a),
846 "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a", // 1.0
847 [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
850 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
851 [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
854 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a",
855 [(set RegF64:$d, (uint_to_fp RegI32:$a))]>;
858 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a",
859 [(set RegF64:$d, (uint_to_fp RegI64:$a))]>;
862 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
863 [(set RegF64:$d, (fextend RegF32:$a))]>;
866 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.s16\t$d, $a",
867 [(set RegF64:$d, (sint_to_fp RegI16:$a))]>;
870 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.s32\t$d, $a",
871 [(set RegF64:$d, (sint_to_fp RegI32:$a))]>;
874 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.s64\t$d, $a",
875 [(set RegF64:$d, (sint_to_fp RegI64:$a))]>;
877 // NOTE: These are temporarily here to help test some Clang-generated code.
878 // We really need to properly introduce anyext and bitconvert into the back-end.
880 def ANY_EXTEND_I64_I32
881 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
882 [(set RegI64:$d, (anyext RegI32:$a))]>;
886 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a",
887 [(set RegI32:$d, (bitconvert RegF32:$a))]>;
889 ///===- Control Flow Instructions -----------------------------------------===//
891 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
893 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
896 let isBranch = 1, isTerminator = 1 in {
897 // FIXME: The pattern part is blank because I cannot (or do not yet know
898 // how to) use the first operand of PredicateOperand (a RegPred register) here
900 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
901 [/*(brcond pred:$_p, bb:$d)*/]>;
904 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
905 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
906 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
909 let hasSideEffects = 1 in {
910 def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>;
913 ///===- Parameter Passing Pseudo-Instructions -----------------------------===//
915 def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b),
916 "mov.pred\t$a, %param$b", []>;
917 def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b),
918 "mov.b16\t$a, %param$b", []>;
919 def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b),
920 "mov.b32\t$a, %param$b", []>;
921 def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b),
922 "mov.b64\t$a, %param$b", []>;
923 def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b),
924 "mov.f32\t$a, %param$b", []>;
925 def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b),
926 "mov.f64\t$a, %param$b", []>;
928 def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>;
929 def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>;
930 def WRITEPARAMI32 : InstPTX<(outs), (ins RegI32:$a), "//w", []>;
931 def WRITEPARAMI64 : InstPTX<(outs), (ins RegI64:$a), "//w", []>;
932 def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>;
933 def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>;
935 ///===- Intrinsic Instructions --------------------------------------------===//
936 include "PTXIntrinsicInstrInfo.td"
938 ///===- Load/Store Instructions -------------------------------------------===//
939 include "PTXInstrLoadStore.td"