1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
28 // Shader Model Support
29 def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">;
30 def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">;
31 def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">;
32 def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
39 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
40 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
43 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
44 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
46 //===----------------------------------------------------------------------===//
47 // Instruction Pattern Stuff
48 //===----------------------------------------------------------------------===//
50 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
52 const PointerType *PT;
53 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
54 (PT = dyn_cast<PointerType>(Src->getType())))
55 return PT->getAddressSpace() == PTX::GLOBAL;
59 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
61 const PointerType *PT;
62 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
63 (PT = dyn_cast<PointerType>(Src->getType())))
64 return PT->getAddressSpace() == PTX::CONSTANT;
68 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
70 const PointerType *PT;
71 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
72 (PT = dyn_cast<PointerType>(Src->getType())))
73 return PT->getAddressSpace() == PTX::LOCAL;
77 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
79 const PointerType *PT;
80 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
81 (PT = dyn_cast<PointerType>(Src->getType())))
82 return PT->getAddressSpace() == PTX::PARAMETER;
86 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
88 const PointerType *PT;
89 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
90 (PT = dyn_cast<PointerType>(Src->getType())))
91 return PT->getAddressSpace() == PTX::SHARED;
96 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
98 const PointerType *PT;
99 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
100 (PT = dyn_cast<PointerType>(Src->getType())))
101 return PT->getAddressSpace() == PTX::GLOBAL;
106 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
108 const PointerType *PT;
109 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
110 (PT = dyn_cast<PointerType>(Src->getType())))
111 return PT->getAddressSpace() == PTX::LOCAL;
116 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
118 const PointerType *PT;
119 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
120 (PT = dyn_cast<PointerType>(Src->getType())))
121 return PT->getAddressSpace() == PTX::PARAMETER;
126 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
128 const PointerType *PT;
129 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
130 (PT = dyn_cast<PointerType>(Src->getType())))
131 return PT->getAddressSpace() == PTX::SHARED;
136 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
137 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
138 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
139 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
140 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
141 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
144 def MEMri32 : Operand<i32> {
145 let PrintMethod = "printMemOperand";
146 let MIOperandInfo = (ops RegI32, i32imm);
148 def MEMri64 : Operand<i64> {
149 let PrintMethod = "printMemOperand";
150 let MIOperandInfo = (ops RegI64, i64imm);
152 def MEMii32 : Operand<i32> {
153 let PrintMethod = "printMemOperand";
154 let MIOperandInfo = (ops i32imm, i32imm);
156 def MEMii64 : Operand<i64> {
157 let PrintMethod = "printMemOperand";
158 let MIOperandInfo = (ops i64imm, i64imm);
160 // The operand here does not correspond to an actual address, so we
161 // can use i32 in 64-bit address modes.
162 def MEMpi : Operand<i32> {
163 let PrintMethod = "printParamOperand";
164 let MIOperandInfo = (ops i32imm);
166 def MEMret : Operand<i32> {
167 let PrintMethod = "printReturnOperand";
168 let MIOperandInfo = (ops i32imm);
171 // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
172 // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
174 // def PTXcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PTXCallSeqStart,
175 // [SDNPHasChain, SDNPOutGlue]>;
176 // def PTXcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PTXCallSeqEnd,
177 // [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
179 def PTXcall : SDNode<"PTXISD::CALL", SDTNone,
180 [SDNPHasChain, SDNPVariadic, SDNPOptInGlue, SDNPOutGlue]>;
183 // Branch & call targets have OtherVT type.
184 def brtarget : Operand<OtherVT>;
185 def calltarget : Operand<i32>;
187 //===----------------------------------------------------------------------===//
188 // PTX Specific Node Definitions
189 //===----------------------------------------------------------------------===//
191 // PTX allow generic 3-reg shifts like shl r0, r1, r2
192 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
193 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
194 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
197 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
199 : SDNode<"PTXISD::RET", SDTNone,
200 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
202 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
204 // Load/store .param space
206 : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>,
207 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
209 : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>,
210 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
213 : SDNode<"PTXISD::READ_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>,
214 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
216 : SDNode<"PTXISD::WRITE_PARAM", SDTypeProfile<0, 1, []>,
217 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
219 //===----------------------------------------------------------------------===//
220 // Instruction Class Templates
221 //===----------------------------------------------------------------------===//
223 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
224 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
225 def rr32 : InstPTX<(outs RegF32:$d),
227 !strconcat(opcstr, ".f32\t$d, $a"),
228 [(set RegF32:$d, (opnode RegF32:$a))]>;
229 def ri32 : InstPTX<(outs RegF32:$d),
231 !strconcat(opcstr, ".f32\t$d, $a"),
232 [(set RegF32:$d, (opnode fpimm:$a))]>;
233 def rr64 : InstPTX<(outs RegF64:$d),
235 !strconcat(opcstr, ".f64\t$d, $a"),
236 [(set RegF64:$d, (opnode RegF64:$a))]>;
237 def ri64 : InstPTX<(outs RegF64:$d),
239 !strconcat(opcstr, ".f64\t$d, $a"),
240 [(set RegF64:$d, (opnode fpimm:$a))]>;
243 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
244 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
245 def rr32 : InstPTX<(outs RegF32:$d),
246 (ins RegF32:$a, RegF32:$b),
247 !strconcat(opcstr, ".f32\t$d, $a, $b"),
248 [(set RegF32:$d, (opnode RegF32:$a, RegF32:$b))]>;
249 def ri32 : InstPTX<(outs RegF32:$d),
250 (ins RegF32:$a, f32imm:$b),
251 !strconcat(opcstr, ".f32\t$d, $a, $b"),
252 [(set RegF32:$d, (opnode RegF32:$a, fpimm:$b))]>;
253 def rr64 : InstPTX<(outs RegF64:$d),
254 (ins RegF64:$a, RegF64:$b),
255 !strconcat(opcstr, ".f64\t$d, $a, $b"),
256 [(set RegF64:$d, (opnode RegF64:$a, RegF64:$b))]>;
257 def ri64 : InstPTX<(outs RegF64:$d),
258 (ins RegF64:$a, f64imm:$b),
259 !strconcat(opcstr, ".f64\t$d, $a, $b"),
260 [(set RegF64:$d, (opnode RegF64:$a, fpimm:$b))]>;
263 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
264 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
265 def rrr32 : InstPTX<(outs RegF32:$d),
266 (ins RegF32:$a, RegF32:$b, RegF32:$c),
267 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
268 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
271 def rri32 : InstPTX<(outs RegF32:$d),
272 (ins RegF32:$a, RegF32:$b, f32imm:$c),
273 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
274 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
277 def rrr64 : InstPTX<(outs RegF64:$d),
278 (ins RegF64:$a, RegF64:$b, RegF64:$c),
279 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
280 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
283 def rri64 : InstPTX<(outs RegF64:$d),
284 (ins RegF64:$a, RegF64:$b, f64imm:$c),
285 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
286 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
291 multiclass INT3<string opcstr, SDNode opnode> {
292 def rr16 : InstPTX<(outs RegI16:$d),
293 (ins RegI16:$a, RegI16:$b),
294 !strconcat(opcstr, ".u16\t$d, $a, $b"),
295 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
296 def ri16 : InstPTX<(outs RegI16:$d),
297 (ins RegI16:$a, i16imm:$b),
298 !strconcat(opcstr, ".u16\t$d, $a, $b"),
299 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
300 def rr32 : InstPTX<(outs RegI32:$d),
301 (ins RegI32:$a, RegI32:$b),
302 !strconcat(opcstr, ".u32\t$d, $a, $b"),
303 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
304 def ri32 : InstPTX<(outs RegI32:$d),
305 (ins RegI32:$a, i32imm:$b),
306 !strconcat(opcstr, ".u32\t$d, $a, $b"),
307 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
308 def rr64 : InstPTX<(outs RegI64:$d),
309 (ins RegI64:$a, RegI64:$b),
310 !strconcat(opcstr, ".u64\t$d, $a, $b"),
311 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
312 def ri64 : InstPTX<(outs RegI64:$d),
313 (ins RegI64:$a, i64imm:$b),
314 !strconcat(opcstr, ".u64\t$d, $a, $b"),
315 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
318 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
319 def ripreds : InstPTX<(outs RegPred:$d),
320 (ins RegPred:$a, i1imm:$b),
321 !strconcat(opcstr, ".pred\t$d, $a, $b"),
322 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
323 def rrpreds : InstPTX<(outs RegPred:$d),
324 (ins RegPred:$a, RegPred:$b),
325 !strconcat(opcstr, ".pred\t$d, $a, $b"),
326 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
327 def rr16 : InstPTX<(outs RegI16:$d),
328 (ins RegI16:$a, RegI16:$b),
329 !strconcat(opcstr, ".b16\t$d, $a, $b"),
330 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
331 def ri16 : InstPTX<(outs RegI16:$d),
332 (ins RegI16:$a, i16imm:$b),
333 !strconcat(opcstr, ".b16\t$d, $a, $b"),
334 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
335 def rr32 : InstPTX<(outs RegI32:$d),
336 (ins RegI32:$a, RegI32:$b),
337 !strconcat(opcstr, ".b32\t$d, $a, $b"),
338 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
339 def ri32 : InstPTX<(outs RegI32:$d),
340 (ins RegI32:$a, i32imm:$b),
341 !strconcat(opcstr, ".b32\t$d, $a, $b"),
342 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
343 def rr64 : InstPTX<(outs RegI64:$d),
344 (ins RegI64:$a, RegI64:$b),
345 !strconcat(opcstr, ".b64\t$d, $a, $b"),
346 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
347 def ri64 : InstPTX<(outs RegI64:$d),
348 (ins RegI64:$a, i64imm:$b),
349 !strconcat(opcstr, ".b64\t$d, $a, $b"),
350 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
353 multiclass INT3ntnc<string opcstr, SDNode opnode> {
354 def rr16 : InstPTX<(outs RegI16:$d),
355 (ins RegI16:$a, RegI16:$b),
356 !strconcat(opcstr, "16\t$d, $a, $b"),
357 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
358 def rr32 : InstPTX<(outs RegI32:$d),
359 (ins RegI32:$a, RegI32:$b),
360 !strconcat(opcstr, "32\t$d, $a, $b"),
361 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
362 def rr64 : InstPTX<(outs RegI64:$d),
363 (ins RegI64:$a, RegI64:$b),
364 !strconcat(opcstr, "64\t$d, $a, $b"),
365 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
366 def ri16 : InstPTX<(outs RegI16:$d),
367 (ins RegI16:$a, i16imm:$b),
368 !strconcat(opcstr, "16\t$d, $a, $b"),
369 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
370 def ri32 : InstPTX<(outs RegI32:$d),
371 (ins RegI32:$a, i32imm:$b),
372 !strconcat(opcstr, "32\t$d, $a, $b"),
373 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
374 def ri64 : InstPTX<(outs RegI64:$d),
375 (ins RegI64:$a, i64imm:$b),
376 !strconcat(opcstr, "64\t$d, $a, $b"),
377 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
378 def ir16 : InstPTX<(outs RegI16:$d),
379 (ins i16imm:$a, RegI16:$b),
380 !strconcat(opcstr, "16\t$d, $a, $b"),
381 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
382 def ir32 : InstPTX<(outs RegI32:$d),
383 (ins i32imm:$a, RegI32:$b),
384 !strconcat(opcstr, "32\t$d, $a, $b"),
385 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
386 def ir64 : InstPTX<(outs RegI64:$d),
387 (ins i64imm:$a, RegI64:$b),
388 !strconcat(opcstr, "64\t$d, $a, $b"),
389 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
392 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
393 CondCode cmp, string cmpstr> {
394 // TODO support 5-operand format: p|q, a, b, c
397 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
398 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
399 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
401 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
402 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
403 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
406 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
407 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
408 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
410 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
411 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
412 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
414 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
415 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
416 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
418 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
419 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
420 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
422 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
423 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
424 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
426 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
427 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
428 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
431 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
432 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
433 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
435 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
436 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
437 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
439 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
440 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
441 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
443 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
444 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
445 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
447 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
448 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
449 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
451 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
452 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
453 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
456 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
457 CondCode ucmp, CondCode ocmp, string cmpstr> {
458 // TODO support 5-operand format: p|q, a, b, c
461 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
462 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
463 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
465 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
466 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
467 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
470 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
471 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
472 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
474 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
475 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
476 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
479 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
480 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
481 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
483 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
484 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
485 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
488 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
489 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
490 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
492 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
493 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
494 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
497 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
498 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
499 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
501 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
502 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
503 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
506 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
507 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
508 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
510 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
511 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
512 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
515 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
516 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
517 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
519 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
520 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
521 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
524 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
526 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
527 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
528 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
531 multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
532 def rr32 : InstPTX<(outs RC:$d),
534 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
535 [(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
536 def rr64 : InstPTX<(outs RC:$d),
538 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
539 [(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
540 def ri32 : InstPTX<(outs RC:$d),
542 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
543 [(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
544 def ri64 : InstPTX<(outs RC:$d),
546 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
547 [(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
548 def ii32 : InstPTX<(outs RC:$d),
550 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
551 [(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
552 def ii64 : InstPTX<(outs RC:$d),
554 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
555 [(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
558 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
559 defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
560 defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
561 defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
562 defm f32 : PTX_LD<opstr, ".f32", RegF32, pat_load>;
563 defm f64 : PTX_LD<opstr, ".f64", RegF64, pat_load>;
566 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
567 def rr32 : InstPTX<(outs),
568 (ins RC:$d, MEMri32:$a),
569 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
570 [(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
571 def rr64 : InstPTX<(outs),
572 (ins RC:$d, MEMri64:$a),
573 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
574 [(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
575 def ri32 : InstPTX<(outs),
576 (ins RC:$d, MEMri32:$a),
577 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
578 [(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
579 def ri64 : InstPTX<(outs),
580 (ins RC:$d, MEMri64:$a),
581 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
582 [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
583 def ii32 : InstPTX<(outs),
584 (ins RC:$d, MEMii32:$a),
585 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
586 [(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
587 def ii64 : InstPTX<(outs),
588 (ins RC:$d, MEMii64:$a),
589 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
590 [(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
593 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
594 defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
595 defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
596 defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
597 defm f32 : PTX_ST<opstr, ".f32", RegF32, pat_store>;
598 defm f64 : PTX_ST<opstr, ".f64", RegF64, pat_store>;
601 //===----------------------------------------------------------------------===//
603 //===----------------------------------------------------------------------===//
605 ///===- Integer Arithmetic Instructions -----------------------------------===//
607 defm ADD : INT3<"add", add>;
608 defm SUB : INT3<"sub", sub>;
609 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
610 defm DIV : INT3<"div", udiv>;
611 defm REM : INT3<"rem", urem>;
613 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
615 // Standard Unary Operations
616 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
618 // Standard Binary Operations
619 defm FADD : PTX_FLOAT_3OP<"add.rn", fadd>;
620 defm FSUB : PTX_FLOAT_3OP<"sub.rn", fsub>;
621 defm FMUL : PTX_FLOAT_3OP<"mul.rn", fmul>;
623 // For floating-point division:
624 // SM_13+ defaults to .rn for f32 and f64,
625 // SM10 must *not* provide a rounding
628 // - Allow user selection of rounding modes for fdiv
629 // - Add support for -prec-div=false (.approx)
631 def FDIVrr32SM13 : InstPTX<(outs RegF32:$d),
632 (ins RegF32:$a, RegF32:$b),
633 "div.rn.f32\t$d, $a, $b",
634 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
635 Requires<[FDivNeedsRoundingMode]>;
636 def FDIVri32SM13 : InstPTX<(outs RegF32:$d),
637 (ins RegF32:$a, f32imm:$b),
638 "div.rn.f32\t$d, $a, $b",
639 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
640 Requires<[FDivNeedsRoundingMode]>;
641 def FDIVrr32SM10 : InstPTX<(outs RegF32:$d),
642 (ins RegF32:$a, RegF32:$b),
643 "div.f32\t$d, $a, $b",
644 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
645 Requires<[FDivNoRoundingMode]>;
646 def FDIVri32SM10 : InstPTX<(outs RegF32:$d),
647 (ins RegF32:$a, f32imm:$b),
648 "div.f32\t$d, $a, $b",
649 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
650 Requires<[FDivNoRoundingMode]>;
652 def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
653 (ins RegF64:$a, RegF64:$b),
654 "div.rn.f64\t$d, $a, $b",
655 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
656 Requires<[FDivNeedsRoundingMode]>;
657 def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
658 (ins RegF64:$a, f64imm:$b),
659 "div.rn.f64\t$d, $a, $b",
660 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
661 Requires<[FDivNeedsRoundingMode]>;
662 def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
663 (ins RegF64:$a, RegF64:$b),
664 "div.f64\t$d, $a, $b",
665 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
666 Requires<[FDivNoRoundingMode]>;
667 def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
668 (ins RegF64:$a, f64imm:$b),
669 "div.f64\t$d, $a, $b",
670 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
671 Requires<[FDivNoRoundingMode]>;
675 // Multi-operation hybrid instructions
677 // The selection of mad/fma is tricky. In some cases, they are the *same*
678 // instruction, but in other cases we may prefer one or the other. Also,
679 // different PTX versions differ on whether rounding mode flags are required.
680 // In the short term, mad is supported on all PTX versions and we use a
681 // default rounding mode no matter what shader model or PTX version.
682 // TODO: Allow the rounding mode to be selectable through llc.
683 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>,
684 Requires<[FMadNeedsRoundingMode, SupportsFMA]>;
685 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>,
686 Requires<[FMadNoRoundingMode, SupportsFMA]>;
688 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
690 def FSQRT32 : InstPTX<(outs RegF32:$d),
692 "sqrt.rn.f32\t$d, $a",
693 [(set RegF32:$d, (fsqrt RegF32:$a))]>;
695 def FSQRT64 : InstPTX<(outs RegF64:$d),
697 "sqrt.rn.f64\t$d, $a",
698 [(set RegF64:$d, (fsqrt RegF64:$a))]>;
700 def FSIN32 : InstPTX<(outs RegF32:$d),
702 "sin.approx.f32\t$d, $a",
703 [(set RegF32:$d, (fsin RegF32:$a))]>;
705 def FSIN64 : InstPTX<(outs RegF64:$d),
707 "sin.approx.f64\t$d, $a",
708 [(set RegF64:$d, (fsin RegF64:$a))]>;
710 def FCOS32 : InstPTX<(outs RegF32:$d),
712 "cos.approx.f32\t$d, $a",
713 [(set RegF32:$d, (fcos RegF32:$a))]>;
715 def FCOS64 : InstPTX<(outs RegF64:$d),
717 "cos.approx.f64\t$d, $a",
718 [(set RegF64:$d, (fcos RegF64:$a))]>;
721 ///===- Comparison and Selection Instructions -----------------------------===//
727 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
728 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
729 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
730 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
731 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
732 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
733 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">;
734 defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE, "le">;
735 defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT, "gt">;
736 defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE, "ge">;
740 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
741 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
742 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
743 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
744 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
745 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
746 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">;
747 defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE, "le">;
748 defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT, "gt">;
749 defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE, "ge">;
753 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
754 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
755 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
756 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
757 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
758 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
759 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">;
760 defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE, "le">;
761 defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT, "gt">;
762 defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">;
766 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", SETUEQ, SETOEQ, "eq">;
767 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", SETUNE, SETONE, "ne">;
768 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
769 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", SETULE, SETOLE, "le">;
770 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", SETUGT, SETOGT, "gt">;
771 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", SETUGE, SETOGE, "ge">;
775 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", SETUEQ, SETOEQ, "eq">;
776 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", SETUNE, SETONE, "ne">;
777 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
778 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", SETULE, SETOLE, "le">;
779 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", SETUGT, SETOGT, "gt">;
780 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", SETUGE, SETOGE, "ge">;
784 defm PTX_SELPu16 : PTX_SELP<RegI16, "u16">;
785 defm PTX_SELPu32 : PTX_SELP<RegI32, "u32">;
786 defm PTX_SELPu64 : PTX_SELP<RegI64, "u64">;
787 defm PTX_SELPf32 : PTX_SELP<RegF32, "f32">;
788 defm PTX_SELPf64 : PTX_SELP<RegF64, "f64">;
790 ///===- Logic and Shift Instructions --------------------------------------===//
792 defm SHL : INT3ntnc<"shl.b", PTXshl>;
793 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
794 defm SRA : INT3ntnc<"shr.s", PTXsra>;
796 defm AND : PTX_LOGIC<"and", and>;
797 defm OR : PTX_LOGIC<"or", or>;
798 defm XOR : PTX_LOGIC<"xor", xor>;
800 ///===- Data Movement and Conversion Instructions -------------------------===//
802 let neverHasSideEffects = 1 in {
804 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
806 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
808 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
810 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
812 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
814 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
817 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
819 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
820 [(set RegPred:$d, imm:$a)]>;
822 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
823 [(set RegI16:$d, imm:$a)]>;
825 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
826 [(set RegI32:$d, imm:$a)]>;
828 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
829 [(set RegI64:$d, imm:$a)]>;
831 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
832 [(set RegF32:$d, fpimm:$a)]>;
834 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
835 [(set RegF64:$d, fpimm:$a)]>;
838 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
840 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
841 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
843 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
844 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
848 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
849 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
850 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
851 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
853 // These instructions are used to load/store from the .param space for
854 // device and kernel parameters
856 let hasSideEffects = 1 in {
857 def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
858 "ld.param.pred\t$d, [$a]",
859 [(set RegPred:$d, (PTXloadparam timm:$a))]>;
860 def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
861 "ld.param.u16\t$d, [$a]",
862 [(set RegI16:$d, (PTXloadparam timm:$a))]>;
863 def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
864 "ld.param.u32\t$d, [$a]",
865 [(set RegI32:$d, (PTXloadparam timm:$a))]>;
866 def LDpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
867 "ld.param.u64\t$d, [$a]",
868 [(set RegI64:$d, (PTXloadparam timm:$a))]>;
869 def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
870 "ld.param.f32\t$d, [$a]",
871 [(set RegF32:$d, (PTXloadparam timm:$a))]>;
872 def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
873 "ld.param.f64\t$d, [$a]",
874 [(set RegF64:$d, (PTXloadparam timm:$a))]>;
876 def STpiPred : InstPTX<(outs), (ins MEMpi:$d, RegPred:$a),
877 "st.param.pred\t[$d], $a",
878 [(PTXstoreparam timm:$d, RegPred:$a)]>;
879 def STpiU16 : InstPTX<(outs), (ins MEMpi:$d, RegI16:$a),
880 "st.param.u16\t[$d], $a",
881 [(PTXstoreparam timm:$d, RegI16:$a)]>;
882 def STpiU32 : InstPTX<(outs), (ins MEMpi:$d, RegI32:$a),
883 "st.param.u32\t[$d], $a",
884 [(PTXstoreparam timm:$d, RegI32:$a)]>;
885 def STpiU64 : InstPTX<(outs), (ins MEMpi:$d, RegI64:$a),
886 "st.param.u64\t[$d], $a",
887 [(PTXstoreparam timm:$d, RegI64:$a)]>;
888 def STpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a),
889 "st.param.f32\t[$d], $a",
890 [(PTXstoreparam timm:$d, RegF32:$a)]>;
891 def STpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a),
892 "st.param.f64\t[$d], $a",
893 [(PTXstoreparam timm:$d, RegF64:$a)]>;
897 defm STg : PTX_ST_ALL<"st.global", store_global>;
898 defm STl : PTX_ST_ALL<"st.local", store_local>;
899 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
901 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
902 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
903 // TODO: Do something with st.param if/when it is needed.
905 // Conversion to pred
906 // PTX does not directly support converting to a predicate type, so we fake it
907 // by performing a greater-than test between the value and zero. This follows
908 // the C convention that any non-zero value is equivalent to 'true'.
910 : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
911 [(set RegPred:$d, (trunc RegI16:$a))]>;
914 : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
915 [(set RegPred:$d, (trunc RegI32:$a))]>;
918 : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
919 [(set RegPred:$d, (trunc RegI64:$a))]>;
922 : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
923 [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
926 : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
927 [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
930 // PTX does not directly support converting a predicate to a value, so we
931 // use a select instruction to select either 0 or 1 (integer or fp) based
932 // on the truth value of the predicate.
934 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
935 [(set RegI16:$d, (anyext RegPred:$a))]>;
938 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
939 [(set RegI16:$d, (zext RegPred:$a))]>;
942 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
943 [(set RegI16:$d, (sext RegPred:$a))]>;
946 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
947 [(set RegI16:$d, (trunc RegI32:$a))]>;
950 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a",
951 [(set RegI16:$d, (trunc RegI64:$a))]>;
954 : InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a",
955 [(set RegI16:$d, (fp_to_uint RegF32:$a))]>;
958 : InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a",
959 [(set RegI16:$d, (fp_to_uint RegF64:$a))]>;
964 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
965 [(set RegI32:$d, (zext RegPred:$a))]>;
968 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
969 [(set RegI32:$d, (anyext RegI16:$a))]>;
972 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
973 [(set RegI32:$d, (zext RegI16:$a))]>;
976 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
977 [(set RegI32:$d, (sext RegPred:$a))]>;
980 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
981 [(set RegI32:$d, (sext RegI16:$a))]>;
984 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
985 [(set RegI32:$d, (trunc RegI64:$a))]>;
988 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a",
989 [(set RegI32:$d, (fp_to_uint RegF32:$a))]>;
992 : InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a",
993 [(set RegI32:$d, (fp_to_uint RegF64:$a))]>;
998 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
999 [(set RegI64:$d, (zext RegPred:$a))]>;
1002 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
1003 [(set RegI64:$d, (sext RegPred:$a))]>;
1006 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
1007 [(set RegI64:$d, (zext RegI16:$a))]>;
1010 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
1011 [(set RegI64:$d, (sext RegI16:$a))]>;
1014 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
1015 [(set RegI64:$d, (zext RegI32:$a))]>;
1018 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
1019 [(set RegI64:$d, (sext RegI32:$a))]>;
1022 : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a",
1023 [(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
1026 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a",
1027 [(set RegI64:$d, (fp_to_uint RegF64:$a))]>;
1029 // Conversion to f32
1032 : InstPTX<(outs RegF32:$d), (ins RegPred:$a),
1033 "selp.f32\t$d, 0F3F800000, 0F00000000, $a", // 1.0
1034 [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
1037 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
1038 [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
1041 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a",
1042 [(set RegF32:$d, (uint_to_fp RegI32:$a))]>;
1045 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a",
1046 [(set RegF32:$d, (uint_to_fp RegI64:$a))]>;
1049 : InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
1050 [(set RegF32:$d, (fround RegF64:$a))]>;
1052 // Conversion to f64
1055 : InstPTX<(outs RegF64:$d), (ins RegPred:$a),
1056 "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a", // 1.0
1057 [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
1060 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
1061 [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
1064 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a",
1065 [(set RegF64:$d, (uint_to_fp RegI32:$a))]>;
1068 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a",
1069 [(set RegF64:$d, (uint_to_fp RegI64:$a))]>;
1072 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
1073 [(set RegF64:$d, (fextend RegF32:$a))]>;
1075 ///===- Control Flow Instructions -----------------------------------------===//
1077 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1079 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
1082 let isBranch = 1, isTerminator = 1 in {
1083 // FIXME: The pattern part is blank because I cannot (or do not yet know
1084 // how to) use the first operand of PredicateOperand (a RegPred register) here
1086 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
1087 [/*(brcond pred:$_p, bb:$d)*/]>;
1090 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1091 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
1092 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
1095 let hasSideEffects = 1 in {
1096 def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>;
1100 ///===- Spill Instructions ------------------------------------------------===//
1101 // Special instructions used for stack spilling
1102 def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
1103 "mov.u16\ts$d, $a", []>;
1104 def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
1105 "mov.u32\ts$d, $a", []>;
1106 def STACKSTOREI64 : InstPTX<(outs), (ins i32imm:$d, RegI64:$a),
1107 "mov.u64\ts$d, $a", []>;
1108 def STACKSTOREF32 : InstPTX<(outs), (ins i32imm:$d, RegF32:$a),
1109 "mov.f32\ts$d, $a", []>;
1110 def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
1111 "mov.f64\ts$d, $a", []>;
1113 def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
1114 "mov.u16\t$d, s$a", []>;
1115 def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),
1116 "mov.u32\t$d, s$a", []>;
1117 def STACKLOADI64 : InstPTX<(outs), (ins RegI64:$d, i32imm:$a),
1118 "mov.u64\t$d, s$a", []>;
1119 def STACKLOADF32 : InstPTX<(outs), (ins RegF32:$d, i32imm:$a),
1120 "mov.f32\t$d, s$a", []>;
1121 def STACKLOADF64 : InstPTX<(outs), (ins RegF64:$d, i32imm:$a),
1122 "mov.f64\t$d, s$a", []>;
1124 ///===- Parameter Passing Pseudo-Instructions -----------------------------===//
1126 def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b),
1127 "mov.pred\t$a, %param$b", []>;
1128 def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b),
1129 "mov.b16\t$a, %param$b", []>;
1130 def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b),
1131 "mov.b32\t$a, %param$b", []>;
1132 def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b),
1133 "mov.b64\t$a, %param$b", []>;
1134 def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b),
1135 "mov.f32\t$a, %param$b", []>;
1136 def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b),
1137 "mov.f64\t$a, %param$b", []>;
1139 def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>;
1140 def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>;
1141 def WRITEPARAMI32 : InstPTX<(outs), (ins RegI32:$a), "//w", []>;
1142 def WRITEPARAMI64 : InstPTX<(outs), (ins RegI64:$a), "//w", []>;
1143 def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>;
1144 def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>;
1147 // def ADJCALLSTACKUP :
1148 // InstPTX<(outs), (ins i32imm:$amt1, i32imm:$amt2), "",
1149 // [(PTXcallseq_end timm:$amt1, timm:$amt2)]>;
1150 // def ADJCALLSTACKDOWN :
1151 // InstPTX<(outs), (ins i32imm:$amt), "",
1152 // [(PTXcallseq_start timm:$amt)]>;
1154 ///===- Intrinsic Instructions --------------------------------------------===//
1156 include "PTXIntrinsicInstrInfo.td"