1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
28 // Shader Model Support
29 def SupportsSM13 : Predicate<"getSubtarget().supportsSM13()">;
30 def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
31 def SupportsSM20 : Predicate<"getSubtarget().supportsSM20()">;
32 def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
40 //===----------------------------------------------------------------------===//
41 // Instruction Pattern Stuff
42 //===----------------------------------------------------------------------===//
44 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
46 const PointerType *PT;
47 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
48 (PT = dyn_cast<PointerType>(Src->getType())))
49 return PT->getAddressSpace() == PTX::GLOBAL;
53 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
55 const PointerType *PT;
56 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
57 (PT = dyn_cast<PointerType>(Src->getType())))
58 return PT->getAddressSpace() == PTX::CONSTANT;
62 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
64 const PointerType *PT;
65 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
66 (PT = dyn_cast<PointerType>(Src->getType())))
67 return PT->getAddressSpace() == PTX::LOCAL;
71 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
73 const PointerType *PT;
74 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
75 (PT = dyn_cast<PointerType>(Src->getType())))
76 return PT->getAddressSpace() == PTX::PARAMETER;
80 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
82 const PointerType *PT;
83 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
84 (PT = dyn_cast<PointerType>(Src->getType())))
85 return PT->getAddressSpace() == PTX::SHARED;
90 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
92 const PointerType *PT;
93 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
94 (PT = dyn_cast<PointerType>(Src->getType())))
95 return PT->getAddressSpace() == PTX::GLOBAL;
100 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
102 const PointerType *PT;
103 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
104 (PT = dyn_cast<PointerType>(Src->getType())))
105 return PT->getAddressSpace() == PTX::LOCAL;
110 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
112 const PointerType *PT;
113 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
114 (PT = dyn_cast<PointerType>(Src->getType())))
115 return PT->getAddressSpace() == PTX::PARAMETER;
120 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
122 const PointerType *PT;
123 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
124 (PT = dyn_cast<PointerType>(Src->getType())))
125 return PT->getAddressSpace() == PTX::SHARED;
130 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
131 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
132 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
133 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
134 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
135 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
138 def MEMri32 : Operand<i32> {
139 let PrintMethod = "printMemOperand";
140 let MIOperandInfo = (ops RRegu32, i32imm);
142 def MEMri64 : Operand<i64> {
143 let PrintMethod = "printMemOperand";
144 let MIOperandInfo = (ops RRegu64, i64imm);
146 def MEMii32 : Operand<i32> {
147 let PrintMethod = "printMemOperand";
148 let MIOperandInfo = (ops i32imm, i32imm);
150 def MEMii64 : Operand<i64> {
151 let PrintMethod = "printMemOperand";
152 let MIOperandInfo = (ops i64imm, i64imm);
154 // The operand here does not correspond to an actual address, so we
155 // can use i32 in 64-bit address modes.
156 def MEMpi : Operand<i32> {
157 let PrintMethod = "printParamOperand";
158 let MIOperandInfo = (ops i32imm);
161 // Branch & call targets have OtherVT type.
162 def brtarget : Operand<OtherVT>;
163 def calltarget : Operand<i32>;
165 //===----------------------------------------------------------------------===//
166 // PTX Specific Node Definitions
167 //===----------------------------------------------------------------------===//
169 // PTX allow generic 3-reg shifts like shl r0, r1, r2
170 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
171 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
172 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
175 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
177 : SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
179 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
181 //===----------------------------------------------------------------------===//
182 // Instruction Class Templates
183 //===----------------------------------------------------------------------===//
185 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
186 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
187 def rr32 : InstPTX<(outs RRegf32:$d),
189 !strconcat(opcstr, ".f32\t$d, $a"),
190 [(set RRegf32:$d, (opnode RRegf32:$a))]>;
191 def ri32 : InstPTX<(outs RRegf32:$d),
193 !strconcat(opcstr, ".f32\t$d, $a"),
194 [(set RRegf32:$d, (opnode fpimm:$a))]>;
195 def rr64 : InstPTX<(outs RRegf64:$d),
197 !strconcat(opcstr, ".f64\t$d, $a"),
198 [(set RRegf64:$d, (opnode RRegf64:$a))]>;
199 def ri64 : InstPTX<(outs RRegf64:$d),
201 !strconcat(opcstr, ".f64\t$d, $a"),
202 [(set RRegf64:$d, (opnode fpimm:$a))]>;
205 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
206 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
207 def rr32 : InstPTX<(outs RRegf32:$d),
208 (ins RRegf32:$a, RRegf32:$b),
209 !strconcat(opcstr, ".f32\t$d, $a, $b"),
210 [(set RRegf32:$d, (opnode RRegf32:$a, RRegf32:$b))]>;
211 def ri32 : InstPTX<(outs RRegf32:$d),
212 (ins RRegf32:$a, f32imm:$b),
213 !strconcat(opcstr, ".f32\t$d, $a, $b"),
214 [(set RRegf32:$d, (opnode RRegf32:$a, fpimm:$b))]>;
215 def rr64 : InstPTX<(outs RRegf64:$d),
216 (ins RRegf64:$a, RRegf64:$b),
217 !strconcat(opcstr, ".f64\t$d, $a, $b"),
218 [(set RRegf64:$d, (opnode RRegf64:$a, RRegf64:$b))]>;
219 def ri64 : InstPTX<(outs RRegf64:$d),
220 (ins RRegf64:$a, f64imm:$b),
221 !strconcat(opcstr, ".f64\t$d, $a, $b"),
222 [(set RRegf64:$d, (opnode RRegf64:$a, fpimm:$b))]>;
225 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
226 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
227 def rrr32 : InstPTX<(outs RRegf32:$d),
228 (ins RRegf32:$a, RRegf32:$b, RRegf32:$c),
229 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
230 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
233 def rri32 : InstPTX<(outs RRegf32:$d),
234 (ins RRegf32:$a, RRegf32:$b, f32imm:$c),
235 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
236 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
239 def rrr64 : InstPTX<(outs RRegf64:$d),
240 (ins RRegf64:$a, RRegf64:$b, RRegf64:$c),
241 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
242 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
245 def rri64 : InstPTX<(outs RRegf64:$d),
246 (ins RRegf64:$a, RRegf64:$b, f64imm:$c),
247 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
248 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
253 multiclass INT3<string opcstr, SDNode opnode> {
254 def rr16 : InstPTX<(outs RRegu16:$d),
255 (ins RRegu16:$a, RRegu16:$b),
256 !strconcat(opcstr, ".u16\t$d, $a, $b"),
257 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
258 def ri16 : InstPTX<(outs RRegu16:$d),
259 (ins RRegu16:$a, i16imm:$b),
260 !strconcat(opcstr, ".u16\t$d, $a, $b"),
261 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
262 def rr32 : InstPTX<(outs RRegu32:$d),
263 (ins RRegu32:$a, RRegu32:$b),
264 !strconcat(opcstr, ".u32\t$d, $a, $b"),
265 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
266 def ri32 : InstPTX<(outs RRegu32:$d),
267 (ins RRegu32:$a, i32imm:$b),
268 !strconcat(opcstr, ".u32\t$d, $a, $b"),
269 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
270 def rr64 : InstPTX<(outs RRegu64:$d),
271 (ins RRegu64:$a, RRegu64:$b),
272 !strconcat(opcstr, ".u64\t$d, $a, $b"),
273 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
274 def ri64 : InstPTX<(outs RRegu64:$d),
275 (ins RRegu64:$a, i64imm:$b),
276 !strconcat(opcstr, ".u64\t$d, $a, $b"),
277 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
280 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
281 def ripreds : InstPTX<(outs Preds:$d),
282 (ins Preds:$a, i1imm:$b),
283 !strconcat(opcstr, ".pred\t$d, $a, $b"),
284 [(set Preds:$d, (opnode Preds:$a, imm:$b))]>;
285 def rrpreds : InstPTX<(outs Preds:$d),
286 (ins Preds:$a, Preds:$b),
287 !strconcat(opcstr, ".pred\t$d, $a, $b"),
288 [(set Preds:$d, (opnode Preds:$a, Preds:$b))]>;
289 def rr16 : InstPTX<(outs RRegu16:$d),
290 (ins RRegu16:$a, RRegu16:$b),
291 !strconcat(opcstr, ".b16\t$d, $a, $b"),
292 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
293 def ri16 : InstPTX<(outs RRegu16:$d),
294 (ins RRegu16:$a, i16imm:$b),
295 !strconcat(opcstr, ".b16\t$d, $a, $b"),
296 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
297 def rr32 : InstPTX<(outs RRegu32:$d),
298 (ins RRegu32:$a, RRegu32:$b),
299 !strconcat(opcstr, ".b32\t$d, $a, $b"),
300 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
301 def ri32 : InstPTX<(outs RRegu32:$d),
302 (ins RRegu32:$a, i32imm:$b),
303 !strconcat(opcstr, ".b32\t$d, $a, $b"),
304 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
305 def rr64 : InstPTX<(outs RRegu64:$d),
306 (ins RRegu64:$a, RRegu64:$b),
307 !strconcat(opcstr, ".b64\t$d, $a, $b"),
308 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
309 def ri64 : InstPTX<(outs RRegu64:$d),
310 (ins RRegu64:$a, i64imm:$b),
311 !strconcat(opcstr, ".b64\t$d, $a, $b"),
312 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
315 multiclass INT3ntnc<string opcstr, SDNode opnode> {
316 def rr16 : InstPTX<(outs RRegu16:$d),
317 (ins RRegu16:$a, RRegu16:$b),
318 !strconcat(opcstr, "16\t$d, $a, $b"),
319 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
320 def rr32 : InstPTX<(outs RRegu32:$d),
321 (ins RRegu32:$a, RRegu32:$b),
322 !strconcat(opcstr, "32\t$d, $a, $b"),
323 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
324 def rr64 : InstPTX<(outs RRegu64:$d),
325 (ins RRegu64:$a, RRegu64:$b),
326 !strconcat(opcstr, "64\t$d, $a, $b"),
327 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
328 def ri16 : InstPTX<(outs RRegu16:$d),
329 (ins RRegu16:$a, i16imm:$b),
330 !strconcat(opcstr, "16\t$d, $a, $b"),
331 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
332 def ri32 : InstPTX<(outs RRegu32:$d),
333 (ins RRegu32:$a, i32imm:$b),
334 !strconcat(opcstr, "32\t$d, $a, $b"),
335 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
336 def ri64 : InstPTX<(outs RRegu64:$d),
337 (ins RRegu64:$a, i64imm:$b),
338 !strconcat(opcstr, "64\t$d, $a, $b"),
339 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
340 def ir16 : InstPTX<(outs RRegu16:$d),
341 (ins i16imm:$a, RRegu16:$b),
342 !strconcat(opcstr, "16\t$d, $a, $b"),
343 [(set RRegu16:$d, (opnode imm:$a, RRegu16:$b))]>;
344 def ir32 : InstPTX<(outs RRegu32:$d),
345 (ins i32imm:$a, RRegu32:$b),
346 !strconcat(opcstr, "32\t$d, $a, $b"),
347 [(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
348 def ir64 : InstPTX<(outs RRegu64:$d),
349 (ins i64imm:$a, RRegu64:$b),
350 !strconcat(opcstr, "64\t$d, $a, $b"),
351 [(set RRegu64:$d, (opnode imm:$a, RRegu64:$b))]>;
354 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
355 CondCode cmp, string cmpstr> {
356 // TODO support 5-operand format: p|q, a, b, c
359 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
360 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
361 [(set Preds:$p, (setcc RC:$a, RC:$b, cmp))]>;
363 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b),
364 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
365 [(set Preds:$p, (setcc RC:$a, imm:$b, cmp))]>;
368 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
369 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
370 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
372 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
373 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
374 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
376 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
377 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
378 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
380 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
381 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
382 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
384 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
385 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
386 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
388 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
389 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
390 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
393 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
394 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
395 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
397 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
398 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
399 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
401 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
402 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
403 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
405 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
406 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
407 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
409 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
410 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
411 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
413 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
414 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
415 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
418 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
419 CondCode ucmp, CondCode ocmp, string cmpstr> {
420 // TODO support 5-operand format: p|q, a, b, c
423 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
424 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
425 [(set Preds:$p, (setcc RC:$a, RC:$b, ucmp))]>;
427 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
428 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
429 [(set Preds:$p, (setcc RC:$a, RC:$b, ocmp))]>;
432 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
433 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
434 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
436 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
437 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
438 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
441 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
442 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
443 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
445 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
446 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
447 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
450 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
451 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
452 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
454 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
455 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
456 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
459 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
460 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
461 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
463 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
464 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
465 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
468 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
469 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
470 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
472 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
473 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
474 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
477 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
478 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
479 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
481 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
482 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
483 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
486 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
488 : InstPTX<(outs RC:$r), (ins Preds:$a, RC:$b, RC:$c),
489 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
490 [(set RC:$r, (select Preds:$a, RC:$b, RC:$c))]>;
493 multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
494 def rr32 : InstPTX<(outs RC:$d),
496 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
497 [(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
498 def rr64 : InstPTX<(outs RC:$d),
500 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
501 [(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
502 def ri32 : InstPTX<(outs RC:$d),
504 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
505 [(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
506 def ri64 : InstPTX<(outs RC:$d),
508 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
509 [(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
510 def ii32 : InstPTX<(outs RC:$d),
512 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
513 [(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
514 def ii64 : InstPTX<(outs RC:$d),
516 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
517 [(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
520 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
521 defm u16 : PTX_LD<opstr, ".u16", RRegu16, pat_load>;
522 defm u32 : PTX_LD<opstr, ".u32", RRegu32, pat_load>;
523 defm u64 : PTX_LD<opstr, ".u64", RRegu64, pat_load>;
524 defm f32 : PTX_LD<opstr, ".f32", RRegf32, pat_load>;
525 defm f64 : PTX_LD<opstr, ".f64", RRegf64, pat_load>;
528 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
529 def rr32 : InstPTX<(outs),
530 (ins RC:$d, MEMri32:$a),
531 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
532 [(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
533 def rr64 : InstPTX<(outs),
534 (ins RC:$d, MEMri64:$a),
535 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
536 [(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
537 def ri32 : InstPTX<(outs),
538 (ins RC:$d, MEMri32:$a),
539 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
540 [(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
541 def ri64 : InstPTX<(outs),
542 (ins RC:$d, MEMri64:$a),
543 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
544 [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
545 def ii32 : InstPTX<(outs),
546 (ins RC:$d, MEMii32:$a),
547 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
548 [(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
549 def ii64 : InstPTX<(outs),
550 (ins RC:$d, MEMii64:$a),
551 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
552 [(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
555 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
556 defm u16 : PTX_ST<opstr, ".u16", RRegu16, pat_store>;
557 defm u32 : PTX_ST<opstr, ".u32", RRegu32, pat_store>;
558 defm u64 : PTX_ST<opstr, ".u64", RRegu64, pat_store>;
559 defm f32 : PTX_ST<opstr, ".f32", RRegf32, pat_store>;
560 defm f64 : PTX_ST<opstr, ".f64", RRegf64, pat_store>;
563 //===----------------------------------------------------------------------===//
565 //===----------------------------------------------------------------------===//
567 ///===- Integer Arithmetic Instructions -----------------------------------===//
569 defm ADD : INT3<"add", add>;
570 defm SUB : INT3<"sub", sub>;
571 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
572 defm DIV : INT3<"div", udiv>;
573 defm REM : INT3<"rem", urem>;
575 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
577 // Standard Unary Operations
578 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
580 // Standard Binary Operations
581 defm FADD : PTX_FLOAT_3OP<"add", fadd>;
582 defm FSUB : PTX_FLOAT_3OP<"sub", fsub>;
583 defm FMUL : PTX_FLOAT_3OP<"mul", fmul>;
585 // TODO: Allow user selection of rounding modes for fdiv.
586 // For division, we need to have f32 and f64 differently.
587 // For f32, we just always use .approx since it is supported on all hardware
588 // for PTX 1.4+, which is our minimum target.
589 def FDIVrr32 : InstPTX<(outs RRegf32:$d),
590 (ins RRegf32:$a, RRegf32:$b),
591 "div.approx.f32\t$d, $a, $b",
592 [(set RRegf32:$d, (fdiv RRegf32:$a, RRegf32:$b))]>;
593 def FDIVri32 : InstPTX<(outs RRegf32:$d),
594 (ins RRegf32:$a, f32imm:$b),
595 "div.approx.f32\t$d, $a, $b",
596 [(set RRegf32:$d, (fdiv RRegf32:$a, fpimm:$b))]>;
598 // For f64, we must specify a rounding for sm 1.3+ but *not* for sm 1.0.
599 def FDIVrr64SM13 : InstPTX<(outs RRegf64:$d),
600 (ins RRegf64:$a, RRegf64:$b),
601 "div.rn.f64\t$d, $a, $b",
602 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
603 Requires<[SupportsSM13]>;
604 def FDIVri64SM13 : InstPTX<(outs RRegf64:$d),
605 (ins RRegf64:$a, f64imm:$b),
606 "div.rn.f64\t$d, $a, $b",
607 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
608 Requires<[SupportsSM13]>;
609 def FDIVrr64SM10 : InstPTX<(outs RRegf64:$d),
610 (ins RRegf64:$a, RRegf64:$b),
611 "div.f64\t$d, $a, $b",
612 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
613 Requires<[DoesNotSupportSM13]>;
614 def FDIVri64SM10 : InstPTX<(outs RRegf64:$d),
615 (ins RRegf64:$a, f64imm:$b),
616 "div.f64\t$d, $a, $b",
617 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
618 Requires<[DoesNotSupportSM13]>;
622 // Multi-operation hybrid instructions
624 // The selection of mad/fma is tricky. In some cases, they are the *same*
625 // instruction, but in other cases we may prefer one or the other. Also,
626 // different PTX versions differ on whether rounding mode flags are required.
627 // In the short term, mad is supported on all PTX versions and we use a
628 // default rounding mode no matter what shader model or PTX version.
629 // TODO: Allow the rounding mode to be selectable through llc.
630 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13]>;
631 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13]>;
633 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
635 def FSQRT32 : InstPTX<(outs RRegf32:$d),
637 "sqrt.rn.f32\t$d, $a",
638 [(set RRegf32:$d, (fsqrt RRegf32:$a))]>;
640 def FSQRT64 : InstPTX<(outs RRegf64:$d),
642 "sqrt.rn.f64\t$d, $a",
643 [(set RRegf64:$d, (fsqrt RRegf64:$a))]>;
645 def FSIN32 : InstPTX<(outs RRegf32:$d),
647 "sin.approx.f32\t$d, $a",
648 [(set RRegf32:$d, (fsin RRegf32:$a))]>;
650 def FSIN64 : InstPTX<(outs RRegf64:$d),
652 "sin.approx.f64\t$d, $a",
653 [(set RRegf64:$d, (fsin RRegf64:$a))]>;
655 def FCOS32 : InstPTX<(outs RRegf32:$d),
657 "cos.approx.f32\t$d, $a",
658 [(set RRegf32:$d, (fcos RRegf32:$a))]>;
660 def FCOS64 : InstPTX<(outs RRegf64:$d),
662 "cos.approx.f64\t$d, $a",
663 [(set RRegf64:$d, (fcos RRegf64:$a))]>;
666 ///===- Comparison and Selection Instructions -----------------------------===//
670 defm SETPEQu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETEQ, "eq">;
671 defm SETPNEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETNE, "ne">;
672 defm SETPLTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULT, "lt">;
673 defm SETPLEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULE, "le">;
674 defm SETPGTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGT, "gt">;
675 defm SETPGEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGE, "ge">;
679 defm SETPEQu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETEQ, "eq">;
680 defm SETPNEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETNE, "ne">;
681 defm SETPLTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULT, "lt">;
682 defm SETPLEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULE, "le">;
683 defm SETPGTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGT, "gt">;
684 defm SETPGEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGE, "ge">;
688 defm SETPEQu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETEQ, "eq">;
689 defm SETPNEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETNE, "ne">;
690 defm SETPLTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULT, "lt">;
691 defm SETPLEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULE, "le">;
692 defm SETPGTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGT, "gt">;
693 defm SETPGEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGE, "ge">;
697 defm SETPEQf32 : PTX_SETP_FP<RRegf32, "f32", SETUEQ, SETOEQ, "eq">;
698 defm SETPNEf32 : PTX_SETP_FP<RRegf32, "f32", SETUNE, SETONE, "ne">;
699 defm SETPLTf32 : PTX_SETP_FP<RRegf32, "f32", SETULT, SETOLT, "lt">;
700 defm SETPLEf32 : PTX_SETP_FP<RRegf32, "f32", SETULE, SETOLE, "le">;
701 defm SETPGTf32 : PTX_SETP_FP<RRegf32, "f32", SETUGT, SETOGT, "gt">;
702 defm SETPGEf32 : PTX_SETP_FP<RRegf32, "f32", SETUGE, SETOGE, "ge">;
706 defm SETPEQf64 : PTX_SETP_FP<RRegf64, "f64", SETUEQ, SETOEQ, "eq">;
707 defm SETPNEf64 : PTX_SETP_FP<RRegf64, "f64", SETUNE, SETONE, "ne">;
708 defm SETPLTf64 : PTX_SETP_FP<RRegf64, "f64", SETULT, SETOLT, "lt">;
709 defm SETPLEf64 : PTX_SETP_FP<RRegf64, "f64", SETULE, SETOLE, "le">;
710 defm SETPGTf64 : PTX_SETP_FP<RRegf64, "f64", SETUGT, SETOGT, "gt">;
711 defm SETPGEf64 : PTX_SETP_FP<RRegf64, "f64", SETUGE, SETOGE, "ge">;
715 defm PTX_SELPu16 : PTX_SELP<RRegu16, "u16">;
716 defm PTX_SELPu32 : PTX_SELP<RRegu32, "u32">;
717 defm PTX_SELPu64 : PTX_SELP<RRegu64, "u64">;
718 defm PTX_SELPf32 : PTX_SELP<RRegf32, "f32">;
719 defm PTX_SELPf64 : PTX_SELP<RRegf64, "f64">;
721 ///===- Logic and Shift Instructions --------------------------------------===//
723 defm SHL : INT3ntnc<"shl.b", PTXshl>;
724 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
725 defm SRA : INT3ntnc<"shr.s", PTXsra>;
727 defm AND : PTX_LOGIC<"and", and>;
728 defm OR : PTX_LOGIC<"or", or>;
729 defm XOR : PTX_LOGIC<"xor", xor>;
731 ///===- Data Movement and Conversion Instructions -------------------------===//
733 let neverHasSideEffects = 1 in {
735 : InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
737 : InstPTX<(outs RRegu16:$d), (ins RRegu16:$a), "mov.u16\t$d, $a", []>;
739 : InstPTX<(outs RRegu32:$d), (ins RRegu32:$a), "mov.u32\t$d, $a", []>;
741 : InstPTX<(outs RRegu64:$d), (ins RRegu64:$a), "mov.u64\t$d, $a", []>;
743 : InstPTX<(outs RRegf32:$d), (ins RRegf32:$a), "mov.f32\t$d, $a", []>;
745 : InstPTX<(outs RRegf64:$d), (ins RRegf64:$a), "mov.f64\t$d, $a", []>;
748 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
750 : InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
751 [(set Preds:$d, imm:$a)]>;
753 : InstPTX<(outs RRegu16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
754 [(set RRegu16:$d, imm:$a)]>;
756 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
757 [(set RRegu32:$d, imm:$a)]>;
759 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
760 [(set RRegu64:$d, imm:$a)]>;
762 : InstPTX<(outs RRegf32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
763 [(set RRegf32:$d, fpimm:$a)]>;
765 : InstPTX<(outs RRegf64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
766 [(set RRegf64:$d, fpimm:$a)]>;
769 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
771 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
772 [(set RRegu32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
774 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
775 [(set RRegu64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
779 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
780 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
781 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
782 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
784 // This is a special instruction that is manually inserted for kernel parameters
785 def LDpiU16 : InstPTX<(outs RRegu16:$d), (ins MEMpi:$a),
786 "ld.param.u16\t$d, [$a]", []>;
787 def LDpiU32 : InstPTX<(outs RRegu32:$d), (ins MEMpi:$a),
788 "ld.param.u32\t$d, [$a]", []>;
789 def LDpiU64 : InstPTX<(outs RRegu64:$d), (ins MEMpi:$a),
790 "ld.param.u64\t$d, [$a]", []>;
791 def LDpiF32 : InstPTX<(outs RRegf32:$d), (ins MEMpi:$a),
792 "ld.param.f32\t$d, [$a]", []>;
793 def LDpiF64 : InstPTX<(outs RRegf64:$d), (ins MEMpi:$a),
794 "ld.param.f64\t$d, [$a]", []>;
797 defm STg : PTX_ST_ALL<"st.global", store_global>;
798 defm STl : PTX_ST_ALL<"st.local", store_local>;
799 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
801 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
802 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
803 // TODO: Do something with st.param if/when it is needed.
805 // Conversion to pred
808 : InstPTX<(outs Preds:$d), (ins RRegu16:$a), "cvt.pred.u16\t$d, $a",
809 [(set Preds:$d, (trunc RRegu16:$a))]>;
812 : InstPTX<(outs Preds:$d), (ins RRegu32:$a), "cvt.pred.u32\t$d, $a",
813 [(set Preds:$d, (trunc RRegu32:$a))]>;
816 : InstPTX<(outs Preds:$d), (ins RRegu64:$a), "cvt.pred.u64\t$d, $a",
817 [(set Preds:$d, (trunc RRegu64:$a))]>;
820 : InstPTX<(outs Preds:$d), (ins RRegf32:$a), "cvt.rni.pred.f32\t$d, $a",
821 [(set Preds:$d, (fp_to_uint RRegf32:$a))]>;
824 : InstPTX<(outs Preds:$d), (ins RRegf64:$a), "cvt.rni.pred.f64\t$d, $a",
825 [(set Preds:$d, (fp_to_uint RRegf64:$a))]>;
830 : InstPTX<(outs RRegu16:$d), (ins Preds:$a), "cvt.u16.pred\t$d, $a",
831 [(set RRegu16:$d, (zext Preds:$a))]>;
834 : InstPTX<(outs RRegu16:$d), (ins RRegu32:$a), "cvt.u16.u32\t$d, $a",
835 [(set RRegu16:$d, (trunc RRegu32:$a))]>;
838 : InstPTX<(outs RRegu16:$d), (ins RRegu64:$a), "cvt.u16.u64\t$d, $a",
839 [(set RRegu16:$d, (trunc RRegu64:$a))]>;
842 : InstPTX<(outs RRegu16:$d), (ins RRegf32:$a), "cvt.rni.u16.f32\t$d, $a",
843 [(set RRegu16:$d, (fp_to_uint RRegf32:$a))]>;
846 : InstPTX<(outs RRegu16:$d), (ins RRegf64:$a), "cvt.rni.u16.f64\t$d, $a",
847 [(set RRegu16:$d, (fp_to_uint RRegf64:$a))]>;
852 : InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
853 [(set RRegu32:$d, (zext Preds:$a))]>;
856 : InstPTX<(outs RRegu32:$d), (ins RRegu16:$a), "cvt.u32.u16\t$d, $a",
857 [(set RRegu32:$d, (zext RRegu16:$a))]>;
860 : InstPTX<(outs RRegu32:$d), (ins RRegu64:$a), "cvt.u32.u64\t$d, $a",
861 [(set RRegu32:$d, (trunc RRegu64:$a))]>;
864 : InstPTX<(outs RRegu32:$d), (ins RRegf32:$a), "cvt.rni.u32.f32\t$d, $a",
865 [(set RRegu32:$d, (fp_to_uint RRegf32:$a))]>;
868 : InstPTX<(outs RRegu32:$d), (ins RRegf64:$a), "cvt.rni.u32.f64\t$d, $a",
869 [(set RRegu32:$d, (fp_to_uint RRegf64:$a))]>;
874 : InstPTX<(outs RRegu64:$d), (ins Preds:$a), "cvt.u64.pred\t$d, $a",
875 [(set RRegu64:$d, (zext Preds:$a))]>;
878 : InstPTX<(outs RRegu64:$d), (ins RRegu16:$a), "cvt.u64.u16\t$d, $a",
879 [(set RRegu64:$d, (zext RRegu16:$a))]>;
882 : InstPTX<(outs RRegu64:$d), (ins RRegu32:$a), "cvt.u64.u32\t$d, $a",
883 [(set RRegu64:$d, (zext RRegu32:$a))]>;
886 : InstPTX<(outs RRegu64:$d), (ins RRegf32:$a), "cvt.rni.u64.f32\t$d, $a",
887 [(set RRegu64:$d, (fp_to_uint RRegf32:$a))]>;
890 : InstPTX<(outs RRegu64:$d), (ins RRegf64:$a), "cvt.rni.u64.f64\t$d, $a",
891 [(set RRegu64:$d, (fp_to_uint RRegf64:$a))]>;
896 : InstPTX<(outs RRegf32:$d), (ins Preds:$a), "cvt.rn.f32.pred\t$d, $a",
897 [(set RRegf32:$d, (uint_to_fp Preds:$a))]>;
900 : InstPTX<(outs RRegf32:$d), (ins RRegu16:$a), "cvt.rn.f32.u16\t$d, $a",
901 [(set RRegf32:$d, (uint_to_fp RRegu16:$a))]>;
904 : InstPTX<(outs RRegf32:$d), (ins RRegu32:$a), "cvt.rn.f32.u32\t$d, $a",
905 [(set RRegf32:$d, (uint_to_fp RRegu32:$a))]>;
908 : InstPTX<(outs RRegf32:$d), (ins RRegu64:$a), "cvt.rn.f32.u64\t$d, $a",
909 [(set RRegf32:$d, (uint_to_fp RRegu64:$a))]>;
912 : InstPTX<(outs RRegf32:$d), (ins RRegf64:$a), "cvt.rn.f32.f64\t$d, $a",
913 [(set RRegf32:$d, (fround RRegf64:$a))]>;
918 : InstPTX<(outs RRegf64:$d), (ins Preds:$a), "cvt.rn.f64.pred\t$d, $a",
919 [(set RRegf64:$d, (uint_to_fp Preds:$a))]>;
922 : InstPTX<(outs RRegf64:$d), (ins RRegu16:$a), "cvt.rn.f64.u16\t$d, $a",
923 [(set RRegf64:$d, (uint_to_fp RRegu16:$a))]>;
926 : InstPTX<(outs RRegf64:$d), (ins RRegu32:$a), "cvt.rn.f64.u32\t$d, $a",
927 [(set RRegf64:$d, (uint_to_fp RRegu32:$a))]>;
930 : InstPTX<(outs RRegf64:$d), (ins RRegu64:$a), "cvt.rn.f64.u64\t$d, $a",
931 [(set RRegf64:$d, (uint_to_fp RRegu64:$a))]>;
934 : InstPTX<(outs RRegf64:$d), (ins RRegf32:$a), "cvt.f64.f32\t$d, $a",
935 [(set RRegf64:$d, (fextend RRegf32:$a))]>;
937 ///===- Control Flow Instructions -----------------------------------------===//
939 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
941 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
944 let isBranch = 1, isTerminator = 1 in {
945 // FIXME: The pattern part is blank because I cannot (or do not yet know
946 // how to) use the first operand of PredicateOperand (a Preds register) here
948 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
949 [/*(brcond pred:$_p, bb:$d)*/]>;
952 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
953 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
954 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
957 ///===- Intrinsic Instructions --------------------------------------------===//
959 include "PTXIntrinsicInstrInfo.td"