1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
24 // Shader Model Support
25 def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">;
26 def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">;
27 def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">;
28 def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">;
30 // PTX Version Support
31 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
32 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
33 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
34 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
35 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
36 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
39 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
40 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
44 // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
45 // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
47 // def PTXcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PTXCallSeqStart,
48 // [SDNPHasChain, SDNPOutGlue]>;
49 // def PTXcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PTXCallSeqEnd,
50 // [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
52 def PTXcall : SDNode<"PTXISD::CALL", SDTNone,
53 [SDNPHasChain, SDNPVariadic, SDNPOptInGlue, SDNPOutGlue]>;
56 // Branch & call targets have OtherVT type.
57 def brtarget : Operand<OtherVT>;
58 def calltarget : Operand<i32>;
60 //===----------------------------------------------------------------------===//
61 // PTX Specific Node Definitions
62 //===----------------------------------------------------------------------===//
64 // PTX allow generic 3-reg shifts like shl r0, r1, r2
65 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
66 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
67 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
70 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
72 : SDNode<"PTXISD::RET", SDTNone,
73 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
75 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
79 //===----------------------------------------------------------------------===//
80 // Instruction Class Templates
81 //===----------------------------------------------------------------------===//
83 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
84 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
85 def rr32 : InstPTX<(outs RegF32:$d),
87 !strconcat(opcstr, ".f32\t$d, $a"),
88 [(set RegF32:$d, (opnode RegF32:$a))]>;
89 def ri32 : InstPTX<(outs RegF32:$d),
91 !strconcat(opcstr, ".f32\t$d, $a"),
92 [(set RegF32:$d, (opnode fpimm:$a))]>;
93 def rr64 : InstPTX<(outs RegF64:$d),
95 !strconcat(opcstr, ".f64\t$d, $a"),
96 [(set RegF64:$d, (opnode RegF64:$a))]>;
97 def ri64 : InstPTX<(outs RegF64:$d),
99 !strconcat(opcstr, ".f64\t$d, $a"),
100 [(set RegF64:$d, (opnode fpimm:$a))]>;
103 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
104 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
105 def rr32 : InstPTX<(outs RegF32:$d),
106 (ins RegF32:$a, RegF32:$b),
107 !strconcat(opcstr, ".f32\t$d, $a, $b"),
108 [(set RegF32:$d, (opnode RegF32:$a, RegF32:$b))]>;
109 def ri32 : InstPTX<(outs RegF32:$d),
110 (ins RegF32:$a, f32imm:$b),
111 !strconcat(opcstr, ".f32\t$d, $a, $b"),
112 [(set RegF32:$d, (opnode RegF32:$a, fpimm:$b))]>;
113 def rr64 : InstPTX<(outs RegF64:$d),
114 (ins RegF64:$a, RegF64:$b),
115 !strconcat(opcstr, ".f64\t$d, $a, $b"),
116 [(set RegF64:$d, (opnode RegF64:$a, RegF64:$b))]>;
117 def ri64 : InstPTX<(outs RegF64:$d),
118 (ins RegF64:$a, f64imm:$b),
119 !strconcat(opcstr, ".f64\t$d, $a, $b"),
120 [(set RegF64:$d, (opnode RegF64:$a, fpimm:$b))]>;
123 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
124 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
125 def rrr32 : InstPTX<(outs RegF32:$d),
126 (ins RegF32:$a, RegF32:$b, RegF32:$c),
127 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
128 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
131 def rri32 : InstPTX<(outs RegF32:$d),
132 (ins RegF32:$a, RegF32:$b, f32imm:$c),
133 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
134 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
137 def rrr64 : InstPTX<(outs RegF64:$d),
138 (ins RegF64:$a, RegF64:$b, RegF64:$c),
139 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
140 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
143 def rri64 : InstPTX<(outs RegF64:$d),
144 (ins RegF64:$a, RegF64:$b, f64imm:$c),
145 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
146 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
151 multiclass INT3<string opcstr, SDNode opnode> {
152 def rr16 : InstPTX<(outs RegI16:$d),
153 (ins RegI16:$a, RegI16:$b),
154 !strconcat(opcstr, ".u16\t$d, $a, $b"),
155 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
156 def ri16 : InstPTX<(outs RegI16:$d),
157 (ins RegI16:$a, i16imm:$b),
158 !strconcat(opcstr, ".u16\t$d, $a, $b"),
159 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
160 def rr32 : InstPTX<(outs RegI32:$d),
161 (ins RegI32:$a, RegI32:$b),
162 !strconcat(opcstr, ".u32\t$d, $a, $b"),
163 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
164 def ri32 : InstPTX<(outs RegI32:$d),
165 (ins RegI32:$a, i32imm:$b),
166 !strconcat(opcstr, ".u32\t$d, $a, $b"),
167 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
168 def rr64 : InstPTX<(outs RegI64:$d),
169 (ins RegI64:$a, RegI64:$b),
170 !strconcat(opcstr, ".u64\t$d, $a, $b"),
171 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
172 def ri64 : InstPTX<(outs RegI64:$d),
173 (ins RegI64:$a, i64imm:$b),
174 !strconcat(opcstr, ".u64\t$d, $a, $b"),
175 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
178 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
179 def ripreds : InstPTX<(outs RegPred:$d),
180 (ins RegPred:$a, i1imm:$b),
181 !strconcat(opcstr, ".pred\t$d, $a, $b"),
182 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
183 def rrpreds : InstPTX<(outs RegPred:$d),
184 (ins RegPred:$a, RegPred:$b),
185 !strconcat(opcstr, ".pred\t$d, $a, $b"),
186 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
187 def rr16 : InstPTX<(outs RegI16:$d),
188 (ins RegI16:$a, RegI16:$b),
189 !strconcat(opcstr, ".b16\t$d, $a, $b"),
190 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
191 def ri16 : InstPTX<(outs RegI16:$d),
192 (ins RegI16:$a, i16imm:$b),
193 !strconcat(opcstr, ".b16\t$d, $a, $b"),
194 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
195 def rr32 : InstPTX<(outs RegI32:$d),
196 (ins RegI32:$a, RegI32:$b),
197 !strconcat(opcstr, ".b32\t$d, $a, $b"),
198 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
199 def ri32 : InstPTX<(outs RegI32:$d),
200 (ins RegI32:$a, i32imm:$b),
201 !strconcat(opcstr, ".b32\t$d, $a, $b"),
202 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
203 def rr64 : InstPTX<(outs RegI64:$d),
204 (ins RegI64:$a, RegI64:$b),
205 !strconcat(opcstr, ".b64\t$d, $a, $b"),
206 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
207 def ri64 : InstPTX<(outs RegI64:$d),
208 (ins RegI64:$a, i64imm:$b),
209 !strconcat(opcstr, ".b64\t$d, $a, $b"),
210 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
213 multiclass INT3ntnc<string opcstr, SDNode opnode> {
214 def rr16 : InstPTX<(outs RegI16:$d),
215 (ins RegI16:$a, RegI16:$b),
216 !strconcat(opcstr, "16\t$d, $a, $b"),
217 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
218 def rr32 : InstPTX<(outs RegI32:$d),
219 (ins RegI32:$a, RegI32:$b),
220 !strconcat(opcstr, "32\t$d, $a, $b"),
221 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
222 def rr64 : InstPTX<(outs RegI64:$d),
223 (ins RegI64:$a, RegI64:$b),
224 !strconcat(opcstr, "64\t$d, $a, $b"),
225 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
226 def ri16 : InstPTX<(outs RegI16:$d),
227 (ins RegI16:$a, i16imm:$b),
228 !strconcat(opcstr, "16\t$d, $a, $b"),
229 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
230 def ri32 : InstPTX<(outs RegI32:$d),
231 (ins RegI32:$a, i32imm:$b),
232 !strconcat(opcstr, "32\t$d, $a, $b"),
233 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
234 def ri64 : InstPTX<(outs RegI64:$d),
235 (ins RegI64:$a, i64imm:$b),
236 !strconcat(opcstr, "64\t$d, $a, $b"),
237 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
238 def ir16 : InstPTX<(outs RegI16:$d),
239 (ins i16imm:$a, RegI16:$b),
240 !strconcat(opcstr, "16\t$d, $a, $b"),
241 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
242 def ir32 : InstPTX<(outs RegI32:$d),
243 (ins i32imm:$a, RegI32:$b),
244 !strconcat(opcstr, "32\t$d, $a, $b"),
245 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
246 def ir64 : InstPTX<(outs RegI64:$d),
247 (ins i64imm:$a, RegI64:$b),
248 !strconcat(opcstr, "64\t$d, $a, $b"),
249 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
252 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
253 CondCode cmp, string cmpstr> {
254 // TODO support 5-operand format: p|q, a, b, c
257 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
258 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
259 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
261 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
262 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
263 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
266 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
267 !strconcat("setp.", cmpstr, ".and.", regclsname,
269 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
271 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
272 !strconcat("setp.", cmpstr, ".and.", regclsname,
274 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
277 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
278 !strconcat("setp.", cmpstr, ".or.", regclsname,
280 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
282 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
283 !strconcat("setp.", cmpstr, ".or.", regclsname,
285 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
287 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
288 !strconcat("setp.", cmpstr, ".xor.", regclsname,
290 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
292 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
293 !strconcat("setp.", cmpstr, ".xor.", regclsname,
295 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
299 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
300 !strconcat("setp.", cmpstr, ".and.", regclsname,
301 "\t$p, $a, $b, !$c"),
302 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp),
303 (not RegPred:$c)))]>;
305 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
306 !strconcat("setp.", cmpstr, ".and.", regclsname,
307 "\t$p, $a, $b, !$c"),
308 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
309 (not RegPred:$c)))]>;
311 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
312 !strconcat("setp.", cmpstr, ".or.", regclsname,
313 "\t$p, $a, $b, !$c"),
314 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp),
315 (not RegPred:$c)))]>;
317 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
318 !strconcat("setp.", cmpstr, ".or.", regclsname,
319 "\t$p, $a, $b, !$c"),
320 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp),
321 (not RegPred:$c)))]>;
323 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
324 !strconcat("setp.", cmpstr, ".xor.", regclsname,
325 "\t$p, $a, $b, !$c"),
326 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp),
327 (not RegPred:$c)))]>;
329 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
330 !strconcat("setp.", cmpstr, ".xor.", regclsname,
331 "\t$p, $a, $b, !$c"),
332 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
333 (not RegPred:$c)))]>;
336 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname, Operand immcls,
337 CondCode ucmp, CondCode ocmp, string cmpstr> {
338 // TODO support 5-operand format: p|q, a, b, c
341 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
342 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
343 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
345 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
346 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
347 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
350 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
351 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
352 [(set RegPred:$p, (setcc RC:$a, fpimm:$b, ucmp))]>;
354 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
355 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
356 [(set RegPred:$p, (setcc RC:$a, fpimm:$b, ocmp))]>;
359 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
360 !strconcat("setp.", cmpstr, "u.and.", regclsname,
362 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
365 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
366 !strconcat("setp.", cmpstr, ".and.", regclsname,
368 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
372 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
373 !strconcat("setp.", cmpstr, "u.or.", regclsname,
375 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
377 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
378 !strconcat("setp.", cmpstr, ".or.", regclsname,
380 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
383 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
384 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
386 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
389 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
390 !strconcat("setp.", cmpstr, ".xor.", regclsname,
392 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
396 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
397 !strconcat("setp.", cmpstr, "u.and.", regclsname,
398 "\t$p, $a, $b, !$c"),
399 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
400 (not RegPred:$c)))]>;
402 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
403 !strconcat("setp.", cmpstr, ".and.", regclsname,
404 "\t$p, $a, $b, !$c"),
405 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
406 (not RegPred:$c)))]>;
409 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
410 !strconcat("setp.", cmpstr, "u.or.", regclsname,
411 "\t$p, $a, $b, !$c"),
412 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp),
413 (not RegPred:$c)))]>;
415 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
416 !strconcat("setp.", cmpstr, ".or.", regclsname,
417 "\t$p, $a, $b, !$c"),
418 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp),
419 (not RegPred:$c)))]>;
422 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
423 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
424 "\t$p, $a, $b, !$c"),
425 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
426 (not RegPred:$c)))]>;
428 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
429 !strconcat("setp.", cmpstr, ".xor.", regclsname,
430 "\t$p, $a, $b, !$c"),
431 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
432 (not RegPred:$c)))]>;
435 multiclass PTX_SELP<RegisterClass RC, string regclsname, Operand immcls,
438 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
439 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
440 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
442 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, immcls:$c),
443 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
444 [(set RC:$r, (select RegPred:$a, RC:$b, immnode:$c))]>;
446 : InstPTX<(outs RC:$r), (ins RegPred:$a, immcls:$b, immcls:$c),
447 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
448 [(set RC:$r, (select RegPred:$a, immnode:$b, immnode:$c))]>;
453 //===----------------------------------------------------------------------===//
455 //===----------------------------------------------------------------------===//
457 ///===- Integer Arithmetic Instructions -----------------------------------===//
459 defm ADD : INT3<"add", add>;
460 defm SUB : INT3<"sub", sub>;
461 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
462 defm DIV : INT3<"div", udiv>;
463 defm REM : INT3<"rem", urem>;
465 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
467 // Standard Unary Operations
468 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
470 // Standard Binary Operations
471 defm FADD : PTX_FLOAT_3OP<"add.rn", fadd>;
472 defm FSUB : PTX_FLOAT_3OP<"sub.rn", fsub>;
473 defm FMUL : PTX_FLOAT_3OP<"mul.rn", fmul>;
475 // For floating-point division:
476 // SM_13+ defaults to .rn for f32 and f64,
477 // SM10 must *not* provide a rounding
480 // - Allow user selection of rounding modes for fdiv
481 // - Add support for -prec-div=false (.approx)
483 def FDIVrr32SM13 : InstPTX<(outs RegF32:$d),
484 (ins RegF32:$a, RegF32:$b),
485 "div.rn.f32\t$d, $a, $b",
486 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
487 Requires<[FDivNeedsRoundingMode]>;
488 def FDIVri32SM13 : InstPTX<(outs RegF32:$d),
489 (ins RegF32:$a, f32imm:$b),
490 "div.rn.f32\t$d, $a, $b",
491 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
492 Requires<[FDivNeedsRoundingMode]>;
493 def FDIVrr32SM10 : InstPTX<(outs RegF32:$d),
494 (ins RegF32:$a, RegF32:$b),
495 "div.f32\t$d, $a, $b",
496 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
497 Requires<[FDivNoRoundingMode]>;
498 def FDIVri32SM10 : InstPTX<(outs RegF32:$d),
499 (ins RegF32:$a, f32imm:$b),
500 "div.f32\t$d, $a, $b",
501 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
502 Requires<[FDivNoRoundingMode]>;
504 def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
505 (ins RegF64:$a, RegF64:$b),
506 "div.rn.f64\t$d, $a, $b",
507 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
508 Requires<[FDivNeedsRoundingMode]>;
509 def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
510 (ins RegF64:$a, f64imm:$b),
511 "div.rn.f64\t$d, $a, $b",
512 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
513 Requires<[FDivNeedsRoundingMode]>;
514 def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
515 (ins RegF64:$a, RegF64:$b),
516 "div.f64\t$d, $a, $b",
517 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
518 Requires<[FDivNoRoundingMode]>;
519 def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
520 (ins RegF64:$a, f64imm:$b),
521 "div.f64\t$d, $a, $b",
522 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
523 Requires<[FDivNoRoundingMode]>;
527 // Multi-operation hybrid instructions
529 // The selection of mad/fma is tricky. In some cases, they are the *same*
530 // instruction, but in other cases we may prefer one or the other. Also,
531 // different PTX versions differ on whether rounding mode flags are required.
532 // In the short term, mad is supported on all PTX versions and we use a
533 // default rounding mode no matter what shader model or PTX version.
534 // TODO: Allow the rounding mode to be selectable through llc.
535 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>,
536 Requires<[FMadNeedsRoundingMode, SupportsFMA]>;
537 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>,
538 Requires<[FMadNoRoundingMode, SupportsFMA]>;
540 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
542 def FSQRT32 : InstPTX<(outs RegF32:$d),
544 "sqrt.rn.f32\t$d, $a",
545 [(set RegF32:$d, (fsqrt RegF32:$a))]>;
547 def FSQRT64 : InstPTX<(outs RegF64:$d),
549 "sqrt.rn.f64\t$d, $a",
550 [(set RegF64:$d, (fsqrt RegF64:$a))]>;
552 def FSIN32 : InstPTX<(outs RegF32:$d),
554 "sin.approx.f32\t$d, $a",
555 [(set RegF32:$d, (fsin RegF32:$a))]>;
557 def FSIN64 : InstPTX<(outs RegF64:$d),
559 "sin.approx.f64\t$d, $a",
560 [(set RegF64:$d, (fsin RegF64:$a))]>;
562 def FCOS32 : InstPTX<(outs RegF32:$d),
564 "cos.approx.f32\t$d, $a",
565 [(set RegF32:$d, (fcos RegF32:$a))]>;
567 def FCOS64 : InstPTX<(outs RegF64:$d),
569 "cos.approx.f64\t$d, $a",
570 [(set RegF64:$d, (fcos RegF64:$a))]>;
573 ///===- Comparison and Selection Instructions -----------------------------===//
579 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
580 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
581 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
582 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
583 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
584 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
585 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">;
586 defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE, "le">;
587 defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT, "gt">;
588 defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE, "ge">;
592 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
593 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
594 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
595 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
596 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
597 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
598 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">;
599 defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE, "le">;
600 defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT, "gt">;
601 defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE, "ge">;
605 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
606 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
607 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
608 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
609 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
610 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
611 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">;
612 defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE, "le">;
613 defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT, "gt">;
614 defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">;
618 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUEQ, SETOEQ, "eq">;
619 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUNE, SETONE, "ne">;
620 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULT, SETOLT, "lt">;
621 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULE, SETOLE, "le">;
622 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGT, SETOGT, "gt">;
623 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGE, SETOGE, "ge">;
627 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUEQ, SETOEQ, "eq">;
628 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUNE, SETONE, "ne">;
629 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULT, SETOLT, "lt">;
630 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULE, SETOLE, "le">;
631 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGT, SETOGT, "gt">;
632 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGE, SETOGE, "ge">;
636 defm SELPi16 : PTX_SELP<RegI16, "u16", i16imm, imm>;
637 defm SELPi32 : PTX_SELP<RegI32, "u32", i32imm, imm>;
638 defm SELPi64 : PTX_SELP<RegI64, "u64", i64imm, imm>;
639 defm SELPf32 : PTX_SELP<RegF32, "f32", f32imm, fpimm>;
640 defm SELPf64 : PTX_SELP<RegF64, "f64", f64imm, fpimm>;
642 ///===- Logic and Shift Instructions --------------------------------------===//
644 defm SHL : INT3ntnc<"shl.b", PTXshl>;
645 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
646 defm SRA : INT3ntnc<"shr.s", PTXsra>;
648 defm AND : PTX_LOGIC<"and", and>;
649 defm OR : PTX_LOGIC<"or", or>;
650 defm XOR : PTX_LOGIC<"xor", xor>;
652 ///===- Data Movement and Conversion Instructions -------------------------===//
655 // Implement the anyext instruction in terms of the PTX cvt instructions.
656 //def : Pat<(i32 (anyext RegI16:$a)), (CVT_u32_u16 RegI16:$a)>;
657 //def : Pat<(i64 (anyext RegI16:$a)), (CVT_u64_u16 RegI16:$a)>;
658 //def : Pat<(i64 (anyext RegI32:$a)), (CVT_u64_u32 RegI32:$a)>;
661 // These instructions implement the bit-wise conversion between integer and
662 // floating-point types.
664 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a", []>;
666 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "mov.b32\t$d, $a", []>;
668 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "mov.b64\t$d, $a", []>;
670 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "mov.b64\t$d, $a", []>;
672 let neverHasSideEffects = 1 in {
674 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
676 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
678 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
680 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
682 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
684 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
687 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
689 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
690 [(set RegPred:$d, imm:$a)]>;
692 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
693 [(set RegI16:$d, imm:$a)]>;
695 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
696 [(set RegI32:$d, imm:$a)]>;
698 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
699 [(set RegI64:$d, imm:$a)]>;
701 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
702 [(set RegF32:$d, fpimm:$a)]>;
704 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
705 [(set RegF64:$d, fpimm:$a)]>;
708 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
710 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
711 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
713 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
714 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
717 // PTX cvt instructions
718 // Note all of these may actually be used, we just define all possible patterns
723 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a", []>;
725 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a", []>;
727 : InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a", []>;
729 : InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.s16.f32\t$d, $a", []>;
731 : InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a", []>;
733 : InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.s16.f64\t$d, $a", []>;
737 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a", []>;
739 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.s32.s16\t$d, $a", []>;
741 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a", []>;
743 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a", []>;
745 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.s32.f32\t$d, $a", []>;
747 : InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a", []>;
749 : InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.s32.f64\t$d, $a", []>;
753 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a", []>;
755 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.s64.s16\t$d, $a", []>;
757 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a", []>;
759 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.s64.s32\t$d, $a", []>;
761 : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a", []>;
763 : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.s64.f32\t$d, $a", []>;
765 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a", []>;
767 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.s64.f64\t$d, $a", []>;
771 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a", []>;
773 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.s16\t$d, $a", []>;
775 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a", []>;
777 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.s32\t$d, $a", []>;
779 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a", []>;
781 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.s64\t$d, $a", []>;
783 : InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a", []>;
787 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a", []>;
789 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.s16\t$d, $a", []>;
791 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a", []>;
793 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.s32\t$d, $a", []>;
795 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a", []>;
797 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.s64\t$d, $a", []>;
799 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", []>;
802 // Type conversion notes:
803 // - PTX does not directly support converting a predicate to a value, so we
804 // use a select instruction to select either 0 or 1 (integer or fp) based
805 // on the truth value of the predicate.
806 // - PTX does not directly support converting to a predicate type, so we fake it
807 // by performing a greater-than test between the value and zero. This follows
808 // the C convention that any non-zero value is equivalent to 'true'.
810 // Conversion to pred
811 def : Pat<(i1 (trunc RegI16:$a)), (SETPGTu16ri RegI16:$a, 0)>;
812 def : Pat<(i1 (trunc RegI32:$a)), (SETPGTu32ri RegI32:$a, 0)>;
813 def : Pat<(i1 (trunc RegI64:$a)), (SETPGTu64ri RegI64:$a, 0)>;
814 def : Pat<(i1 (fp_to_uint RegF32:$a)), (SETPGTu32ri (MOVi32f32 RegF32:$a), 0)>;
815 def : Pat<(i1 (fp_to_uint RegF64:$a)), (SETPGTu64ri (MOVi64f64 RegF64:$a), 0)>;
818 def : Pat<(i16 (anyext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>;
819 def : Pat<(i16 (sext RegPred:$a)), (SELPi16ii RegPred:$a, 0xFFFF, 0)>;
820 def : Pat<(i16 (zext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>;
821 def : Pat<(i16 (trunc RegI32:$a)), (CVTu16u32 RegI32:$a)>;
822 def : Pat<(i16 (trunc RegI64:$a)), (CVTu16u64 RegI64:$a)>;
823 def : Pat<(i16 (fp_to_uint RegF32:$a)), (CVTu16f32 RegF32:$a)>;
824 def : Pat<(i16 (fp_to_sint RegF32:$a)), (CVTs16f32 RegF32:$a)>;
825 def : Pat<(i16 (fp_to_uint RegF64:$a)), (CVTu16f64 RegF64:$a)>;
826 def : Pat<(i16 (fp_to_sint RegF64:$a)), (CVTs16f64 RegF64:$a)>;
829 def : Pat<(i32 (anyext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>;
830 def : Pat<(i32 (sext RegPred:$a)), (SELPi32ii RegPred:$a, 0xFFFFFFFF, 0)>;
831 def : Pat<(i32 (zext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>;
832 def : Pat<(i32 (anyext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
833 def : Pat<(i32 (sext RegI16:$a)), (CVTs32s16 RegI16:$a)>;
834 def : Pat<(i32 (zext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
835 def : Pat<(i32 (trunc RegI64:$a)), (CVTu32u64 RegI64:$a)>;
836 def : Pat<(i32 (fp_to_uint RegF32:$a)), (CVTu32f32 RegF32:$a)>;
837 def : Pat<(i32 (fp_to_sint RegF32:$a)), (CVTs32f32 RegF32:$a)>;
838 def : Pat<(i32 (fp_to_uint RegF64:$a)), (CVTu32f64 RegF64:$a)>;
839 def : Pat<(i32 (fp_to_sint RegF64:$a)), (CVTs32f64 RegF64:$a)>;
840 def : Pat<(i32 (bitconvert RegF32:$a)), (MOVi32f32 RegF32:$a)>;
843 def : Pat<(i64 (anyext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>;
844 def : Pat<(i64 (sext RegPred:$a)), (SELPi64ii RegPred:$a,
845 0xFFFFFFFFFFFFFFFF, 0)>;
846 def : Pat<(i64 (zext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>;
847 def : Pat<(i64 (anyext RegI16:$a)), (CVTu64u16 RegI16:$a)>;
848 def : Pat<(i64 (sext RegI16:$a)), (CVTs64s16 RegI16:$a)>;
849 def : Pat<(i64 (zext RegI16:$a)), (CVTu64u16 RegI16:$a)>;
850 def : Pat<(i64 (anyext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
851 def : Pat<(i64 (sext RegI32:$a)), (CVTs64s32 RegI32:$a)>;
852 def : Pat<(i64 (zext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
853 def : Pat<(i64 (fp_to_uint RegF32:$a)), (CVTu64f32 RegF32:$a)>;
854 def : Pat<(i64 (fp_to_sint RegF32:$a)), (CVTs64f32 RegF32:$a)>;
855 def : Pat<(i64 (fp_to_uint RegF64:$a)), (CVTu64f64 RegF64:$a)>;
856 def : Pat<(i64 (fp_to_sint RegF64:$a)), (CVTs64f64 RegF64:$a)>;
857 def : Pat<(i64 (bitconvert RegF64:$a)), (MOVi64f64 RegF64:$a)>;
860 def : Pat<(f32 (uint_to_fp RegPred:$a)), (SELPf32rr RegPred:$a,
861 (MOVf32i32 0x3F800000), (MOVf32i32 0))>;
862 def : Pat<(f32 (uint_to_fp RegI16:$a)), (CVTf32u16 RegI16:$a)>;
863 def : Pat<(f32 (sint_to_fp RegI16:$a)), (CVTf32s16 RegI16:$a)>;
864 def : Pat<(f32 (uint_to_fp RegI32:$a)), (CVTf32u32 RegI32:$a)>;
865 def : Pat<(f32 (sint_to_fp RegI32:$a)), (CVTf32s32 RegI32:$a)>;
866 def : Pat<(f32 (uint_to_fp RegI64:$a)), (CVTf32u64 RegI64:$a)>;
867 def : Pat<(f32 (sint_to_fp RegI64:$a)), (CVTf32s64 RegI64:$a)>;
868 def : Pat<(f32 (fround RegF64:$a)), (CVTf32f64 RegF64:$a)>;
869 def : Pat<(f32 (bitconvert RegI32:$a)), (MOVf32i32 RegI32:$a)>;
872 def : Pat<(f64 (uint_to_fp RegPred:$a)), (SELPf64rr RegPred:$a,
873 (MOVf64i64 0x3F80000000000000), (MOVf64i64 0))>;
874 def : Pat<(f64 (uint_to_fp RegI16:$a)), (CVTf64u16 RegI16:$a)>;
875 def : Pat<(f64 (sint_to_fp RegI16:$a)), (CVTf64s16 RegI16:$a)>;
876 def : Pat<(f64 (uint_to_fp RegI32:$a)), (CVTf64u32 RegI32:$a)>;
877 def : Pat<(f64 (sint_to_fp RegI32:$a)), (CVTf64s32 RegI32:$a)>;
878 def : Pat<(f64 (uint_to_fp RegI64:$a)), (CVTf64u64 RegI64:$a)>;
879 def : Pat<(f64 (sint_to_fp RegI64:$a)), (CVTf64s64 RegI64:$a)>;
880 def : Pat<(f64 (fextend RegF32:$a)), (CVTf64f32 RegF32:$a)>;
881 def : Pat<(f64 (bitconvert RegI64:$a)), (MOVf64i64 RegI64:$a)>;
884 ///===- Control Flow Instructions -----------------------------------------===//
886 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
888 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
891 let isBranch = 1, isTerminator = 1 in {
892 // FIXME: The pattern part is blank because I cannot (or do not yet know
893 // how to) use the first operand of PredicateOperand (a RegPred register) here
895 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
896 [/*(brcond pred:$_p, bb:$d)*/]>;
899 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
900 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
901 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
904 let hasSideEffects = 1 in {
905 def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>;
908 ///===- Parameter Passing Pseudo-Instructions -----------------------------===//
910 def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b),
911 "mov.pred\t$a, %param$b", []>;
912 def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b),
913 "mov.b16\t$a, %param$b", []>;
914 def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b),
915 "mov.b32\t$a, %param$b", []>;
916 def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b),
917 "mov.b64\t$a, %param$b", []>;
918 def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b),
919 "mov.f32\t$a, %param$b", []>;
920 def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b),
921 "mov.f64\t$a, %param$b", []>;
923 def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>;
924 def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>;
925 def WRITEPARAMI32 : InstPTX<(outs), (ins RegI32:$a), "//w", []>;
926 def WRITEPARAMI64 : InstPTX<(outs), (ins RegI64:$a), "//w", []>;
927 def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>;
928 def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>;
930 ///===- Intrinsic Instructions --------------------------------------------===//
931 include "PTXIntrinsicInstrInfo.td"
933 ///===- Load/Store Instructions -------------------------------------------===//
934 include "PTXInstrLoadStore.td"