1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
28 // Shader Model Support
29 def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">;
30 def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">;
31 def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">;
32 def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
39 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
40 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
43 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
44 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
46 //===----------------------------------------------------------------------===//
47 // Instruction Pattern Stuff
48 //===----------------------------------------------------------------------===//
50 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
52 const PointerType *PT;
53 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
54 (PT = dyn_cast<PointerType>(Src->getType())))
55 return PT->getAddressSpace() == PTX::GLOBAL;
59 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
61 const PointerType *PT;
62 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
63 (PT = dyn_cast<PointerType>(Src->getType())))
64 return PT->getAddressSpace() == PTX::CONSTANT;
68 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
70 const PointerType *PT;
71 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
72 (PT = dyn_cast<PointerType>(Src->getType())))
73 return PT->getAddressSpace() == PTX::LOCAL;
77 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
79 const PointerType *PT;
80 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
81 (PT = dyn_cast<PointerType>(Src->getType())))
82 return PT->getAddressSpace() == PTX::PARAMETER;
86 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
88 const PointerType *PT;
89 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
90 (PT = dyn_cast<PointerType>(Src->getType())))
91 return PT->getAddressSpace() == PTX::SHARED;
96 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
98 const PointerType *PT;
99 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
100 (PT = dyn_cast<PointerType>(Src->getType())))
101 return PT->getAddressSpace() == PTX::GLOBAL;
106 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
108 const PointerType *PT;
109 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
110 (PT = dyn_cast<PointerType>(Src->getType())))
111 return PT->getAddressSpace() == PTX::LOCAL;
116 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
118 const PointerType *PT;
119 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
120 (PT = dyn_cast<PointerType>(Src->getType())))
121 return PT->getAddressSpace() == PTX::PARAMETER;
126 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
128 const PointerType *PT;
129 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
130 (PT = dyn_cast<PointerType>(Src->getType())))
131 return PT->getAddressSpace() == PTX::SHARED;
136 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
137 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
138 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
139 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
140 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
141 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
144 def MEMri32 : Operand<i32> {
145 let PrintMethod = "printMemOperand";
146 let MIOperandInfo = (ops RegI32, i32imm);
148 def MEMri64 : Operand<i64> {
149 let PrintMethod = "printMemOperand";
150 let MIOperandInfo = (ops RegI64, i64imm);
152 def MEMii32 : Operand<i32> {
153 let PrintMethod = "printMemOperand";
154 let MIOperandInfo = (ops i32imm, i32imm);
156 def MEMii64 : Operand<i64> {
157 let PrintMethod = "printMemOperand";
158 let MIOperandInfo = (ops i64imm, i64imm);
160 // The operand here does not correspond to an actual address, so we
161 // can use i32 in 64-bit address modes.
162 def MEMpi : Operand<i32> {
163 let PrintMethod = "printParamOperand";
164 let MIOperandInfo = (ops i32imm);
166 def MEMret : Operand<i32> {
167 let PrintMethod = "printReturnOperand";
168 let MIOperandInfo = (ops i32imm);
171 // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
172 // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
174 // def PTXcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PTXCallSeqStart,
175 // [SDNPHasChain, SDNPOutGlue]>;
176 // def PTXcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PTXCallSeqEnd,
177 // [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
179 def PTXcall : SDNode<"PTXISD::CALL", SDTNone,
180 [SDNPHasChain, SDNPVariadic, SDNPOptInGlue, SDNPOutGlue]>;
183 // Branch & call targets have OtherVT type.
184 def brtarget : Operand<OtherVT>;
185 def calltarget : Operand<i32>;
187 //===----------------------------------------------------------------------===//
188 // PTX Specific Node Definitions
189 //===----------------------------------------------------------------------===//
191 // PTX allow generic 3-reg shifts like shl r0, r1, r2
192 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
193 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
194 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
197 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
199 : SDNode<"PTXISD::RET", SDTNone,
200 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
202 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
204 // Load/store .param space
206 : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>,
207 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
209 : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>,
210 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
213 : SDNode<"PTXISD::READ_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>,
214 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
216 : SDNode<"PTXISD::WRITE_PARAM", SDTypeProfile<0, 1, []>,
217 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
219 //===----------------------------------------------------------------------===//
220 // Instruction Class Templates
221 //===----------------------------------------------------------------------===//
223 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
224 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
225 def rr32 : InstPTX<(outs RegF32:$d),
227 !strconcat(opcstr, ".f32\t$d, $a"),
228 [(set RegF32:$d, (opnode RegF32:$a))]>;
229 def ri32 : InstPTX<(outs RegF32:$d),
231 !strconcat(opcstr, ".f32\t$d, $a"),
232 [(set RegF32:$d, (opnode fpimm:$a))]>;
233 def rr64 : InstPTX<(outs RegF64:$d),
235 !strconcat(opcstr, ".f64\t$d, $a"),
236 [(set RegF64:$d, (opnode RegF64:$a))]>;
237 def ri64 : InstPTX<(outs RegF64:$d),
239 !strconcat(opcstr, ".f64\t$d, $a"),
240 [(set RegF64:$d, (opnode fpimm:$a))]>;
243 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
244 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
245 def rr32 : InstPTX<(outs RegF32:$d),
246 (ins RegF32:$a, RegF32:$b),
247 !strconcat(opcstr, ".f32\t$d, $a, $b"),
248 [(set RegF32:$d, (opnode RegF32:$a, RegF32:$b))]>;
249 def ri32 : InstPTX<(outs RegF32:$d),
250 (ins RegF32:$a, f32imm:$b),
251 !strconcat(opcstr, ".f32\t$d, $a, $b"),
252 [(set RegF32:$d, (opnode RegF32:$a, fpimm:$b))]>;
253 def rr64 : InstPTX<(outs RegF64:$d),
254 (ins RegF64:$a, RegF64:$b),
255 !strconcat(opcstr, ".f64\t$d, $a, $b"),
256 [(set RegF64:$d, (opnode RegF64:$a, RegF64:$b))]>;
257 def ri64 : InstPTX<(outs RegF64:$d),
258 (ins RegF64:$a, f64imm:$b),
259 !strconcat(opcstr, ".f64\t$d, $a, $b"),
260 [(set RegF64:$d, (opnode RegF64:$a, fpimm:$b))]>;
263 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
264 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
265 def rrr32 : InstPTX<(outs RegF32:$d),
266 (ins RegF32:$a, RegF32:$b, RegF32:$c),
267 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
268 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
271 def rri32 : InstPTX<(outs RegF32:$d),
272 (ins RegF32:$a, RegF32:$b, f32imm:$c),
273 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
274 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
277 def rrr64 : InstPTX<(outs RegF64:$d),
278 (ins RegF64:$a, RegF64:$b, RegF64:$c),
279 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
280 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
283 def rri64 : InstPTX<(outs RegF64:$d),
284 (ins RegF64:$a, RegF64:$b, f64imm:$c),
285 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
286 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
291 multiclass INT3<string opcstr, SDNode opnode> {
292 def rr16 : InstPTX<(outs RegI16:$d),
293 (ins RegI16:$a, RegI16:$b),
294 !strconcat(opcstr, ".u16\t$d, $a, $b"),
295 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
296 def ri16 : InstPTX<(outs RegI16:$d),
297 (ins RegI16:$a, i16imm:$b),
298 !strconcat(opcstr, ".u16\t$d, $a, $b"),
299 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
300 def rr32 : InstPTX<(outs RegI32:$d),
301 (ins RegI32:$a, RegI32:$b),
302 !strconcat(opcstr, ".u32\t$d, $a, $b"),
303 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
304 def ri32 : InstPTX<(outs RegI32:$d),
305 (ins RegI32:$a, i32imm:$b),
306 !strconcat(opcstr, ".u32\t$d, $a, $b"),
307 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
308 def rr64 : InstPTX<(outs RegI64:$d),
309 (ins RegI64:$a, RegI64:$b),
310 !strconcat(opcstr, ".u64\t$d, $a, $b"),
311 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
312 def ri64 : InstPTX<(outs RegI64:$d),
313 (ins RegI64:$a, i64imm:$b),
314 !strconcat(opcstr, ".u64\t$d, $a, $b"),
315 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
318 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
319 def ripreds : InstPTX<(outs RegPred:$d),
320 (ins RegPred:$a, i1imm:$b),
321 !strconcat(opcstr, ".pred\t$d, $a, $b"),
322 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
323 def rrpreds : InstPTX<(outs RegPred:$d),
324 (ins RegPred:$a, RegPred:$b),
325 !strconcat(opcstr, ".pred\t$d, $a, $b"),
326 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
327 def rr16 : InstPTX<(outs RegI16:$d),
328 (ins RegI16:$a, RegI16:$b),
329 !strconcat(opcstr, ".b16\t$d, $a, $b"),
330 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
331 def ri16 : InstPTX<(outs RegI16:$d),
332 (ins RegI16:$a, i16imm:$b),
333 !strconcat(opcstr, ".b16\t$d, $a, $b"),
334 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
335 def rr32 : InstPTX<(outs RegI32:$d),
336 (ins RegI32:$a, RegI32:$b),
337 !strconcat(opcstr, ".b32\t$d, $a, $b"),
338 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
339 def ri32 : InstPTX<(outs RegI32:$d),
340 (ins RegI32:$a, i32imm:$b),
341 !strconcat(opcstr, ".b32\t$d, $a, $b"),
342 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
343 def rr64 : InstPTX<(outs RegI64:$d),
344 (ins RegI64:$a, RegI64:$b),
345 !strconcat(opcstr, ".b64\t$d, $a, $b"),
346 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
347 def ri64 : InstPTX<(outs RegI64:$d),
348 (ins RegI64:$a, i64imm:$b),
349 !strconcat(opcstr, ".b64\t$d, $a, $b"),
350 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
353 multiclass INT3ntnc<string opcstr, SDNode opnode> {
354 def rr16 : InstPTX<(outs RegI16:$d),
355 (ins RegI16:$a, RegI16:$b),
356 !strconcat(opcstr, "16\t$d, $a, $b"),
357 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
358 def rr32 : InstPTX<(outs RegI32:$d),
359 (ins RegI32:$a, RegI32:$b),
360 !strconcat(opcstr, "32\t$d, $a, $b"),
361 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
362 def rr64 : InstPTX<(outs RegI64:$d),
363 (ins RegI64:$a, RegI64:$b),
364 !strconcat(opcstr, "64\t$d, $a, $b"),
365 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
366 def ri16 : InstPTX<(outs RegI16:$d),
367 (ins RegI16:$a, i16imm:$b),
368 !strconcat(opcstr, "16\t$d, $a, $b"),
369 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
370 def ri32 : InstPTX<(outs RegI32:$d),
371 (ins RegI32:$a, i32imm:$b),
372 !strconcat(opcstr, "32\t$d, $a, $b"),
373 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
374 def ri64 : InstPTX<(outs RegI64:$d),
375 (ins RegI64:$a, i64imm:$b),
376 !strconcat(opcstr, "64\t$d, $a, $b"),
377 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
378 def ir16 : InstPTX<(outs RegI16:$d),
379 (ins i16imm:$a, RegI16:$b),
380 !strconcat(opcstr, "16\t$d, $a, $b"),
381 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
382 def ir32 : InstPTX<(outs RegI32:$d),
383 (ins i32imm:$a, RegI32:$b),
384 !strconcat(opcstr, "32\t$d, $a, $b"),
385 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
386 def ir64 : InstPTX<(outs RegI64:$d),
387 (ins i64imm:$a, RegI64:$b),
388 !strconcat(opcstr, "64\t$d, $a, $b"),
389 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
392 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
393 CondCode cmp, string cmpstr> {
394 // TODO support 5-operand format: p|q, a, b, c
397 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
398 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
399 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
401 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
402 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
403 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
406 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
407 !strconcat("setp.", cmpstr, ".and.", regclsname,
409 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
411 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
412 !strconcat("setp.", cmpstr, ".and.", regclsname,
414 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
417 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
418 !strconcat("setp.", cmpstr, ".or.", regclsname,
420 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
422 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
423 !strconcat("setp.", cmpstr, ".or.", regclsname,
425 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
427 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
428 !strconcat("setp.", cmpstr, ".xor.", regclsname,
430 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
432 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
433 !strconcat("setp.", cmpstr, ".xor.", regclsname,
435 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
439 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
440 !strconcat("setp.", cmpstr, ".and.", regclsname,
441 "\t$p, $a, $b, !$c"),
442 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp),
443 (not RegPred:$c)))]>;
445 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
446 !strconcat("setp.", cmpstr, ".and.", regclsname,
447 "\t$p, $a, $b, !$c"),
448 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
449 (not RegPred:$c)))]>;
451 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
452 !strconcat("setp.", cmpstr, ".or.", regclsname,
453 "\t$p, $a, $b, !$c"),
454 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp),
455 (not RegPred:$c)))]>;
457 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
458 !strconcat("setp.", cmpstr, ".or.", regclsname,
459 "\t$p, $a, $b, !$c"),
460 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp),
461 (not RegPred:$c)))]>;
463 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
464 !strconcat("setp.", cmpstr, ".xor.", regclsname,
465 "\t$p, $a, $b, !$c"),
466 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp),
467 (not RegPred:$c)))]>;
469 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
470 !strconcat("setp.", cmpstr, ".xor.", regclsname,
471 "\t$p, $a, $b, !$c"),
472 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
473 (not RegPred:$c)))]>;
476 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
477 CondCode ucmp, CondCode ocmp, string cmpstr> {
478 // TODO support 5-operand format: p|q, a, b, c
481 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
482 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
483 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
485 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
486 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
487 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
490 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
491 !strconcat("setp.", cmpstr, "u.and.", regclsname,
493 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
496 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
497 !strconcat("setp.", cmpstr, ".and.", regclsname,
499 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
503 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
504 !strconcat("setp.", cmpstr, "u.or.", regclsname,
506 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
508 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
509 !strconcat("setp.", cmpstr, ".or.", regclsname,
511 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
514 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
515 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
517 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
520 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
521 !strconcat("setp.", cmpstr, ".xor.", regclsname,
523 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
527 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
528 !strconcat("setp.", cmpstr, "u.and.", regclsname,
529 "\t$p, $a, $b, !$c"),
530 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp),
531 (not RegPred:$c)))]>;
533 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
534 !strconcat("setp.", cmpstr, ".and.", regclsname,
535 "\t$p, $a, $b, !$c"),
536 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp),
537 (not RegPred:$c)))]>;
540 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
541 !strconcat("setp.", cmpstr, "u.or.", regclsname,
542 "\t$p, $a, $b, !$c"),
543 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp),
544 (not RegPred:$c)))]>;
546 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
547 !strconcat("setp.", cmpstr, ".or.", regclsname,
548 "\t$p, $a, $b, !$c"),
549 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp),
550 (not RegPred:$c)))]>;
553 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
554 !strconcat("setp.", cmpstr, "u.xor.", regclsname,
555 "\t$p, $a, $b, !$c"),
556 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp),
557 (not RegPred:$c)))]>;
559 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
560 !strconcat("setp.", cmpstr, ".xor.", regclsname,
561 "\t$p, $a, $b, !$c"),
562 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp),
563 (not RegPred:$c)))]>;
566 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
568 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
569 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
570 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
573 multiclass PTX_LD<string opstr, string typestr,
574 RegisterClass RC, PatFrag pat_load> {
575 def rr32 : InstPTX<(outs RC:$d),
577 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
578 [(set RC:$d, (pat_load ADDRrr32:$a))]>,
579 Requires<[Use32BitAddresses]>;
580 def rr64 : InstPTX<(outs RC:$d),
582 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
583 [(set RC:$d, (pat_load ADDRrr64:$a))]>,
584 Requires<[Use64BitAddresses]>;
585 def ri32 : InstPTX<(outs RC:$d),
587 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
588 [(set RC:$d, (pat_load ADDRri32:$a))]>,
589 Requires<[Use32BitAddresses]>;
590 def ri64 : InstPTX<(outs RC:$d),
592 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
593 [(set RC:$d, (pat_load ADDRri64:$a))]>,
594 Requires<[Use64BitAddresses]>;
595 def ii32 : InstPTX<(outs RC:$d),
597 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
598 [(set RC:$d, (pat_load ADDRii32:$a))]>,
599 Requires<[Use32BitAddresses]>;
600 def ii64 : InstPTX<(outs RC:$d),
602 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
603 [(set RC:$d, (pat_load ADDRii64:$a))]>,
604 Requires<[Use64BitAddresses]>;
607 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
608 defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
609 defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
610 defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
611 defm f32 : PTX_LD<opstr, ".f32", RegF32, pat_load>;
612 defm f64 : PTX_LD<opstr, ".f64", RegF64, pat_load>;
615 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC,
617 def rr32 : InstPTX<(outs),
618 (ins RC:$d, MEMri32:$a),
619 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
620 [(pat_store RC:$d, ADDRrr32:$a)]>,
621 Requires<[Use32BitAddresses]>;
622 def rr64 : InstPTX<(outs),
623 (ins RC:$d, MEMri64:$a),
624 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
625 [(pat_store RC:$d, ADDRrr64:$a)]>,
626 Requires<[Use64BitAddresses]>;
627 def ri32 : InstPTX<(outs),
628 (ins RC:$d, MEMri32:$a),
629 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
630 [(pat_store RC:$d, ADDRri32:$a)]>,
631 Requires<[Use32BitAddresses]>;
632 def ri64 : InstPTX<(outs),
633 (ins RC:$d, MEMri64:$a),
634 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
635 [(pat_store RC:$d, ADDRri64:$a)]>,
636 Requires<[Use64BitAddresses]>;
637 def ii32 : InstPTX<(outs),
638 (ins RC:$d, MEMii32:$a),
639 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
640 [(pat_store RC:$d, ADDRii32:$a)]>,
641 Requires<[Use32BitAddresses]>;
642 def ii64 : InstPTX<(outs),
643 (ins RC:$d, MEMii64:$a),
644 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
645 [(pat_store RC:$d, ADDRii64:$a)]>,
646 Requires<[Use64BitAddresses]>;
649 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
650 defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
651 defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
652 defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
653 defm f32 : PTX_ST<opstr, ".f32", RegF32, pat_store>;
654 defm f64 : PTX_ST<opstr, ".f64", RegF64, pat_store>;
657 //===----------------------------------------------------------------------===//
659 //===----------------------------------------------------------------------===//
661 ///===- Integer Arithmetic Instructions -----------------------------------===//
663 defm ADD : INT3<"add", add>;
664 defm SUB : INT3<"sub", sub>;
665 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
666 defm DIV : INT3<"div", udiv>;
667 defm REM : INT3<"rem", urem>;
669 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
671 // Standard Unary Operations
672 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
674 // Standard Binary Operations
675 defm FADD : PTX_FLOAT_3OP<"add.rn", fadd>;
676 defm FSUB : PTX_FLOAT_3OP<"sub.rn", fsub>;
677 defm FMUL : PTX_FLOAT_3OP<"mul.rn", fmul>;
679 // For floating-point division:
680 // SM_13+ defaults to .rn for f32 and f64,
681 // SM10 must *not* provide a rounding
684 // - Allow user selection of rounding modes for fdiv
685 // - Add support for -prec-div=false (.approx)
687 def FDIVrr32SM13 : InstPTX<(outs RegF32:$d),
688 (ins RegF32:$a, RegF32:$b),
689 "div.rn.f32\t$d, $a, $b",
690 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
691 Requires<[FDivNeedsRoundingMode]>;
692 def FDIVri32SM13 : InstPTX<(outs RegF32:$d),
693 (ins RegF32:$a, f32imm:$b),
694 "div.rn.f32\t$d, $a, $b",
695 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
696 Requires<[FDivNeedsRoundingMode]>;
697 def FDIVrr32SM10 : InstPTX<(outs RegF32:$d),
698 (ins RegF32:$a, RegF32:$b),
699 "div.f32\t$d, $a, $b",
700 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
701 Requires<[FDivNoRoundingMode]>;
702 def FDIVri32SM10 : InstPTX<(outs RegF32:$d),
703 (ins RegF32:$a, f32imm:$b),
704 "div.f32\t$d, $a, $b",
705 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
706 Requires<[FDivNoRoundingMode]>;
708 def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
709 (ins RegF64:$a, RegF64:$b),
710 "div.rn.f64\t$d, $a, $b",
711 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
712 Requires<[FDivNeedsRoundingMode]>;
713 def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
714 (ins RegF64:$a, f64imm:$b),
715 "div.rn.f64\t$d, $a, $b",
716 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
717 Requires<[FDivNeedsRoundingMode]>;
718 def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
719 (ins RegF64:$a, RegF64:$b),
720 "div.f64\t$d, $a, $b",
721 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
722 Requires<[FDivNoRoundingMode]>;
723 def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
724 (ins RegF64:$a, f64imm:$b),
725 "div.f64\t$d, $a, $b",
726 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
727 Requires<[FDivNoRoundingMode]>;
731 // Multi-operation hybrid instructions
733 // The selection of mad/fma is tricky. In some cases, they are the *same*
734 // instruction, but in other cases we may prefer one or the other. Also,
735 // different PTX versions differ on whether rounding mode flags are required.
736 // In the short term, mad is supported on all PTX versions and we use a
737 // default rounding mode no matter what shader model or PTX version.
738 // TODO: Allow the rounding mode to be selectable through llc.
739 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>,
740 Requires<[FMadNeedsRoundingMode, SupportsFMA]>;
741 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>,
742 Requires<[FMadNoRoundingMode, SupportsFMA]>;
744 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
746 def FSQRT32 : InstPTX<(outs RegF32:$d),
748 "sqrt.rn.f32\t$d, $a",
749 [(set RegF32:$d, (fsqrt RegF32:$a))]>;
751 def FSQRT64 : InstPTX<(outs RegF64:$d),
753 "sqrt.rn.f64\t$d, $a",
754 [(set RegF64:$d, (fsqrt RegF64:$a))]>;
756 def FSIN32 : InstPTX<(outs RegF32:$d),
758 "sin.approx.f32\t$d, $a",
759 [(set RegF32:$d, (fsin RegF32:$a))]>;
761 def FSIN64 : InstPTX<(outs RegF64:$d),
763 "sin.approx.f64\t$d, $a",
764 [(set RegF64:$d, (fsin RegF64:$a))]>;
766 def FCOS32 : InstPTX<(outs RegF32:$d),
768 "cos.approx.f32\t$d, $a",
769 [(set RegF32:$d, (fcos RegF32:$a))]>;
771 def FCOS64 : InstPTX<(outs RegF64:$d),
773 "cos.approx.f64\t$d, $a",
774 [(set RegF64:$d, (fcos RegF64:$a))]>;
777 ///===- Comparison and Selection Instructions -----------------------------===//
783 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
784 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
785 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
786 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
787 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
788 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
789 defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT, "lt">;
790 defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE, "le">;
791 defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT, "gt">;
792 defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE, "ge">;
796 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
797 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
798 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
799 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
800 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
801 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
802 defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT, "lt">;
803 defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE, "le">;
804 defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT, "gt">;
805 defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE, "ge">;
809 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
810 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
811 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
812 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
813 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
814 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
815 defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT, "lt">;
816 defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE, "le">;
817 defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT, "gt">;
818 defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">;
822 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", SETUEQ, SETOEQ, "eq">;
823 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", SETUNE, SETONE, "ne">;
824 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
825 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", SETULE, SETOLE, "le">;
826 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", SETUGT, SETOGT, "gt">;
827 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", SETUGE, SETOGE, "ge">;
831 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", SETUEQ, SETOEQ, "eq">;
832 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", SETUNE, SETONE, "ne">;
833 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
834 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", SETULE, SETOLE, "le">;
835 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", SETUGT, SETOGT, "gt">;
836 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", SETUGE, SETOGE, "ge">;
840 defm PTX_SELPu16 : PTX_SELP<RegI16, "u16">;
841 defm PTX_SELPu32 : PTX_SELP<RegI32, "u32">;
842 defm PTX_SELPu64 : PTX_SELP<RegI64, "u64">;
843 defm PTX_SELPf32 : PTX_SELP<RegF32, "f32">;
844 defm PTX_SELPf64 : PTX_SELP<RegF64, "f64">;
846 ///===- Logic and Shift Instructions --------------------------------------===//
848 defm SHL : INT3ntnc<"shl.b", PTXshl>;
849 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
850 defm SRA : INT3ntnc<"shr.s", PTXsra>;
852 defm AND : PTX_LOGIC<"and", and>;
853 defm OR : PTX_LOGIC<"or", or>;
854 defm XOR : PTX_LOGIC<"xor", xor>;
856 ///===- Data Movement and Conversion Instructions -------------------------===//
858 let neverHasSideEffects = 1 in {
860 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
862 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
864 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
866 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
868 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
870 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
873 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
875 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
876 [(set RegPred:$d, imm:$a)]>;
878 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
879 [(set RegI16:$d, imm:$a)]>;
881 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
882 [(set RegI32:$d, imm:$a)]>;
884 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
885 [(set RegI64:$d, imm:$a)]>;
887 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
888 [(set RegF32:$d, fpimm:$a)]>;
890 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
891 [(set RegF64:$d, fpimm:$a)]>;
894 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
896 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
897 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
899 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
900 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
904 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
905 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
906 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
907 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
909 // These instructions are used to load/store from the .param space for
910 // device and kernel parameters
912 let hasSideEffects = 1 in {
913 def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
914 "ld.param.pred\t$d, [$a]",
915 [(set RegPred:$d, (PTXloadparam timm:$a))]>;
916 def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
917 "ld.param.u16\t$d, [$a]",
918 [(set RegI16:$d, (PTXloadparam timm:$a))]>;
919 def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
920 "ld.param.u32\t$d, [$a]",
921 [(set RegI32:$d, (PTXloadparam timm:$a))]>;
922 def LDpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
923 "ld.param.u64\t$d, [$a]",
924 [(set RegI64:$d, (PTXloadparam timm:$a))]>;
925 def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
926 "ld.param.f32\t$d, [$a]",
927 [(set RegF32:$d, (PTXloadparam timm:$a))]>;
928 def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
929 "ld.param.f64\t$d, [$a]",
930 [(set RegF64:$d, (PTXloadparam timm:$a))]>;
932 def STpiPred : InstPTX<(outs), (ins MEMpi:$d, RegPred:$a),
933 "st.param.pred\t[$d], $a",
934 [(PTXstoreparam timm:$d, RegPred:$a)]>;
935 def STpiU16 : InstPTX<(outs), (ins MEMpi:$d, RegI16:$a),
936 "st.param.u16\t[$d], $a",
937 [(PTXstoreparam timm:$d, RegI16:$a)]>;
938 def STpiU32 : InstPTX<(outs), (ins MEMpi:$d, RegI32:$a),
939 "st.param.u32\t[$d], $a",
940 [(PTXstoreparam timm:$d, RegI32:$a)]>;
941 def STpiU64 : InstPTX<(outs), (ins MEMpi:$d, RegI64:$a),
942 "st.param.u64\t[$d], $a",
943 [(PTXstoreparam timm:$d, RegI64:$a)]>;
944 def STpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a),
945 "st.param.f32\t[$d], $a",
946 [(PTXstoreparam timm:$d, RegF32:$a)]>;
947 def STpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a),
948 "st.param.f64\t[$d], $a",
949 [(PTXstoreparam timm:$d, RegF64:$a)]>;
953 defm STg : PTX_ST_ALL<"st.global", store_global>;
954 defm STl : PTX_ST_ALL<"st.local", store_local>;
955 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
957 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
958 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
959 // TODO: Do something with st.param if/when it is needed.
961 // Conversion to pred
962 // PTX does not directly support converting to a predicate type, so we fake it
963 // by performing a greater-than test between the value and zero. This follows
964 // the C convention that any non-zero value is equivalent to 'true'.
966 : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
967 [(set RegPred:$d, (trunc RegI16:$a))]>;
970 : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
971 [(set RegPred:$d, (trunc RegI32:$a))]>;
974 : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
975 [(set RegPred:$d, (trunc RegI64:$a))]>;
978 : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
979 [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
982 : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
983 [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
986 // PTX does not directly support converting a predicate to a value, so we
987 // use a select instruction to select either 0 or 1 (integer or fp) based
988 // on the truth value of the predicate.
990 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
991 [(set RegI16:$d, (anyext RegPred:$a))]>;
994 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
995 [(set RegI16:$d, (zext RegPred:$a))]>;
998 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
999 [(set RegI16:$d, (sext RegPred:$a))]>;
1002 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
1003 [(set RegI16:$d, (trunc RegI32:$a))]>;
1006 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a",
1007 [(set RegI16:$d, (trunc RegI64:$a))]>;
1010 : InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a",
1011 [(set RegI16:$d, (fp_to_uint RegF32:$a))]>;
1014 : InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a",
1015 [(set RegI16:$d, (fp_to_uint RegF64:$a))]>;
1017 // Conversion to u32
1020 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
1021 [(set RegI32:$d, (zext RegPred:$a))]>;
1024 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
1025 [(set RegI32:$d, (anyext RegI16:$a))]>;
1028 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
1029 [(set RegI32:$d, (zext RegI16:$a))]>;
1032 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
1033 [(set RegI32:$d, (sext RegPred:$a))]>;
1036 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
1037 [(set RegI32:$d, (sext RegI16:$a))]>;
1040 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
1041 [(set RegI32:$d, (trunc RegI64:$a))]>;
1044 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a",
1045 [(set RegI32:$d, (fp_to_uint RegF32:$a))]>;
1048 : InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a",
1049 [(set RegI32:$d, (fp_to_uint RegF64:$a))]>;
1051 // Conversion to u64
1054 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
1055 [(set RegI64:$d, (zext RegPred:$a))]>;
1058 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
1059 [(set RegI64:$d, (sext RegPred:$a))]>;
1062 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
1063 [(set RegI64:$d, (zext RegI16:$a))]>;
1066 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
1067 [(set RegI64:$d, (sext RegI16:$a))]>;
1070 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
1071 [(set RegI64:$d, (zext RegI32:$a))]>;
1074 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
1075 [(set RegI64:$d, (sext RegI32:$a))]>;
1078 : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a",
1079 [(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
1082 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a",
1083 [(set RegI64:$d, (fp_to_uint RegF64:$a))]>;
1085 // Conversion to f32
1088 : InstPTX<(outs RegF32:$d), (ins RegPred:$a),
1089 "selp.f32\t$d, 0F3F800000, 0F00000000, $a", // 1.0
1090 [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
1093 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
1094 [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
1097 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a",
1098 [(set RegF32:$d, (uint_to_fp RegI32:$a))]>;
1101 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a",
1102 [(set RegF32:$d, (uint_to_fp RegI64:$a))]>;
1105 : InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
1106 [(set RegF32:$d, (fround RegF64:$a))]>;
1108 // Conversion to f64
1111 : InstPTX<(outs RegF64:$d), (ins RegPred:$a),
1112 "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a", // 1.0
1113 [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
1116 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
1117 [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
1120 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a",
1121 [(set RegF64:$d, (uint_to_fp RegI32:$a))]>;
1124 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a",
1125 [(set RegF64:$d, (uint_to_fp RegI64:$a))]>;
1128 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
1129 [(set RegF64:$d, (fextend RegF32:$a))]>;
1131 ///===- Control Flow Instructions -----------------------------------------===//
1133 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1135 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
1138 let isBranch = 1, isTerminator = 1 in {
1139 // FIXME: The pattern part is blank because I cannot (or do not yet know
1140 // how to) use the first operand of PredicateOperand (a RegPred register) here
1142 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
1143 [/*(brcond pred:$_p, bb:$d)*/]>;
1146 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1147 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
1148 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
1151 let hasSideEffects = 1 in {
1152 def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>;
1156 ///===- Spill Instructions ------------------------------------------------===//
1157 // Special instructions used for stack spilling
1158 def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
1159 "mov.u16\ts$d, $a", []>;
1160 def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
1161 "mov.u32\ts$d, $a", []>;
1162 def STACKSTOREI64 : InstPTX<(outs), (ins i32imm:$d, RegI64:$a),
1163 "mov.u64\ts$d, $a", []>;
1164 def STACKSTOREF32 : InstPTX<(outs), (ins i32imm:$d, RegF32:$a),
1165 "mov.f32\ts$d, $a", []>;
1166 def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
1167 "mov.f64\ts$d, $a", []>;
1169 def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
1170 "mov.u16\t$d, s$a", []>;
1171 def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),
1172 "mov.u32\t$d, s$a", []>;
1173 def STACKLOADI64 : InstPTX<(outs), (ins RegI64:$d, i32imm:$a),
1174 "mov.u64\t$d, s$a", []>;
1175 def STACKLOADF32 : InstPTX<(outs), (ins RegF32:$d, i32imm:$a),
1176 "mov.f32\t$d, s$a", []>;
1177 def STACKLOADF64 : InstPTX<(outs), (ins RegF64:$d, i32imm:$a),
1178 "mov.f64\t$d, s$a", []>;
1180 ///===- Parameter Passing Pseudo-Instructions -----------------------------===//
1182 def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b),
1183 "mov.pred\t$a, %param$b", []>;
1184 def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b),
1185 "mov.b16\t$a, %param$b", []>;
1186 def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b),
1187 "mov.b32\t$a, %param$b", []>;
1188 def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b),
1189 "mov.b64\t$a, %param$b", []>;
1190 def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b),
1191 "mov.f32\t$a, %param$b", []>;
1192 def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b),
1193 "mov.f64\t$a, %param$b", []>;
1195 def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>;
1196 def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>;
1197 def WRITEPARAMI32 : InstPTX<(outs), (ins RegI32:$a), "//w", []>;
1198 def WRITEPARAMI64 : InstPTX<(outs), (ins RegI64:$a), "//w", []>;
1199 def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>;
1200 def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>;
1203 // def ADJCALLSTACKUP :
1204 // InstPTX<(outs), (ins i32imm:$amt1, i32imm:$amt2), "",
1205 // [(PTXcallseq_end timm:$amt1, timm:$amt2)]>;
1206 // def ADJCALLSTACKDOWN :
1207 // InstPTX<(outs), (ins i32imm:$amt), "",
1208 // [(PTXcallseq_start timm:$amt)]>;
1210 ///===- Intrinsic Instructions --------------------------------------------===//
1212 include "PTXIntrinsicInstrInfo.td"