1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
28 // Shader Model Support
29 def SupportsSM13 : Predicate<"getSubtarget().supportsSM13()">;
30 def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
31 def SupportsSM20 : Predicate<"getSubtarget().supportsSM20()">;
32 def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
39 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
40 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
43 def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
44 def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
46 //===----------------------------------------------------------------------===//
47 // Instruction Pattern Stuff
48 //===----------------------------------------------------------------------===//
50 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
52 const PointerType *PT;
53 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
54 (PT = dyn_cast<PointerType>(Src->getType())))
55 return PT->getAddressSpace() == PTX::GLOBAL;
59 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
61 const PointerType *PT;
62 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
63 (PT = dyn_cast<PointerType>(Src->getType())))
64 return PT->getAddressSpace() == PTX::CONSTANT;
68 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
70 const PointerType *PT;
71 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
72 (PT = dyn_cast<PointerType>(Src->getType())))
73 return PT->getAddressSpace() == PTX::LOCAL;
77 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
79 const PointerType *PT;
80 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
81 (PT = dyn_cast<PointerType>(Src->getType())))
82 return PT->getAddressSpace() == PTX::PARAMETER;
86 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
88 const PointerType *PT;
89 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
90 (PT = dyn_cast<PointerType>(Src->getType())))
91 return PT->getAddressSpace() == PTX::SHARED;
96 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
98 const PointerType *PT;
99 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
100 (PT = dyn_cast<PointerType>(Src->getType())))
101 return PT->getAddressSpace() == PTX::GLOBAL;
106 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
108 const PointerType *PT;
109 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
110 (PT = dyn_cast<PointerType>(Src->getType())))
111 return PT->getAddressSpace() == PTX::LOCAL;
116 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
118 const PointerType *PT;
119 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
120 (PT = dyn_cast<PointerType>(Src->getType())))
121 return PT->getAddressSpace() == PTX::PARAMETER;
126 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
128 const PointerType *PT;
129 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
130 (PT = dyn_cast<PointerType>(Src->getType())))
131 return PT->getAddressSpace() == PTX::SHARED;
136 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
137 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
138 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
139 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
140 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
141 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
144 def MEMri32 : Operand<i32> {
145 let PrintMethod = "printMemOperand";
146 let MIOperandInfo = (ops RegI32, i32imm);
148 def MEMri64 : Operand<i64> {
149 let PrintMethod = "printMemOperand";
150 let MIOperandInfo = (ops RegI64, i64imm);
152 def MEMii32 : Operand<i32> {
153 let PrintMethod = "printMemOperand";
154 let MIOperandInfo = (ops i32imm, i32imm);
156 def MEMii64 : Operand<i64> {
157 let PrintMethod = "printMemOperand";
158 let MIOperandInfo = (ops i64imm, i64imm);
160 // The operand here does not correspond to an actual address, so we
161 // can use i32 in 64-bit address modes.
162 def MEMpi : Operand<i32> {
163 let PrintMethod = "printParamOperand";
164 let MIOperandInfo = (ops i32imm);
167 // Branch & call targets have OtherVT type.
168 def brtarget : Operand<OtherVT>;
169 def calltarget : Operand<i32>;
171 //===----------------------------------------------------------------------===//
172 // PTX Specific Node Definitions
173 //===----------------------------------------------------------------------===//
175 // PTX allow generic 3-reg shifts like shl r0, r1, r2
176 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
177 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
178 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
181 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
183 : SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
185 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
187 //===----------------------------------------------------------------------===//
188 // Instruction Class Templates
189 //===----------------------------------------------------------------------===//
191 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
192 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
193 def rr32 : InstPTX<(outs RegF32:$d),
195 !strconcat(opcstr, ".f32\t$d, $a"),
196 [(set RegF32:$d, (opnode RegF32:$a))]>;
197 def ri32 : InstPTX<(outs RegF32:$d),
199 !strconcat(opcstr, ".f32\t$d, $a"),
200 [(set RegF32:$d, (opnode fpimm:$a))]>;
201 def rr64 : InstPTX<(outs RegF64:$d),
203 !strconcat(opcstr, ".f64\t$d, $a"),
204 [(set RegF64:$d, (opnode RegF64:$a))]>;
205 def ri64 : InstPTX<(outs RegF64:$d),
207 !strconcat(opcstr, ".f64\t$d, $a"),
208 [(set RegF64:$d, (opnode fpimm:$a))]>;
211 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
212 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
213 def rr32 : InstPTX<(outs RegF32:$d),
214 (ins RegF32:$a, RegF32:$b),
215 !strconcat(opcstr, ".f32\t$d, $a, $b"),
216 [(set RegF32:$d, (opnode RegF32:$a, RegF32:$b))]>;
217 def ri32 : InstPTX<(outs RegF32:$d),
218 (ins RegF32:$a, f32imm:$b),
219 !strconcat(opcstr, ".f32\t$d, $a, $b"),
220 [(set RegF32:$d, (opnode RegF32:$a, fpimm:$b))]>;
221 def rr64 : InstPTX<(outs RegF64:$d),
222 (ins RegF64:$a, RegF64:$b),
223 !strconcat(opcstr, ".f64\t$d, $a, $b"),
224 [(set RegF64:$d, (opnode RegF64:$a, RegF64:$b))]>;
225 def ri64 : InstPTX<(outs RegF64:$d),
226 (ins RegF64:$a, f64imm:$b),
227 !strconcat(opcstr, ".f64\t$d, $a, $b"),
228 [(set RegF64:$d, (opnode RegF64:$a, fpimm:$b))]>;
231 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
232 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
233 def rrr32 : InstPTX<(outs RegF32:$d),
234 (ins RegF32:$a, RegF32:$b, RegF32:$c),
235 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
236 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
239 def rri32 : InstPTX<(outs RegF32:$d),
240 (ins RegF32:$a, RegF32:$b, f32imm:$c),
241 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
242 [(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
245 def rrr64 : InstPTX<(outs RegF64:$d),
246 (ins RegF64:$a, RegF64:$b, RegF64:$c),
247 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
248 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
251 def rri64 : InstPTX<(outs RegF64:$d),
252 (ins RegF64:$a, RegF64:$b, f64imm:$c),
253 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
254 [(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
259 multiclass INT3<string opcstr, SDNode opnode> {
260 def rr16 : InstPTX<(outs RegI16:$d),
261 (ins RegI16:$a, RegI16:$b),
262 !strconcat(opcstr, ".u16\t$d, $a, $b"),
263 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
264 def ri16 : InstPTX<(outs RegI16:$d),
265 (ins RegI16:$a, i16imm:$b),
266 !strconcat(opcstr, ".u16\t$d, $a, $b"),
267 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
268 def rr32 : InstPTX<(outs RegI32:$d),
269 (ins RegI32:$a, RegI32:$b),
270 !strconcat(opcstr, ".u32\t$d, $a, $b"),
271 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
272 def ri32 : InstPTX<(outs RegI32:$d),
273 (ins RegI32:$a, i32imm:$b),
274 !strconcat(opcstr, ".u32\t$d, $a, $b"),
275 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
276 def rr64 : InstPTX<(outs RegI64:$d),
277 (ins RegI64:$a, RegI64:$b),
278 !strconcat(opcstr, ".u64\t$d, $a, $b"),
279 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
280 def ri64 : InstPTX<(outs RegI64:$d),
281 (ins RegI64:$a, i64imm:$b),
282 !strconcat(opcstr, ".u64\t$d, $a, $b"),
283 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
286 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
287 def ripreds : InstPTX<(outs RegPred:$d),
288 (ins RegPred:$a, i1imm:$b),
289 !strconcat(opcstr, ".pred\t$d, $a, $b"),
290 [(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
291 def rrpreds : InstPTX<(outs RegPred:$d),
292 (ins RegPred:$a, RegPred:$b),
293 !strconcat(opcstr, ".pred\t$d, $a, $b"),
294 [(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
295 def rr16 : InstPTX<(outs RegI16:$d),
296 (ins RegI16:$a, RegI16:$b),
297 !strconcat(opcstr, ".b16\t$d, $a, $b"),
298 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
299 def ri16 : InstPTX<(outs RegI16:$d),
300 (ins RegI16:$a, i16imm:$b),
301 !strconcat(opcstr, ".b16\t$d, $a, $b"),
302 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
303 def rr32 : InstPTX<(outs RegI32:$d),
304 (ins RegI32:$a, RegI32:$b),
305 !strconcat(opcstr, ".b32\t$d, $a, $b"),
306 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
307 def ri32 : InstPTX<(outs RegI32:$d),
308 (ins RegI32:$a, i32imm:$b),
309 !strconcat(opcstr, ".b32\t$d, $a, $b"),
310 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
311 def rr64 : InstPTX<(outs RegI64:$d),
312 (ins RegI64:$a, RegI64:$b),
313 !strconcat(opcstr, ".b64\t$d, $a, $b"),
314 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
315 def ri64 : InstPTX<(outs RegI64:$d),
316 (ins RegI64:$a, i64imm:$b),
317 !strconcat(opcstr, ".b64\t$d, $a, $b"),
318 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
321 multiclass INT3ntnc<string opcstr, SDNode opnode> {
322 def rr16 : InstPTX<(outs RegI16:$d),
323 (ins RegI16:$a, RegI16:$b),
324 !strconcat(opcstr, "16\t$d, $a, $b"),
325 [(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
326 def rr32 : InstPTX<(outs RegI32:$d),
327 (ins RegI32:$a, RegI32:$b),
328 !strconcat(opcstr, "32\t$d, $a, $b"),
329 [(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
330 def rr64 : InstPTX<(outs RegI64:$d),
331 (ins RegI64:$a, RegI64:$b),
332 !strconcat(opcstr, "64\t$d, $a, $b"),
333 [(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
334 def ri16 : InstPTX<(outs RegI16:$d),
335 (ins RegI16:$a, i16imm:$b),
336 !strconcat(opcstr, "16\t$d, $a, $b"),
337 [(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
338 def ri32 : InstPTX<(outs RegI32:$d),
339 (ins RegI32:$a, i32imm:$b),
340 !strconcat(opcstr, "32\t$d, $a, $b"),
341 [(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
342 def ri64 : InstPTX<(outs RegI64:$d),
343 (ins RegI64:$a, i64imm:$b),
344 !strconcat(opcstr, "64\t$d, $a, $b"),
345 [(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
346 def ir16 : InstPTX<(outs RegI16:$d),
347 (ins i16imm:$a, RegI16:$b),
348 !strconcat(opcstr, "16\t$d, $a, $b"),
349 [(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
350 def ir32 : InstPTX<(outs RegI32:$d),
351 (ins i32imm:$a, RegI32:$b),
352 !strconcat(opcstr, "32\t$d, $a, $b"),
353 [(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
354 def ir64 : InstPTX<(outs RegI64:$d),
355 (ins i64imm:$a, RegI64:$b),
356 !strconcat(opcstr, "64\t$d, $a, $b"),
357 [(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
360 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
361 CondCode cmp, string cmpstr> {
362 // TODO support 5-operand format: p|q, a, b, c
365 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
366 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
367 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
369 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
370 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
371 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
374 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
375 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
376 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
378 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
379 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
380 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
382 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
383 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
384 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
386 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
387 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
388 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
390 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
391 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
392 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
394 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
395 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
396 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
399 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
400 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
401 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
403 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
404 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
405 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
407 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
408 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
409 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
411 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
412 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
413 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
415 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
416 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
417 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
419 : InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
420 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
421 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
424 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
425 CondCode ucmp, CondCode ocmp, string cmpstr> {
426 // TODO support 5-operand format: p|q, a, b, c
429 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
430 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
431 [(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
433 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
434 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
435 [(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
438 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
439 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
440 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
442 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
443 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
444 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
447 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
448 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
449 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
451 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
452 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
453 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
456 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
457 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
458 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
460 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
461 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
462 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
465 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
466 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
467 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
469 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
470 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
471 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
474 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
475 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
476 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
478 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
479 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
480 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
483 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
484 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
485 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
487 : InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
488 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
489 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
492 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
494 : InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
495 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
496 [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
499 multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
500 def rr32 : InstPTX<(outs RC:$d),
502 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
503 [(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
504 def rr64 : InstPTX<(outs RC:$d),
506 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
507 [(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
508 def ri32 : InstPTX<(outs RC:$d),
510 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
511 [(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
512 def ri64 : InstPTX<(outs RC:$d),
514 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
515 [(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
516 def ii32 : InstPTX<(outs RC:$d),
518 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
519 [(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
520 def ii64 : InstPTX<(outs RC:$d),
522 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
523 [(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
526 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
527 defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
528 defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
529 defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
530 defm f32 : PTX_LD<opstr, ".f32", RegF32, pat_load>;
531 defm f64 : PTX_LD<opstr, ".f64", RegF64, pat_load>;
534 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
535 def rr32 : InstPTX<(outs),
536 (ins RC:$d, MEMri32:$a),
537 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
538 [(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
539 def rr64 : InstPTX<(outs),
540 (ins RC:$d, MEMri64:$a),
541 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
542 [(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
543 def ri32 : InstPTX<(outs),
544 (ins RC:$d, MEMri32:$a),
545 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
546 [(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
547 def ri64 : InstPTX<(outs),
548 (ins RC:$d, MEMri64:$a),
549 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
550 [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
551 def ii32 : InstPTX<(outs),
552 (ins RC:$d, MEMii32:$a),
553 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
554 [(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
555 def ii64 : InstPTX<(outs),
556 (ins RC:$d, MEMii64:$a),
557 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
558 [(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
561 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
562 defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
563 defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
564 defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
565 defm f32 : PTX_ST<opstr, ".f32", RegF32, pat_store>;
566 defm f64 : PTX_ST<opstr, ".f64", RegF64, pat_store>;
569 //===----------------------------------------------------------------------===//
571 //===----------------------------------------------------------------------===//
573 ///===- Integer Arithmetic Instructions -----------------------------------===//
575 defm ADD : INT3<"add", add>;
576 defm SUB : INT3<"sub", sub>;
577 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
578 defm DIV : INT3<"div", udiv>;
579 defm REM : INT3<"rem", urem>;
581 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
583 // Standard Unary Operations
584 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
586 // Standard Binary Operations
587 defm FADD : PTX_FLOAT_3OP<"add.rn", fadd>;
588 defm FSUB : PTX_FLOAT_3OP<"sub.rn", fsub>;
589 defm FMUL : PTX_FLOAT_3OP<"mul.rn", fmul>;
591 // For floating-point division:
592 // SM_13+ defaults to .rn for f32 and f64,
593 // SM10 must *not* provide a rounding
596 // - Allow user selection of rounding modes for fdiv
597 // - Add support for -prec-div=false (.approx)
599 def FDIVrr32SM13 : InstPTX<(outs RegF32:$d),
600 (ins RegF32:$a, RegF32:$b),
601 "div.rn.f32\t$d, $a, $b",
602 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
603 Requires<[SupportsSM13]>;
604 def FDIVri32SM13 : InstPTX<(outs RegF32:$d),
605 (ins RegF32:$a, f32imm:$b),
606 "div.rn.f32\t$d, $a, $b",
607 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
608 Requires<[SupportsSM13]>;
609 def FDIVrr32SM10 : InstPTX<(outs RegF32:$d),
610 (ins RegF32:$a, RegF32:$b),
611 "div.f32\t$d, $a, $b",
612 [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
613 Requires<[DoesNotSupportSM13]>;
614 def FDIVri32SM10 : InstPTX<(outs RegF32:$d),
615 (ins RegF32:$a, f32imm:$b),
616 "div.f32\t$d, $a, $b",
617 [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
618 Requires<[DoesNotSupportSM13]>;
620 def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
621 (ins RegF64:$a, RegF64:$b),
622 "div.rn.f64\t$d, $a, $b",
623 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
624 Requires<[SupportsSM13]>;
625 def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
626 (ins RegF64:$a, f64imm:$b),
627 "div.rn.f64\t$d, $a, $b",
628 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
629 Requires<[SupportsSM13]>;
630 def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
631 (ins RegF64:$a, RegF64:$b),
632 "div.f64\t$d, $a, $b",
633 [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
634 Requires<[DoesNotSupportSM13]>;
635 def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
636 (ins RegF64:$a, f64imm:$b),
637 "div.f64\t$d, $a, $b",
638 [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
639 Requires<[DoesNotSupportSM13]>;
643 // Multi-operation hybrid instructions
645 // The selection of mad/fma is tricky. In some cases, they are the *same*
646 // instruction, but in other cases we may prefer one or the other. Also,
647 // different PTX versions differ on whether rounding mode flags are required.
648 // In the short term, mad is supported on all PTX versions and we use a
649 // default rounding mode no matter what shader model or PTX version.
650 // TODO: Allow the rounding mode to be selectable through llc.
651 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13, SupportsFMA]>;
652 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13, SupportsFMA]>;
654 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
656 def FSQRT32 : InstPTX<(outs RegF32:$d),
658 "sqrt.rn.f32\t$d, $a",
659 [(set RegF32:$d, (fsqrt RegF32:$a))]>;
661 def FSQRT64 : InstPTX<(outs RegF64:$d),
663 "sqrt.rn.f64\t$d, $a",
664 [(set RegF64:$d, (fsqrt RegF64:$a))]>;
666 def FSIN32 : InstPTX<(outs RegF32:$d),
668 "sin.approx.f32\t$d, $a",
669 [(set RegF32:$d, (fsin RegF32:$a))]>;
671 def FSIN64 : InstPTX<(outs RegF64:$d),
673 "sin.approx.f64\t$d, $a",
674 [(set RegF64:$d, (fsin RegF64:$a))]>;
676 def FCOS32 : InstPTX<(outs RegF32:$d),
678 "cos.approx.f32\t$d, $a",
679 [(set RegF32:$d, (fcos RegF32:$a))]>;
681 def FCOS64 : InstPTX<(outs RegF64:$d),
683 "cos.approx.f64\t$d, $a",
684 [(set RegF64:$d, (fcos RegF64:$a))]>;
687 ///===- Comparison and Selection Instructions -----------------------------===//
693 defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
694 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
695 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
696 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
697 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
698 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
702 defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
703 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
704 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
705 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
706 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
707 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
711 defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
712 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
713 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
714 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
715 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
716 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
720 defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", SETUEQ, SETOEQ, "eq">;
721 defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", SETUNE, SETONE, "ne">;
722 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
723 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", SETULE, SETOLE, "le">;
724 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", SETUGT, SETOGT, "gt">;
725 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", SETUGE, SETOGE, "ge">;
729 defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", SETUEQ, SETOEQ, "eq">;
730 defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", SETUNE, SETONE, "ne">;
731 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
732 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", SETULE, SETOLE, "le">;
733 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", SETUGT, SETOGT, "gt">;
734 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", SETUGE, SETOGE, "ge">;
738 defm PTX_SELPu16 : PTX_SELP<RegI16, "u16">;
739 defm PTX_SELPu32 : PTX_SELP<RegI32, "u32">;
740 defm PTX_SELPu64 : PTX_SELP<RegI64, "u64">;
741 defm PTX_SELPf32 : PTX_SELP<RegF32, "f32">;
742 defm PTX_SELPf64 : PTX_SELP<RegF64, "f64">;
744 ///===- Logic and Shift Instructions --------------------------------------===//
746 defm SHL : INT3ntnc<"shl.b", PTXshl>;
747 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
748 defm SRA : INT3ntnc<"shr.s", PTXsra>;
750 defm AND : PTX_LOGIC<"and", and>;
751 defm OR : PTX_LOGIC<"or", or>;
752 defm XOR : PTX_LOGIC<"xor", xor>;
754 ///===- Data Movement and Conversion Instructions -------------------------===//
756 let neverHasSideEffects = 1 in {
758 : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
760 : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
762 : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
764 : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
766 : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
768 : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
771 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
773 : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
774 [(set RegPred:$d, imm:$a)]>;
776 : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
777 [(set RegI16:$d, imm:$a)]>;
779 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
780 [(set RegI32:$d, imm:$a)]>;
782 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
783 [(set RegI64:$d, imm:$a)]>;
785 : InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
786 [(set RegF32:$d, fpimm:$a)]>;
788 : InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
789 [(set RegF64:$d, fpimm:$a)]>;
792 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
794 : InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
795 [(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
797 : InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
798 [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
802 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
803 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
804 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
805 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
807 // This is a special instruction that is manually inserted for kernel parameters
808 def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
809 "ld.param.u16\t$d, [$a]", []>;
810 def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
811 "ld.param.u32\t$d, [$a]", []>;
812 def LDpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
813 "ld.param.u64\t$d, [$a]", []>;
814 def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
815 "ld.param.f32\t$d, [$a]", []>;
816 def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
817 "ld.param.f64\t$d, [$a]", []>;
820 defm STg : PTX_ST_ALL<"st.global", store_global>;
821 defm STl : PTX_ST_ALL<"st.local", store_local>;
822 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
824 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
825 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
826 // TODO: Do something with st.param if/when it is needed.
828 // Conversion to pred
831 : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "cvt.pred.u16\t$d, $a",
832 [(set RegPred:$d, (trunc RegI16:$a))]>;
835 : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "cvt.pred.u32\t$d, $a",
836 [(set RegPred:$d, (trunc RegI32:$a))]>;
839 : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "cvt.pred.u64\t$d, $a",
840 [(set RegPred:$d, (trunc RegI64:$a))]>;
843 : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "cvt.rzi.pred.f32\t$d, $a",
844 [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
847 : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "cvt.rzi.pred.f64\t$d, $a",
848 [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
853 : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "cvt.u16.pred\t$d, $a",
854 [(set RegI16:$d, (zext RegPred:$a))]>;
857 : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
858 [(set RegI16:$d, (trunc RegI32:$a))]>;
861 : InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a",
862 [(set RegI16:$d, (trunc RegI64:$a))]>;
865 : InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a",
866 [(set RegI16:$d, (fp_to_uint RegF32:$a))]>;
869 : InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a",
870 [(set RegI16:$d, (fp_to_uint RegF64:$a))]>;
875 : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "cvt.u32.pred\t$d, $a",
876 [(set RegI32:$d, (zext RegPred:$a))]>;
879 : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
880 [(set RegI32:$d, (zext RegI16:$a))]>;
883 : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
884 [(set RegI32:$d, (trunc RegI64:$a))]>;
887 : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a",
888 [(set RegI32:$d, (fp_to_uint RegF32:$a))]>;
891 : InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a",
892 [(set RegI32:$d, (fp_to_uint RegF64:$a))]>;
897 : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "cvt.u64.pred\t$d, $a",
898 [(set RegI64:$d, (zext RegPred:$a))]>;
901 : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
902 [(set RegI64:$d, (zext RegI16:$a))]>;
905 : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
906 [(set RegI64:$d, (zext RegI32:$a))]>;
909 : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a",
910 [(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
913 : InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a",
914 [(set RegI64:$d, (fp_to_uint RegF64:$a))]>;
919 : InstPTX<(outs RegF32:$d), (ins RegPred:$a), "cvt.rn.f32.pred\t$d, $a",
920 [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
923 : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
924 [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
927 : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a",
928 [(set RegF32:$d, (uint_to_fp RegI32:$a))]>;
931 : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a",
932 [(set RegF32:$d, (uint_to_fp RegI64:$a))]>;
935 : InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
936 [(set RegF32:$d, (fround RegF64:$a))]>;
941 : InstPTX<(outs RegF64:$d), (ins RegPred:$a), "cvt.rn.f64.pred\t$d, $a",
942 [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
945 : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
946 [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
949 : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a",
950 [(set RegF64:$d, (uint_to_fp RegI32:$a))]>;
953 : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a",
954 [(set RegF64:$d, (uint_to_fp RegI64:$a))]>;
957 : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
958 [(set RegF64:$d, (fextend RegF32:$a))]>;
960 ///===- Control Flow Instructions -----------------------------------------===//
962 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
964 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
967 let isBranch = 1, isTerminator = 1 in {
968 // FIXME: The pattern part is blank because I cannot (or do not yet know
969 // how to) use the first operand of PredicateOperand (a RegPred register) here
971 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
972 [/*(brcond pred:$_p, bb:$d)*/]>;
975 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
976 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
977 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
980 ///===- Spill Instructions ------------------------------------------------===//
981 // Special instructions used for stack spilling
982 def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
983 "mov.u16\ts$d, $a", []>;
984 def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
985 "mov.u32\ts$d, $a", []>;
986 def STACKSTOREI64 : InstPTX<(outs), (ins i32imm:$d, RegI64:$a),
987 "mov.u64\ts$d, $a", []>;
988 def STACKSTOREF32 : InstPTX<(outs), (ins i32imm:$d, RegF32:$a),
989 "mov.f32\ts$d, $a", []>;
990 def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
991 "mov.f64\ts$d, $a", []>;
993 def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
994 "mov.u16\t$d, s$a", []>;
995 def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),
996 "mov.u32\t$d, s$a", []>;
997 def STACKLOADI64 : InstPTX<(outs), (ins RegI64:$d, i32imm:$a),
998 "mov.u64\t$d, s$a", []>;
999 def STACKLOADF32 : InstPTX<(outs), (ins RegF32:$d, i32imm:$a),
1000 "mov.f32\t$d, s$a", []>;
1001 def STACKLOADF64 : InstPTX<(outs), (ins RegF64:$d, i32imm:$a),
1002 "mov.f64\t$d, s$a", []>;
1004 ///===- Intrinsic Instructions --------------------------------------------===//
1006 include "PTXIntrinsicInstrInfo.td"