1 //===-- PTXTargetMachine.cpp - Define TargetMachine for PTX ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PTX target.
12 //===----------------------------------------------------------------------===//
15 #include "PTXTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Analysis/Passes.h"
18 #include "llvm/Analysis/Verifier.h"
19 #include "llvm/Assembly/PrintModulePass.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
39 #include "llvm/Transforms/Scalar.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/TargetRegistry.h"
47 MCStreamer *createPTXAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
48 bool isVerboseAsm, bool useLoc,
50 MCInstPrinter *InstPrint,
56 extern "C" void LLVMInitializePTXTarget() {
58 RegisterTargetMachine<PTX32TargetMachine> X(ThePTX32Target);
59 RegisterTargetMachine<PTX64TargetMachine> Y(ThePTX64Target);
61 TargetRegistry::RegisterAsmStreamer(ThePTX32Target, createPTXAsmStreamer);
62 TargetRegistry::RegisterAsmStreamer(ThePTX64Target, createPTXAsmStreamer);
66 const char* DataLayout32 =
67 "e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
68 const char* DataLayout64 =
69 "e-p:64:64-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
71 // Copied from LLVMTargetMachine.cpp
72 void printNoVerify(PassManagerBase &PM, const char *Banner) {
74 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
77 void printAndVerify(PassManagerBase &PM,
80 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
82 //if (VerifyMachineCode)
83 // PM.add(createMachineVerifierPass(Banner));
87 // DataLayout and FrameLowering are filled with dummy data
88 PTXTargetMachine::PTXTargetMachine(const Target &T,
89 StringRef TT, StringRef CPU, StringRef FS,
90 Reloc::Model RM, CodeModel::Model CM,
92 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
93 DataLayout(is64Bit ? DataLayout64 : DataLayout32),
94 Subtarget(TT, CPU, FS, is64Bit),
95 FrameLowering(Subtarget),
100 PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
101 StringRef CPU, StringRef FS,
102 Reloc::Model RM, CodeModel::Model CM)
103 : PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) {
106 PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
107 StringRef CPU, StringRef FS,
108 Reloc::Model RM, CodeModel::Model CM)
109 : PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) {
112 bool PTXTargetMachine::addInstSelector(PassManagerBase &PM,
113 CodeGenOpt::Level OptLevel) {
114 PM.add(createPTXISelDag(*this, OptLevel));
118 bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM,
119 CodeGenOpt::Level OptLevel) {
120 // PTXMFInfoExtract must after register allocation!
121 PM.add(createPTXMFInfoExtract(*this, OptLevel));
125 bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
126 formatted_raw_ostream &Out,
127 CodeGenFileType FileType,
128 CodeGenOpt::Level OptLevel,
129 bool DisableVerify) {
130 // This is mostly based on LLVMTargetMachine::addPassesToEmitFile
132 // Add common CodeGen passes.
133 MCContext *Context = 0;
134 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
136 assert(Context != 0 && "Failed to get MCContext");
138 if (hasMCSaveTempLabels())
139 Context->setAllowTemporaryLabels(false);
141 const MCAsmInfo &MAI = *getMCAsmInfo();
142 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
143 OwningPtr<MCStreamer> AsmStreamer;
146 default: return true;
147 case CGFT_AssemblyFile: {
148 MCInstPrinter *InstPrinter =
149 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
151 // Create a code emitter if asked to show the encoding.
152 MCCodeEmitter *MCE = 0;
153 MCAsmBackend *MAB = 0;
155 MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
156 true, /* verbose asm */
161 false /* show MC encoding */);
162 AsmStreamer.reset(S);
165 case CGFT_ObjectFile: {
166 llvm_unreachable("Object file emission is not supported with PTX");
169 // The Null output is intended for use for performance analysis and testing,
171 AsmStreamer.reset(createNullStreamer(*Context));
176 //AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
178 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
179 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
183 // If successful, createAsmPrinter took ownership of AsmStreamer.
188 PM.add(createGCInfoDeleter());
192 bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
193 CodeGenOpt::Level OptLevel,
195 MCContext *&OutContext) {
196 // Add standard LLVM codegen passes.
197 // This is derived from LLVMTargetMachine::addCommonCodeGenPasses, with some
198 // modifications for the PTX target.
200 // Standard LLVM-Level Passes.
202 // Basic AliasAnalysis support.
203 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
204 // BasicAliasAnalysis wins if they disagree. This is intended to help
205 // support "obvious" type-punning idioms.
206 PM.add(createTypeBasedAliasAnalysisPass());
207 PM.add(createBasicAliasAnalysisPass());
209 // Before running any passes, run the verifier to determine if the input
210 // coming from the front-end and/or optimizer is valid.
212 PM.add(createVerifierPass());
214 // Run loop strength reduction before anything else.
215 if (OptLevel != CodeGenOpt::None) {
216 PM.add(createLoopStrengthReducePass(getTargetLowering()));
217 //PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
220 PM.add(createGCLoweringPass());
222 // Make sure that no unreachable blocks are instruction selected.
223 PM.add(createUnreachableBlockEliminationPass());
225 PM.add(createLowerInvokePass(getTargetLowering()));
226 // The lower invoke pass may create unreachable code. Remove it.
227 PM.add(createUnreachableBlockEliminationPass());
229 if (OptLevel != CodeGenOpt::None)
230 PM.add(createCodeGenPreparePass(getTargetLowering()));
232 PM.add(createStackProtectorPass(getTargetLowering()));
234 addPreISel(PM, OptLevel);
236 //PM.add(createPrintFunctionPass("\n\n"
237 // "*** Final LLVM Code input to ISel ***\n",
240 // All passes which modify the LLVM IR are now complete; run the verifier
241 // to ensure that the IR is valid.
243 PM.add(createVerifierPass());
245 // Standard Lower-Level Passes.
247 // Install a MachineModuleInfo class, which is an immutable pass that holds
248 // all the per-module stuff we're generating, including MCContext.
249 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
251 &getTargetLowering()->getObjFileLowering());
253 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
255 // Set up a MachineFunction for the rest of CodeGen to work on.
256 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
258 // Ask the target for an isel.
259 if (addInstSelector(PM, OptLevel))
262 // Print the instruction selected machine code...
263 printAndVerify(PM, "After Instruction Selection");
265 // Expand pseudo-instructions emitted by ISel.
266 PM.add(createExpandISelPseudosPass());
268 // Pre-ra tail duplication.
269 if (OptLevel != CodeGenOpt::None) {
270 PM.add(createTailDuplicatePass(true));
271 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
274 // Optimize PHIs before DCE: removing dead PHI cycles may make more
275 // instructions dead.
276 if (OptLevel != CodeGenOpt::None)
277 PM.add(createOptimizePHIsPass());
279 // If the target requests it, assign local variables to stack slots relative
280 // to one another and simplify frame index references where possible.
281 PM.add(createLocalStackSlotAllocationPass());
283 if (OptLevel != CodeGenOpt::None) {
284 // With optimization, dead code should already be eliminated. However
285 // there is one known exception: lowered code for arguments that are only
286 // used by tail calls, where the tail calls reuse the incoming stack
287 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
288 PM.add(createDeadMachineInstructionElimPass());
289 printAndVerify(PM, "After codegen DCE pass");
291 PM.add(createMachineLICMPass());
292 PM.add(createMachineCSEPass());
293 PM.add(createMachineSinkingPass());
294 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
296 PM.add(createPeepholeOptimizerPass());
297 printAndVerify(PM, "After codegen peephole optimization pass");
300 // Run pre-ra passes.
301 if (addPreRegAlloc(PM, OptLevel))
302 printAndVerify(PM, "After PreRegAlloc passes");
304 // Perform register allocation.
305 PM.add(createPTXRegisterAllocator());
306 printAndVerify(PM, "After Register Allocation");
308 // Perform stack slot coloring and post-ra machine LICM.
309 if (OptLevel != CodeGenOpt::None) {
310 // FIXME: Re-enable coloring with register when it's capable of adding
312 PM.add(createStackSlotColoringPass(false));
314 // FIXME: Post-RA LICM has asserts that fire on virtual registers.
315 // Run post-ra machine LICM to hoist reloads / remats.
316 //if (!DisablePostRAMachineLICM)
317 // PM.add(createMachineLICMPass(false));
319 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
322 // Run post-ra passes.
323 if (addPostRegAlloc(PM, OptLevel))
324 printAndVerify(PM, "After PostRegAlloc passes");
326 PM.add(createLowerSubregsPass());
327 printAndVerify(PM, "After LowerSubregs");
329 // Insert prolog/epilog code. Eliminate abstract frame index references...
330 PM.add(createPrologEpilogCodeInserter());
331 printAndVerify(PM, "After PrologEpilogCodeInserter");
333 // Run pre-sched2 passes.
334 if (addPreSched2(PM, OptLevel))
335 printAndVerify(PM, "After PreSched2 passes");
337 // Second pass scheduler.
338 if (OptLevel != CodeGenOpt::None) {
339 PM.add(createPostRAScheduler(OptLevel));
340 printAndVerify(PM, "After PostRAScheduler");
343 // Branch folding must be run after regalloc and prolog/epilog insertion.
344 if (OptLevel != CodeGenOpt::None) {
345 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
346 printNoVerify(PM, "After BranchFolding");
350 if (OptLevel != CodeGenOpt::None) {
351 PM.add(createTailDuplicatePass(false));
352 printNoVerify(PM, "After TailDuplicate");
355 PM.add(createGCMachineCodeAnalysisPass());
358 // PM.add(createGCInfoPrinter(dbgs()));
360 if (OptLevel != CodeGenOpt::None) {
361 PM.add(createCodePlacementOptPass());
362 printNoVerify(PM, "After CodePlacementOpt");
365 if (addPreEmitPass(PM, OptLevel))
366 printNoVerify(PM, "After PreEmit passes");