2 ##===- generate-register-td.py --------------------------------*-python-*--===##
4 ## The LLVM Compiler Infrastructure
6 ## This file is distributed under the University of Illinois Open Source
7 ## License. See LICENSE.TXT for details.
9 ##===----------------------------------------------------------------------===##
11 ## This file describes the PTX register file generator.
13 ##===----------------------------------------------------------------------===##
15 from sys import argv, exit, stdout
19 print('Usage: generate-register-td.py <num_preds> <num_8> <num_16> <num_32> <num_64>')
23 num_pred = int(argv[1])
24 num_8bit = int(argv[2])
25 num_16bit = int(argv[3])
26 num_32bit = int(argv[4])
27 num_64bit = int(argv[5])
29 print('ERROR: Invalid integer parameter')
32 ## Print the register definition file
33 td_file = open('PTXRegisterInfo.td', 'w')
36 //===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
38 // The LLVM Compiler Infrastructure
40 // This file is distributed under the University of Illinois Open Source
41 // License. See LICENSE.TXT for details.
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
46 // Declarations that describe the PTX register file
47 //===----------------------------------------------------------------------===//
49 class PTXReg<string n> : Register<n> {
50 let Namespace = "PTX";
53 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
59 # Print predicate registers
60 td_file.write('\n///===- Predicate Registers -----------------------------------------------===//\n\n')
61 for r in range(0, num_pred):
62 td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
64 # Print 8-bit registers
65 td_file.write('\n///===- 8-Bit Registers --------------------------------------------------===//\n\n')
66 for r in range(0, num_8bit):
67 td_file.write('def RQ%d : PTXReg<"rq%d">;\n' % (r, r))
69 # Print 16-bit registers
70 td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
71 for r in range(0, num_16bit):
72 td_file.write('def RH%d : PTXReg<"rh%d">;\n' % (r, r))
74 # Print 32-bit registers
75 td_file.write('\n///===- 32-Bit Registers --------------------------------------------------===//\n\n')
76 for r in range(0, num_32bit):
77 td_file.write('def R%d : PTXReg<"r%d">;\n' % (r, r))
79 # Print 64-bit registers
80 td_file.write('\n///===- 64-Bit Registers --------------------------------------------------===//\n\n')
81 for r in range(0, num_64bit):
82 td_file.write('def RD%d : PTXReg<"rd%d">;\n' % (r, r))
86 //===----------------------------------------------------------------------===//
88 //===----------------------------------------------------------------------===//
92 # Print register classes
94 td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
95 td_file.write('def RegI8 : RegisterClass<"PTX", [i8], 8, (sequence "RQ%%u", 0, %d)>;\n' % (num_8bit-1))
96 td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
97 td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
98 td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
99 td_file.write('def RegF32 : RegisterClass<"PTX", [f32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
100 td_file.write('def RegF64 : RegisterClass<"PTX", [f64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
105 ## Now write the PTXCallingConv.td file
106 td_file = open('PTXCallingConv.td', 'w')
108 # Reserve 10% of the available registers for return values, and the other 90%
110 num_ret_pred = int(0.1 * num_pred)
111 num_ret_8bit = int(0.1 * num_8bit)
112 num_ret_16bit = int(0.1 * num_16bit)
113 num_ret_32bit = int(0.1 * num_32bit)
114 num_ret_64bit = int(0.1 * num_64bit)
115 num_param_pred = num_pred - num_ret_pred
116 num_param_8bit = num_8bit - num_ret_8bit
117 num_param_16bit = num_16bit - num_ret_16bit
118 num_param_32bit = num_32bit - num_ret_32bit
119 num_param_64bit = num_64bit - num_ret_64bit
121 param_regs_pred = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
122 ret_regs_pred = ['P%d' % i for i in range(0, num_ret_pred)]
123 param_regs_8bit = [('RQ%d' % (i+num_ret_8bit)) for i in range(0, num_param_8bit)]
124 ret_regs_8bit = ['RQ%d' % i for i in range(0, num_ret_8bit)]
125 param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
126 ret_regs_16bit = ['RH%d' % i for i in range(0, num_ret_16bit)]
127 param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
128 ret_regs_32bit = ['R%d' % i for i in range(0, num_ret_32bit)]
129 param_regs_64bit = [('RD%d' % (i+num_ret_64bit)) for i in range(0, num_param_64bit)]
130 ret_regs_64bit = ['RD%d' % i for i in range(0, num_ret_64bit)]
132 param_list_pred = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
133 ret_list_pred = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
134 param_list_8bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_8bit)
135 ret_list_8bit = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_8bit)
136 param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
137 ret_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
138 param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
139 ret_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_32bit)
140 param_list_64bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_64bit)
141 ret_list_64bit = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_64bit)
144 //===--- PTXCallingConv.td - Calling Conventions -----------*- tablegen -*-===//
146 // The LLVM Compiler Infrastructure
148 // This file is distributed under the University of Illinois Open Source
149 // License. See LICENSE.TXT for details.
151 //===----------------------------------------------------------------------===//
153 // This describes the calling conventions for the PTX architecture.
155 //===----------------------------------------------------------------------===//
157 // PTX Formal Parameter Calling Convention
158 def CC_PTX : CallingConv<[
159 CCIfType<[i1], CCAssignToReg<[%s]>>,
160 CCIfType<[i8], CCAssignToReg<[%s]>>,
161 CCIfType<[i16], CCAssignToReg<[%s]>>,
162 CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
163 CCIfType<[i64,f64], CCAssignToReg<[%s]>>
166 // PTX Return Value Calling Convention
167 def RetCC_PTX : CallingConv<[
168 CCIfType<[i1], CCAssignToReg<[%s]>>,
169 CCIfType<[i8], CCAssignToReg<[%s]>>,
170 CCIfType<[i16], CCAssignToReg<[%s]>>,
171 CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
172 CCIfType<[i64,f64], CCAssignToReg<[%s]>>
174 ''' % (param_list_pred, param_list_8bit, param_list_16bit, param_list_32bit, param_list_64bit,
175 ret_list_pred, ret_list_8bit, ret_list_16bit, ret_list_32bit, ret_list_64bit))