1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
37 static unsigned RRegs[32] = {
38 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
39 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
40 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
41 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
42 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
43 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
44 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
45 PPC::R28, PPC::R29, PPC::R30, PPC::R31
47 static unsigned RRegsNoR0[32] = {
49 PPC::R1, PPC::R2, PPC::R3,
50 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
51 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
52 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
53 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
54 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
55 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
56 PPC::R28, PPC::R29, PPC::R30, PPC::R31
58 static unsigned XRegs[32] = {
59 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
60 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
61 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
62 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
63 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
64 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
65 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
66 PPC::X28, PPC::X29, PPC::X30, PPC::X31
68 static unsigned XRegsNoX0[32] = {
70 PPC::X1, PPC::X2, PPC::X3,
71 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
72 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
73 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
74 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
75 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
76 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
77 PPC::X28, PPC::X29, PPC::X30, PPC::X31
79 static unsigned FRegs[32] = {
80 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
81 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
82 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
83 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
84 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
85 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
86 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
87 PPC::F28, PPC::F29, PPC::F30, PPC::F31
89 static unsigned VRegs[32] = {
90 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
91 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
92 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
93 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
94 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
95 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
96 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
97 PPC::V28, PPC::V29, PPC::V30, PPC::V31
99 static unsigned VSRegs[64] = {
100 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
101 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
102 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
103 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
104 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
105 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
106 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
107 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
109 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
110 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
111 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
112 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
113 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
114 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
115 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
116 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
118 static unsigned VSFRegs[64] = {
119 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
120 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
121 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
122 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
123 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
124 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
125 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
126 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
128 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
129 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
130 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
131 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
132 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
133 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
134 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
135 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
137 static unsigned CRBITRegs[32] = {
138 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
139 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
140 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
141 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
142 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
143 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
144 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
145 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
147 static unsigned CRRegs[8] = {
148 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
149 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
152 // Evaluate an expression containing condition register
153 // or condition register field symbols. Returns positive
154 // value on success, or -1 on error.
156 EvaluateCRExpr(const MCExpr *E) {
157 switch (E->getKind()) {
161 case MCExpr::Constant: {
162 int64_t Res = cast<MCConstantExpr>(E)->getValue();
163 return Res < 0 ? -1 : Res;
166 case MCExpr::SymbolRef: {
167 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
168 StringRef Name = SRE->getSymbol().getName();
170 if (Name == "lt") return 0;
171 if (Name == "gt") return 1;
172 if (Name == "eq") return 2;
173 if (Name == "so") return 3;
174 if (Name == "un") return 3;
176 if (Name == "cr0") return 0;
177 if (Name == "cr1") return 1;
178 if (Name == "cr2") return 2;
179 if (Name == "cr3") return 3;
180 if (Name == "cr4") return 4;
181 if (Name == "cr5") return 5;
182 if (Name == "cr6") return 6;
183 if (Name == "cr7") return 7;
191 case MCExpr::Binary: {
192 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
193 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
194 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
197 if (LHSVal < 0 || RHSVal < 0)
200 switch (BE->getOpcode()) {
202 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
203 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
206 return Res < 0 ? -1 : Res;
210 llvm_unreachable("Invalid expression kind!");
215 class PPCAsmParser : public MCTargetAsmParser {
216 MCSubtargetInfo &STI;
217 const MCInstrInfo &MII;
221 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
222 bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
224 bool isPPC64() const { return IsPPC64; }
225 bool isDarwin() const { return IsDarwin; }
227 bool MatchRegisterName(const AsmToken &Tok,
228 unsigned &RegNo, int64_t &IntVal);
230 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
232 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
233 PPCMCExpr::VariantKind &Variant);
234 const MCExpr *FixupVariantKind(const MCExpr *E);
235 bool ParseExpression(const MCExpr *&EVal);
236 bool ParseDarwinExpression(const MCExpr *&EVal);
238 bool ParseOperand(OperandVector &Operands);
240 bool ParseDirectiveWord(unsigned Size, SMLoc L);
241 bool ParseDirectiveTC(unsigned Size, SMLoc L);
242 bool ParseDirectiveMachine(SMLoc L);
243 bool ParseDarwinDirectiveMachine(SMLoc L);
244 bool ParseDirectiveAbiVersion(SMLoc L);
245 bool ParseDirectiveLocalEntry(SMLoc L);
247 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
248 OperandVector &Operands, MCStreamer &Out,
250 bool MatchingInlineAsm) override;
252 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
254 /// @name Auto-generated Match Functions
257 #define GET_ASSEMBLER_HEADER
258 #include "PPCGenAsmMatcher.inc"
264 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
265 const MCInstrInfo &_MII, const MCTargetOptions &Options)
266 : MCTargetAsmParser(), STI(_STI), MII(_MII) {
267 // Check for 64-bit vs. 32-bit pointer mode.
268 Triple TheTriple(STI.getTargetTriple());
269 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
270 TheTriple.getArch() == Triple::ppc64le);
271 IsDarwin = TheTriple.isMacOSX();
272 // Initialize the set of available features.
273 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
276 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
277 SMLoc NameLoc, OperandVector &Operands) override;
279 bool ParseDirective(AsmToken DirectiveID) override;
281 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
282 unsigned Kind) override;
284 const MCExpr *applyModifierToExpr(const MCExpr *E,
285 MCSymbolRefExpr::VariantKind,
286 MCContext &Ctx) override;
289 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
291 struct PPCOperand : public MCParsedAsmOperand {
300 SMLoc StartLoc, EndLoc;
314 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
318 const MCSymbolRefExpr *Sym;
325 struct TLSRegOp TLSReg;
328 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
330 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
332 StartLoc = o.StartLoc;
340 case ContextImmediate:
352 /// getStartLoc - Get the location of the first token of this operand.
353 SMLoc getStartLoc() const override { return StartLoc; }
355 /// getEndLoc - Get the location of the last token of this operand.
356 SMLoc getEndLoc() const override { return EndLoc; }
358 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
359 bool isPPC64() const { return IsPPC64; }
361 int64_t getImm() const {
362 assert(Kind == Immediate && "Invalid access!");
365 int64_t getImmS16Context() const {
366 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
367 if (Kind == Immediate)
369 return static_cast<int16_t>(Imm.Val);
371 int64_t getImmU16Context() const {
372 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
376 const MCExpr *getExpr() const {
377 assert(Kind == Expression && "Invalid access!");
381 int64_t getExprCRVal() const {
382 assert(Kind == Expression && "Invalid access!");
386 const MCExpr *getTLSReg() const {
387 assert(Kind == TLSRegister && "Invalid access!");
391 unsigned getReg() const override {
392 assert(isRegNumber() && "Invalid access!");
393 return (unsigned) Imm.Val;
396 unsigned getVSReg() const {
397 assert(isVSRegNumber() && "Invalid access!");
398 return (unsigned) Imm.Val;
401 unsigned getCCReg() const {
402 assert(isCCRegNumber() && "Invalid access!");
403 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
406 unsigned getCRBit() const {
407 assert(isCRBitNumber() && "Invalid access!");
408 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
411 unsigned getCRBitMask() const {
412 assert(isCRBitMask() && "Invalid access!");
413 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
416 bool isToken() const override { return Kind == Token; }
417 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
418 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
419 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
420 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
421 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
422 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
423 bool isU6ImmX2() const { return Kind == Immediate &&
424 isUInt<6>(getImm()) &&
425 (getImm() & 1) == 0; }
426 bool isU7ImmX4() const { return Kind == Immediate &&
427 isUInt<7>(getImm()) &&
428 (getImm() & 3) == 0; }
429 bool isU8ImmX8() const { return Kind == Immediate &&
430 isUInt<8>(getImm()) &&
431 (getImm() & 7) == 0; }
432 bool isU16Imm() const {
437 case ContextImmediate:
438 return isUInt<16>(getImmU16Context());
443 bool isS16Imm() const {
448 case ContextImmediate:
449 return isInt<16>(getImmS16Context());
454 bool isS16ImmX4() const { return Kind == Expression ||
455 (Kind == Immediate && isInt<16>(getImm()) &&
456 (getImm() & 3) == 0); }
457 bool isS17Imm() const {
462 case ContextImmediate:
463 return isInt<17>(getImmS16Context());
468 bool isTLSReg() const { return Kind == TLSRegister; }
469 bool isDirectBr() const {
470 if (Kind == Expression)
472 if (Kind != Immediate)
474 // Operand must be 64-bit aligned, signed 27-bit immediate.
475 if ((getImm() & 3) != 0)
477 if (isInt<26>(getImm()))
480 // In 32-bit mode, large 32-bit quantities wrap around.
481 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
486 bool isCondBr() const { return Kind == Expression ||
487 (Kind == Immediate && isInt<16>(getImm()) &&
488 (getImm() & 3) == 0); }
489 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
490 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
491 bool isCCRegNumber() const { return (Kind == Expression
492 && isUInt<3>(getExprCRVal())) ||
494 && isUInt<3>(getImm())); }
495 bool isCRBitNumber() const { return (Kind == Expression
496 && isUInt<5>(getExprCRVal())) ||
498 && isUInt<5>(getImm())); }
499 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
500 isPowerOf2_32(getImm()); }
501 bool isMem() const override { return false; }
502 bool isReg() const override { return false; }
504 void addRegOperands(MCInst &Inst, unsigned N) const {
505 llvm_unreachable("addRegOperands");
508 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
509 assert(N == 1 && "Invalid number of operands!");
510 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
513 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
514 assert(N == 1 && "Invalid number of operands!");
515 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
518 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
519 assert(N == 1 && "Invalid number of operands!");
520 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
523 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
524 assert(N == 1 && "Invalid number of operands!");
525 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
528 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
530 addRegG8RCOperands(Inst, N);
532 addRegGPRCOperands(Inst, N);
535 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
537 addRegG8RCNoX0Operands(Inst, N);
539 addRegGPRCNoR0Operands(Inst, N);
542 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
543 assert(N == 1 && "Invalid number of operands!");
544 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
547 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
548 assert(N == 1 && "Invalid number of operands!");
549 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
552 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
553 assert(N == 1 && "Invalid number of operands!");
554 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
557 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
558 assert(N == 1 && "Invalid number of operands!");
559 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
562 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
563 assert(N == 1 && "Invalid number of operands!");
564 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
567 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
568 assert(N == 1 && "Invalid number of operands!");
569 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
572 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
573 assert(N == 1 && "Invalid number of operands!");
574 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
577 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
578 assert(N == 1 && "Invalid number of operands!");
579 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
582 void addImmOperands(MCInst &Inst, unsigned N) const {
583 assert(N == 1 && "Invalid number of operands!");
584 if (Kind == Immediate)
585 Inst.addOperand(MCOperand::CreateImm(getImm()));
587 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
590 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
591 assert(N == 1 && "Invalid number of operands!");
594 Inst.addOperand(MCOperand::CreateImm(getImm()));
596 case ContextImmediate:
597 Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
600 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
605 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
606 assert(N == 1 && "Invalid number of operands!");
609 Inst.addOperand(MCOperand::CreateImm(getImm()));
611 case ContextImmediate:
612 Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
615 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
620 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
621 assert(N == 1 && "Invalid number of operands!");
622 if (Kind == Immediate)
623 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
625 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
628 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
629 assert(N == 1 && "Invalid number of operands!");
630 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
633 StringRef getToken() const {
634 assert(Kind == Token && "Invalid access!");
635 return StringRef(Tok.Data, Tok.Length);
638 void print(raw_ostream &OS) const override;
640 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
642 auto Op = make_unique<PPCOperand>(Token);
643 Op->Tok.Data = Str.data();
644 Op->Tok.Length = Str.size();
647 Op->IsPPC64 = IsPPC64;
651 static std::unique_ptr<PPCOperand>
652 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
653 // Allocate extra memory for the string and copy it.
654 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
655 // deleter which will destroy them by simply using "delete", not correctly
656 // calling operator delete on this extra memory after calling the dtor
658 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
659 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
660 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
661 Op->Tok.Length = Str.size();
662 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
665 Op->IsPPC64 = IsPPC64;
669 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
671 auto Op = make_unique<PPCOperand>(Immediate);
675 Op->IsPPC64 = IsPPC64;
679 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
680 SMLoc E, bool IsPPC64) {
681 auto Op = make_unique<PPCOperand>(Expression);
683 Op->Expr.CRVal = EvaluateCRExpr(Val);
686 Op->IsPPC64 = IsPPC64;
690 static std::unique_ptr<PPCOperand>
691 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
692 auto Op = make_unique<PPCOperand>(TLSRegister);
693 Op->TLSReg.Sym = Sym;
696 Op->IsPPC64 = IsPPC64;
700 static std::unique_ptr<PPCOperand>
701 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
702 auto Op = make_unique<PPCOperand>(ContextImmediate);
706 Op->IsPPC64 = IsPPC64;
710 static std::unique_ptr<PPCOperand>
711 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
712 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
713 return CreateImm(CE->getValue(), S, E, IsPPC64);
715 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
716 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
717 return CreateTLSReg(SRE, S, E, IsPPC64);
719 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
721 if (TE->EvaluateAsConstant(Res))
722 return CreateContextImm(Res, S, E, IsPPC64);
725 return CreateExpr(Val, S, E, IsPPC64);
729 } // end anonymous namespace.
731 void PPCOperand::print(raw_ostream &OS) const {
734 OS << "'" << getToken() << "'";
737 case ContextImmediate:
741 getExpr()->print(OS);
744 getTLSReg()->print(OS);
750 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
752 Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
755 const MCExpr *Expr = Op.getExpr();
756 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
757 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
758 Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
761 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
762 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
763 const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
764 BinExpr->getLHS(), Ctx);
765 Inst.addOperand(MCOperand::CreateExpr(NE));
769 Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
772 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
773 const OperandVector &Operands) {
774 int Opcode = Inst.getOpcode();
778 TmpInst.setOpcode(PPC::LA);
779 TmpInst.addOperand(Inst.getOperand(0));
780 TmpInst.addOperand(Inst.getOperand(2));
781 TmpInst.addOperand(Inst.getOperand(1));
787 TmpInst.setOpcode(PPC::ADDI);
788 TmpInst.addOperand(Inst.getOperand(0));
789 TmpInst.addOperand(Inst.getOperand(1));
790 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
796 TmpInst.setOpcode(PPC::ADDIS);
797 TmpInst.addOperand(Inst.getOperand(0));
798 TmpInst.addOperand(Inst.getOperand(1));
799 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
805 TmpInst.setOpcode(PPC::ADDIC);
806 TmpInst.addOperand(Inst.getOperand(0));
807 TmpInst.addOperand(Inst.getOperand(1));
808 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
814 TmpInst.setOpcode(PPC::ADDICo);
815 TmpInst.addOperand(Inst.getOperand(0));
816 TmpInst.addOperand(Inst.getOperand(1));
817 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
824 int64_t N = Inst.getOperand(2).getImm();
825 int64_t B = Inst.getOperand(3).getImm();
826 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
827 TmpInst.addOperand(Inst.getOperand(0));
828 TmpInst.addOperand(Inst.getOperand(1));
829 TmpInst.addOperand(MCOperand::CreateImm(B));
830 TmpInst.addOperand(MCOperand::CreateImm(0));
831 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
838 int64_t N = Inst.getOperand(2).getImm();
839 int64_t B = Inst.getOperand(3).getImm();
840 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
841 TmpInst.addOperand(Inst.getOperand(0));
842 TmpInst.addOperand(Inst.getOperand(1));
843 TmpInst.addOperand(MCOperand::CreateImm(B + N));
844 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
845 TmpInst.addOperand(MCOperand::CreateImm(31));
852 int64_t N = Inst.getOperand(2).getImm();
853 int64_t B = Inst.getOperand(3).getImm();
854 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
855 TmpInst.addOperand(Inst.getOperand(0));
856 TmpInst.addOperand(Inst.getOperand(0));
857 TmpInst.addOperand(Inst.getOperand(1));
858 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
859 TmpInst.addOperand(MCOperand::CreateImm(B));
860 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
867 int64_t N = Inst.getOperand(2).getImm();
868 int64_t B = Inst.getOperand(3).getImm();
869 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
870 TmpInst.addOperand(Inst.getOperand(0));
871 TmpInst.addOperand(Inst.getOperand(0));
872 TmpInst.addOperand(Inst.getOperand(1));
873 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
874 TmpInst.addOperand(MCOperand::CreateImm(B));
875 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
882 int64_t N = Inst.getOperand(2).getImm();
883 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
884 TmpInst.addOperand(Inst.getOperand(0));
885 TmpInst.addOperand(Inst.getOperand(1));
886 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
887 TmpInst.addOperand(MCOperand::CreateImm(0));
888 TmpInst.addOperand(MCOperand::CreateImm(31));
895 int64_t N = Inst.getOperand(2).getImm();
896 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
897 TmpInst.addOperand(Inst.getOperand(0));
898 TmpInst.addOperand(Inst.getOperand(1));
899 TmpInst.addOperand(MCOperand::CreateImm(N));
900 TmpInst.addOperand(MCOperand::CreateImm(0));
901 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
908 int64_t N = Inst.getOperand(2).getImm();
909 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
910 TmpInst.addOperand(Inst.getOperand(0));
911 TmpInst.addOperand(Inst.getOperand(1));
912 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
913 TmpInst.addOperand(MCOperand::CreateImm(N));
914 TmpInst.addOperand(MCOperand::CreateImm(31));
921 int64_t N = Inst.getOperand(2).getImm();
922 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
923 TmpInst.addOperand(Inst.getOperand(0));
924 TmpInst.addOperand(Inst.getOperand(1));
925 TmpInst.addOperand(MCOperand::CreateImm(0));
926 TmpInst.addOperand(MCOperand::CreateImm(0));
927 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
932 case PPC::CLRLSLWIo: {
934 int64_t B = Inst.getOperand(2).getImm();
935 int64_t N = Inst.getOperand(3).getImm();
936 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
937 TmpInst.addOperand(Inst.getOperand(0));
938 TmpInst.addOperand(Inst.getOperand(1));
939 TmpInst.addOperand(MCOperand::CreateImm(N));
940 TmpInst.addOperand(MCOperand::CreateImm(B - N));
941 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
948 int64_t N = Inst.getOperand(2).getImm();
949 int64_t B = Inst.getOperand(3).getImm();
950 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
951 TmpInst.addOperand(Inst.getOperand(0));
952 TmpInst.addOperand(Inst.getOperand(1));
953 TmpInst.addOperand(MCOperand::CreateImm(B));
954 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
961 int64_t N = Inst.getOperand(2).getImm();
962 int64_t B = Inst.getOperand(3).getImm();
963 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
964 TmpInst.addOperand(Inst.getOperand(0));
965 TmpInst.addOperand(Inst.getOperand(1));
966 TmpInst.addOperand(MCOperand::CreateImm(B + N));
967 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
974 int64_t N = Inst.getOperand(2).getImm();
975 int64_t B = Inst.getOperand(3).getImm();
976 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
977 TmpInst.addOperand(Inst.getOperand(0));
978 TmpInst.addOperand(Inst.getOperand(0));
979 TmpInst.addOperand(Inst.getOperand(1));
980 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
981 TmpInst.addOperand(MCOperand::CreateImm(B));
988 int64_t N = Inst.getOperand(2).getImm();
989 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
990 TmpInst.addOperand(Inst.getOperand(0));
991 TmpInst.addOperand(Inst.getOperand(1));
992 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
993 TmpInst.addOperand(MCOperand::CreateImm(0));
1000 int64_t N = Inst.getOperand(2).getImm();
1001 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1002 TmpInst.addOperand(Inst.getOperand(0));
1003 TmpInst.addOperand(Inst.getOperand(1));
1004 TmpInst.addOperand(MCOperand::CreateImm(N));
1005 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1012 int64_t N = Inst.getOperand(2).getImm();
1013 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1014 TmpInst.addOperand(Inst.getOperand(0));
1015 TmpInst.addOperand(Inst.getOperand(1));
1016 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1017 TmpInst.addOperand(MCOperand::CreateImm(N));
1022 case PPC::CLRRDIo: {
1024 int64_t N = Inst.getOperand(2).getImm();
1025 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1026 TmpInst.addOperand(Inst.getOperand(0));
1027 TmpInst.addOperand(Inst.getOperand(1));
1028 TmpInst.addOperand(MCOperand::CreateImm(0));
1029 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1034 case PPC::CLRLSLDIo: {
1036 int64_t B = Inst.getOperand(2).getImm();
1037 int64_t N = Inst.getOperand(3).getImm();
1038 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1039 TmpInst.addOperand(Inst.getOperand(0));
1040 TmpInst.addOperand(Inst.getOperand(1));
1041 TmpInst.addOperand(MCOperand::CreateImm(N));
1042 TmpInst.addOperand(MCOperand::CreateImm(B - N));
1049 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1050 OperandVector &Operands,
1051 MCStreamer &Out, uint64_t &ErrorInfo,
1052 bool MatchingInlineAsm) {
1055 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1058 // Post-process instructions (typically extended mnemonics)
1059 ProcessInstruction(Inst, Operands);
1061 Out.EmitInstruction(Inst, STI);
1063 case Match_MissingFeature:
1064 return Error(IDLoc, "instruction use requires an option to be enabled");
1065 case Match_MnemonicFail:
1066 return Error(IDLoc, "unrecognized instruction mnemonic");
1067 case Match_InvalidOperand: {
1068 SMLoc ErrorLoc = IDLoc;
1069 if (ErrorInfo != ~0ULL) {
1070 if (ErrorInfo >= Operands.size())
1071 return Error(IDLoc, "too few operands for instruction");
1073 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1074 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1077 return Error(ErrorLoc, "invalid operand for instruction");
1081 llvm_unreachable("Implement any new match types added!");
1085 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1086 if (Tok.is(AsmToken::Identifier)) {
1087 StringRef Name = Tok.getString();
1089 if (Name.equals_lower("lr")) {
1090 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1093 } else if (Name.equals_lower("ctr")) {
1094 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1097 } else if (Name.equals_lower("vrsave")) {
1098 RegNo = PPC::VRSAVE;
1101 } else if (Name.startswith_lower("r") &&
1102 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1103 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1105 } else if (Name.startswith_lower("f") &&
1106 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1107 RegNo = FRegs[IntVal];
1109 } else if (Name.startswith_lower("v") &&
1110 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1111 RegNo = VRegs[IntVal];
1113 } else if (Name.startswith_lower("cr") &&
1114 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1115 RegNo = CRRegs[IntVal];
1124 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1125 MCAsmParser &Parser = getParser();
1126 const AsmToken &Tok = Parser.getTok();
1127 StartLoc = Tok.getLoc();
1128 EndLoc = Tok.getEndLoc();
1132 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1133 Parser.Lex(); // Eat identifier token.
1137 return Error(StartLoc, "invalid register name");
1140 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1141 /// the expression and check for VK_PPC_LO/HI/HA
1142 /// symbol variants. If all symbols with modifier use the same
1143 /// variant, return the corresponding PPCMCExpr::VariantKind,
1144 /// and a modified expression using the default symbol variant.
1145 /// Otherwise, return NULL.
1146 const MCExpr *PPCAsmParser::
1147 ExtractModifierFromExpr(const MCExpr *E,
1148 PPCMCExpr::VariantKind &Variant) {
1149 MCContext &Context = getParser().getContext();
1150 Variant = PPCMCExpr::VK_PPC_None;
1152 switch (E->getKind()) {
1153 case MCExpr::Target:
1154 case MCExpr::Constant:
1157 case MCExpr::SymbolRef: {
1158 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1160 switch (SRE->getKind()) {
1161 case MCSymbolRefExpr::VK_PPC_LO:
1162 Variant = PPCMCExpr::VK_PPC_LO;
1164 case MCSymbolRefExpr::VK_PPC_HI:
1165 Variant = PPCMCExpr::VK_PPC_HI;
1167 case MCSymbolRefExpr::VK_PPC_HA:
1168 Variant = PPCMCExpr::VK_PPC_HA;
1170 case MCSymbolRefExpr::VK_PPC_HIGHER:
1171 Variant = PPCMCExpr::VK_PPC_HIGHER;
1173 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1174 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1176 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1177 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1179 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1180 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1186 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1189 case MCExpr::Unary: {
1190 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1191 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1194 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1197 case MCExpr::Binary: {
1198 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1199 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1200 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1201 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1206 if (!LHS) LHS = BE->getLHS();
1207 if (!RHS) RHS = BE->getRHS();
1209 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1210 Variant = RHSVariant;
1211 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1212 Variant = LHSVariant;
1213 else if (LHSVariant == RHSVariant)
1214 Variant = LHSVariant;
1218 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1222 llvm_unreachable("Invalid expression kind!");
1225 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1226 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1227 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1228 /// FIXME: This is a hack.
1229 const MCExpr *PPCAsmParser::
1230 FixupVariantKind(const MCExpr *E) {
1231 MCContext &Context = getParser().getContext();
1233 switch (E->getKind()) {
1234 case MCExpr::Target:
1235 case MCExpr::Constant:
1238 case MCExpr::SymbolRef: {
1239 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1240 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1242 switch (SRE->getKind()) {
1243 case MCSymbolRefExpr::VK_TLSGD:
1244 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1246 case MCSymbolRefExpr::VK_TLSLD:
1247 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1252 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1255 case MCExpr::Unary: {
1256 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1257 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1258 if (Sub == UE->getSubExpr())
1260 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1263 case MCExpr::Binary: {
1264 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1265 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1266 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1267 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1269 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1273 llvm_unreachable("Invalid expression kind!");
1276 /// ParseExpression. This differs from the default "parseExpression" in that
1277 /// it handles modifiers.
1279 ParseExpression(const MCExpr *&EVal) {
1282 return ParseDarwinExpression(EVal);
1285 // Handle \code @l/@ha \endcode
1286 if (getParser().parseExpression(EVal))
1289 EVal = FixupVariantKind(EVal);
1291 PPCMCExpr::VariantKind Variant;
1292 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1294 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1299 /// ParseDarwinExpression. (MachO Platforms)
1300 /// This differs from the default "parseExpression" in that it handles detection
1301 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1302 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1303 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1304 /// for this to be done at a higher level.
1306 ParseDarwinExpression(const MCExpr *&EVal) {
1307 MCAsmParser &Parser = getParser();
1308 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1309 switch (getLexer().getKind()) {
1312 case AsmToken::Identifier:
1313 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1314 // something starting with any other char should be part of the
1315 // asm syntax. If handwritten asm includes an identifier like lo16,
1316 // then all bets are off - but no-one would do that, right?
1317 StringRef poss = Parser.getTok().getString();
1318 if (poss.equals_lower("lo16")) {
1319 Variant = PPCMCExpr::VK_PPC_LO;
1320 } else if (poss.equals_lower("hi16")) {
1321 Variant = PPCMCExpr::VK_PPC_HI;
1322 } else if (poss.equals_lower("ha16")) {
1323 Variant = PPCMCExpr::VK_PPC_HA;
1325 if (Variant != PPCMCExpr::VK_PPC_None) {
1326 Parser.Lex(); // Eat the xx16
1327 if (getLexer().isNot(AsmToken::LParen))
1328 return Error(Parser.getTok().getLoc(), "expected '('");
1329 Parser.Lex(); // Eat the '('
1334 if (getParser().parseExpression(EVal))
1337 if (Variant != PPCMCExpr::VK_PPC_None) {
1338 if (getLexer().isNot(AsmToken::RParen))
1339 return Error(Parser.getTok().getLoc(), "expected ')'");
1340 Parser.Lex(); // Eat the ')'
1341 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1347 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1349 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1350 MCAsmParser &Parser = getParser();
1351 SMLoc S = Parser.getTok().getLoc();
1352 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1355 // Attempt to parse the next token as an immediate
1356 switch (getLexer().getKind()) {
1357 // Special handling for register names. These are interpreted
1358 // as immediates corresponding to the register number.
1359 case AsmToken::Percent:
1360 Parser.Lex(); // Eat the '%'.
1363 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1364 Parser.Lex(); // Eat the identifier token.
1365 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1368 return Error(S, "invalid register name");
1370 case AsmToken::Identifier:
1371 // Note that non-register-name identifiers from the compiler will begin
1372 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1373 // identifiers like r31foo - so we fall through in the event that parsing
1374 // a register name fails.
1378 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1379 Parser.Lex(); // Eat the identifier token.
1380 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1384 // Fall-through to process non-register-name identifiers as expression.
1385 // All other expressions
1386 case AsmToken::LParen:
1387 case AsmToken::Plus:
1388 case AsmToken::Minus:
1389 case AsmToken::Integer:
1391 case AsmToken::Dollar:
1392 case AsmToken::Exclaim:
1393 case AsmToken::Tilde:
1394 if (!ParseExpression(EVal))
1398 return Error(S, "unknown operand");
1401 // Push the parsed operand into the list of operands
1402 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1404 // Check whether this is a TLS call expression
1405 bool TLSCall = false;
1406 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1407 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1409 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1410 const MCExpr *TLSSym;
1412 Parser.Lex(); // Eat the '('.
1413 S = Parser.getTok().getLoc();
1414 if (ParseExpression(TLSSym))
1415 return Error(S, "invalid TLS call expression");
1416 if (getLexer().isNot(AsmToken::RParen))
1417 return Error(Parser.getTok().getLoc(), "missing ')'");
1418 E = Parser.getTok().getLoc();
1419 Parser.Lex(); // Eat the ')'.
1421 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1424 // Otherwise, check for D-form memory operands
1425 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1426 Parser.Lex(); // Eat the '('.
1427 S = Parser.getTok().getLoc();
1430 switch (getLexer().getKind()) {
1431 case AsmToken::Percent:
1432 Parser.Lex(); // Eat the '%'.
1434 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1435 return Error(S, "invalid register name");
1436 Parser.Lex(); // Eat the identifier token.
1439 case AsmToken::Integer:
1441 if (getParser().parseAbsoluteExpression(IntVal) ||
1442 IntVal < 0 || IntVal > 31)
1443 return Error(S, "invalid register number");
1445 return Error(S, "unexpected integer value");
1449 case AsmToken::Identifier:
1452 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1453 Parser.Lex(); // Eat the identifier token.
1460 return Error(S, "invalid memory operand");
1463 if (getLexer().isNot(AsmToken::RParen))
1464 return Error(Parser.getTok().getLoc(), "missing ')'");
1465 E = Parser.getTok().getLoc();
1466 Parser.Lex(); // Eat the ')'.
1468 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1474 /// Parse an instruction mnemonic followed by its operands.
1475 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1476 SMLoc NameLoc, OperandVector &Operands) {
1477 // The first operand is the token for the instruction name.
1478 // If the next character is a '+' or '-', we need to add it to the
1479 // instruction name, to match what TableGen is doing.
1480 std::string NewOpcode;
1481 if (getLexer().is(AsmToken::Plus)) {
1487 if (getLexer().is(AsmToken::Minus)) {
1493 // If the instruction ends in a '.', we need to create a separate
1494 // token for it, to match what TableGen is doing.
1495 size_t Dot = Name.find('.');
1496 StringRef Mnemonic = Name.slice(0, Dot);
1497 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1499 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1501 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1502 if (Dot != StringRef::npos) {
1503 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1504 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1505 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1507 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1509 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1512 // If there are no more operands then finish
1513 if (getLexer().is(AsmToken::EndOfStatement))
1516 // Parse the first operand
1517 if (ParseOperand(Operands))
1520 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1521 getLexer().is(AsmToken::Comma)) {
1522 // Consume the comma token
1525 // Parse the next operand
1526 if (ParseOperand(Operands))
1533 /// ParseDirective parses the PPC specific directives
1534 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1535 StringRef IDVal = DirectiveID.getIdentifier();
1537 if (IDVal == ".word")
1538 return ParseDirectiveWord(2, DirectiveID.getLoc());
1539 if (IDVal == ".llong")
1540 return ParseDirectiveWord(8, DirectiveID.getLoc());
1542 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1543 if (IDVal == ".machine")
1544 return ParseDirectiveMachine(DirectiveID.getLoc());
1545 if (IDVal == ".abiversion")
1546 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1547 if (IDVal == ".localentry")
1548 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1550 if (IDVal == ".machine")
1551 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1556 /// ParseDirectiveWord
1557 /// ::= .word [ expression (, expression)* ]
1558 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1559 MCAsmParser &Parser = getParser();
1560 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1562 const MCExpr *Value;
1563 if (getParser().parseExpression(Value))
1566 getParser().getStreamer().EmitValue(Value, Size);
1568 if (getLexer().is(AsmToken::EndOfStatement))
1571 if (getLexer().isNot(AsmToken::Comma))
1572 return Error(L, "unexpected token in directive");
1581 /// ParseDirectiveTC
1582 /// ::= .tc [ symbol (, expression)* ]
1583 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1584 MCAsmParser &Parser = getParser();
1585 // Skip TC symbol, which is only used with XCOFF.
1586 while (getLexer().isNot(AsmToken::EndOfStatement)
1587 && getLexer().isNot(AsmToken::Comma))
1589 if (getLexer().isNot(AsmToken::Comma)) {
1590 Error(L, "unexpected token in directive");
1595 // Align to word size.
1596 getParser().getStreamer().EmitValueToAlignment(Size);
1598 // Emit expressions.
1599 return ParseDirectiveWord(Size, L);
1602 /// ParseDirectiveMachine (ELF platforms)
1603 /// ::= .machine [ cpu | "push" | "pop" ]
1604 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1605 MCAsmParser &Parser = getParser();
1606 if (getLexer().isNot(AsmToken::Identifier) &&
1607 getLexer().isNot(AsmToken::String)) {
1608 Error(L, "unexpected token in directive");
1612 StringRef CPU = Parser.getTok().getIdentifier();
1615 // FIXME: Right now, the parser always allows any available
1616 // instruction, so the .machine directive is not useful.
1617 // Implement ".machine any" (by doing nothing) for the benefit
1618 // of existing assembler code. Likewise, we can then implement
1619 // ".machine push" and ".machine pop" as no-op.
1620 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1621 Error(L, "unrecognized machine type");
1625 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1626 Error(L, "unexpected token in directive");
1629 PPCTargetStreamer &TStreamer =
1630 *static_cast<PPCTargetStreamer *>(
1631 getParser().getStreamer().getTargetStreamer());
1632 TStreamer.emitMachine(CPU);
1637 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1638 /// ::= .machine cpu-identifier
1639 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1640 MCAsmParser &Parser = getParser();
1641 if (getLexer().isNot(AsmToken::Identifier) &&
1642 getLexer().isNot(AsmToken::String)) {
1643 Error(L, "unexpected token in directive");
1647 StringRef CPU = Parser.getTok().getIdentifier();
1650 // FIXME: this is only the 'default' set of cpu variants.
1651 // However we don't act on this information at present, this is simply
1652 // allowing parsing to proceed with minimal sanity checking.
1653 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1654 Error(L, "unrecognized cpu type");
1658 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1659 Error(L, "wrong cpu type specified for 64bit");
1662 if (!isPPC64() && CPU == "ppc64") {
1663 Error(L, "wrong cpu type specified for 32bit");
1667 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1668 Error(L, "unexpected token in directive");
1675 /// ParseDirectiveAbiVersion
1676 /// ::= .abiversion constant-expression
1677 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1679 if (getParser().parseAbsoluteExpression(AbiVersion)){
1680 Error(L, "expected constant expression");
1683 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1684 Error(L, "unexpected token in directive");
1688 PPCTargetStreamer &TStreamer =
1689 *static_cast<PPCTargetStreamer *>(
1690 getParser().getStreamer().getTargetStreamer());
1691 TStreamer.emitAbiVersion(AbiVersion);
1696 /// ParseDirectiveLocalEntry
1697 /// ::= .localentry symbol, expression
1698 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1700 if (getParser().parseIdentifier(Name)) {
1701 Error(L, "expected identifier in directive");
1704 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1706 if (getLexer().isNot(AsmToken::Comma)) {
1707 Error(L, "unexpected token in directive");
1713 if (getParser().parseExpression(Expr)) {
1714 Error(L, "expected expression");
1718 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1719 Error(L, "unexpected token in directive");
1723 PPCTargetStreamer &TStreamer =
1724 *static_cast<PPCTargetStreamer *>(
1725 getParser().getStreamer().getTargetStreamer());
1726 TStreamer.emitLocalEntry(Sym, Expr);
1733 /// Force static initialization.
1734 extern "C" void LLVMInitializePowerPCAsmParser() {
1735 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1736 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1737 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1740 #define GET_REGISTER_MATCHER
1741 #define GET_MATCHER_IMPLEMENTATION
1742 #include "PPCGenAsmMatcher.inc"
1744 // Define this matcher function after the auto-generated include so we
1745 // have the match class enum definitions.
1746 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1748 // If the kind is a token for a literal immediate, check if our asm
1749 // operand matches. This is for InstAliases which have a fixed-value
1750 // immediate in the syntax.
1753 case MCK_0: ImmVal = 0; break;
1754 case MCK_1: ImmVal = 1; break;
1755 case MCK_2: ImmVal = 2; break;
1756 case MCK_3: ImmVal = 3; break;
1757 case MCK_4: ImmVal = 4; break;
1758 case MCK_5: ImmVal = 5; break;
1759 case MCK_6: ImmVal = 6; break;
1760 case MCK_7: ImmVal = 7; break;
1761 default: return Match_InvalidOperand;
1764 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1765 if (Op.isImm() && Op.getImm() == ImmVal)
1766 return Match_Success;
1768 return Match_InvalidOperand;
1772 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1773 MCSymbolRefExpr::VariantKind Variant,
1776 case MCSymbolRefExpr::VK_PPC_LO:
1777 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1778 case MCSymbolRefExpr::VK_PPC_HI:
1779 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1780 case MCSymbolRefExpr::VK_PPC_HA:
1781 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1782 case MCSymbolRefExpr::VK_PPC_HIGHER:
1783 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1784 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1785 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1786 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1787 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1788 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1789 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);