1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
37 static unsigned RRegs[32] = {
38 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
39 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
40 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
41 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
42 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
43 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
44 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
45 PPC::R28, PPC::R29, PPC::R30, PPC::R31
47 static unsigned RRegsNoR0[32] = {
49 PPC::R1, PPC::R2, PPC::R3,
50 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
51 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
52 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
53 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
54 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
55 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
56 PPC::R28, PPC::R29, PPC::R30, PPC::R31
58 static unsigned XRegs[32] = {
59 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
60 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
61 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
62 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
63 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
64 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
65 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
66 PPC::X28, PPC::X29, PPC::X30, PPC::X31
68 static unsigned XRegsNoX0[32] = {
70 PPC::X1, PPC::X2, PPC::X3,
71 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
72 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
73 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
74 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
75 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
76 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
77 PPC::X28, PPC::X29, PPC::X30, PPC::X31
79 static unsigned FRegs[32] = {
80 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
81 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
82 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
83 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
84 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
85 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
86 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
87 PPC::F28, PPC::F29, PPC::F30, PPC::F31
89 static unsigned VRegs[32] = {
90 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
91 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
92 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
93 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
94 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
95 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
96 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
97 PPC::V28, PPC::V29, PPC::V30, PPC::V31
99 static unsigned VSRegs[64] = {
100 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
101 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
102 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
103 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
104 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
105 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
106 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
107 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
109 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
110 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
111 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
112 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
113 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
114 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
115 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
116 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
118 static unsigned VSFRegs[64] = {
119 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
120 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
121 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
122 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
123 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
124 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
125 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
126 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
128 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
129 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
130 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
131 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
132 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
133 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
134 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
135 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
137 static unsigned CRBITRegs[32] = {
138 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
139 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
140 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
141 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
142 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
143 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
144 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
145 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
147 static unsigned CRRegs[8] = {
148 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
149 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
152 // Evaluate an expression containing condition register
153 // or condition register field symbols. Returns positive
154 // value on success, or -1 on error.
156 EvaluateCRExpr(const MCExpr *E) {
157 switch (E->getKind()) {
161 case MCExpr::Constant: {
162 int64_t Res = cast<MCConstantExpr>(E)->getValue();
163 return Res < 0 ? -1 : Res;
166 case MCExpr::SymbolRef: {
167 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
168 StringRef Name = SRE->getSymbol().getName();
170 if (Name == "lt") return 0;
171 if (Name == "gt") return 1;
172 if (Name == "eq") return 2;
173 if (Name == "so") return 3;
174 if (Name == "un") return 3;
176 if (Name == "cr0") return 0;
177 if (Name == "cr1") return 1;
178 if (Name == "cr2") return 2;
179 if (Name == "cr3") return 3;
180 if (Name == "cr4") return 4;
181 if (Name == "cr5") return 5;
182 if (Name == "cr6") return 6;
183 if (Name == "cr7") return 7;
191 case MCExpr::Binary: {
192 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
193 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
194 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
197 if (LHSVal < 0 || RHSVal < 0)
200 switch (BE->getOpcode()) {
202 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
203 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
206 return Res < 0 ? -1 : Res;
210 llvm_unreachable("Invalid expression kind!");
215 class PPCAsmParser : public MCTargetAsmParser {
216 MCSubtargetInfo &STI;
218 const MCInstrInfo &MII;
222 MCAsmParser &getParser() const { return Parser; }
223 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
225 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
226 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
228 bool isPPC64() const { return IsPPC64; }
229 bool isDarwin() const { return IsDarwin; }
231 bool MatchRegisterName(const AsmToken &Tok,
232 unsigned &RegNo, int64_t &IntVal);
234 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
236 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
237 PPCMCExpr::VariantKind &Variant);
238 const MCExpr *FixupVariantKind(const MCExpr *E);
239 bool ParseExpression(const MCExpr *&EVal);
240 bool ParseDarwinExpression(const MCExpr *&EVal);
242 bool ParseOperand(OperandVector &Operands);
244 bool ParseDirectiveWord(unsigned Size, SMLoc L);
245 bool ParseDirectiveTC(unsigned Size, SMLoc L);
246 bool ParseDirectiveMachine(SMLoc L);
247 bool ParseDarwinDirectiveMachine(SMLoc L);
248 bool ParseDirectiveAbiVersion(SMLoc L);
249 bool ParseDirectiveLocalEntry(SMLoc L);
251 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
252 OperandVector &Operands, MCStreamer &Out,
254 bool MatchingInlineAsm) override;
256 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
258 /// @name Auto-generated Match Functions
261 #define GET_ASSEMBLER_HEADER
262 #include "PPCGenAsmMatcher.inc"
268 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
269 const MCInstrInfo &_MII,
270 const MCTargetOptions &Options)
271 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
272 // Check for 64-bit vs. 32-bit pointer mode.
273 Triple TheTriple(STI.getTargetTriple());
274 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
275 TheTriple.getArch() == Triple::ppc64le);
276 IsDarwin = TheTriple.isMacOSX();
277 // Initialize the set of available features.
278 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
281 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
282 SMLoc NameLoc, OperandVector &Operands) override;
284 bool ParseDirective(AsmToken DirectiveID) override;
286 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
287 unsigned Kind) override;
289 const MCExpr *applyModifierToExpr(const MCExpr *E,
290 MCSymbolRefExpr::VariantKind,
291 MCContext &Ctx) override;
294 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
296 struct PPCOperand : public MCParsedAsmOperand {
305 SMLoc StartLoc, EndLoc;
319 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
323 const MCSymbolRefExpr *Sym;
330 struct TLSRegOp TLSReg;
333 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
335 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
337 StartLoc = o.StartLoc;
345 case ContextImmediate:
357 /// getStartLoc - Get the location of the first token of this operand.
358 SMLoc getStartLoc() const override { return StartLoc; }
360 /// getEndLoc - Get the location of the last token of this operand.
361 SMLoc getEndLoc() const override { return EndLoc; }
363 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
364 bool isPPC64() const { return IsPPC64; }
366 int64_t getImm() const {
367 assert(Kind == Immediate && "Invalid access!");
370 int64_t getImmS16Context() const {
371 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
372 if (Kind == Immediate)
374 return static_cast<int16_t>(Imm.Val);
376 int64_t getImmU16Context() const {
377 assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
381 const MCExpr *getExpr() const {
382 assert(Kind == Expression && "Invalid access!");
386 int64_t getExprCRVal() const {
387 assert(Kind == Expression && "Invalid access!");
391 const MCExpr *getTLSReg() const {
392 assert(Kind == TLSRegister && "Invalid access!");
396 unsigned getReg() const override {
397 assert(isRegNumber() && "Invalid access!");
398 return (unsigned) Imm.Val;
401 unsigned getVSReg() const {
402 assert(isVSRegNumber() && "Invalid access!");
403 return (unsigned) Imm.Val;
406 unsigned getCCReg() const {
407 assert(isCCRegNumber() && "Invalid access!");
408 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
411 unsigned getCRBit() const {
412 assert(isCRBitNumber() && "Invalid access!");
413 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
416 unsigned getCRBitMask() const {
417 assert(isCRBitMask() && "Invalid access!");
418 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
421 bool isToken() const override { return Kind == Token; }
422 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
423 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
424 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
425 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
426 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
427 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
428 bool isU6ImmX2() const { return Kind == Immediate &&
429 isUInt<6>(getImm()) &&
430 (getImm() & 1) == 0; }
431 bool isU7ImmX4() const { return Kind == Immediate &&
432 isUInt<7>(getImm()) &&
433 (getImm() & 3) == 0; }
434 bool isU8ImmX8() const { return Kind == Immediate &&
435 isUInt<8>(getImm()) &&
436 (getImm() & 7) == 0; }
437 bool isU16Imm() const {
442 case ContextImmediate:
443 return isUInt<16>(getImmU16Context());
448 bool isS16Imm() const {
453 case ContextImmediate:
454 return isInt<16>(getImmS16Context());
459 bool isS16ImmX4() const { return Kind == Expression ||
460 (Kind == Immediate && isInt<16>(getImm()) &&
461 (getImm() & 3) == 0); }
462 bool isS17Imm() const {
467 case ContextImmediate:
468 return isInt<17>(getImmS16Context());
473 bool isTLSReg() const { return Kind == TLSRegister; }
474 bool isDirectBr() const {
475 if (Kind == Expression)
477 if (Kind != Immediate)
479 // Operand must be 64-bit aligned, signed 27-bit immediate.
480 if ((getImm() & 3) != 0)
482 if (isInt<26>(getImm()))
485 // In 32-bit mode, large 32-bit quantities wrap around.
486 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
491 bool isCondBr() const { return Kind == Expression ||
492 (Kind == Immediate && isInt<16>(getImm()) &&
493 (getImm() & 3) == 0); }
494 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
495 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
496 bool isCCRegNumber() const { return (Kind == Expression
497 && isUInt<3>(getExprCRVal())) ||
499 && isUInt<3>(getImm())); }
500 bool isCRBitNumber() const { return (Kind == Expression
501 && isUInt<5>(getExprCRVal())) ||
503 && isUInt<5>(getImm())); }
504 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
505 isPowerOf2_32(getImm()); }
506 bool isMem() const override { return false; }
507 bool isReg() const override { return false; }
509 void addRegOperands(MCInst &Inst, unsigned N) const {
510 llvm_unreachable("addRegOperands");
513 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
514 assert(N == 1 && "Invalid number of operands!");
515 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
518 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
519 assert(N == 1 && "Invalid number of operands!");
520 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
523 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
524 assert(N == 1 && "Invalid number of operands!");
525 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
528 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
529 assert(N == 1 && "Invalid number of operands!");
530 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
533 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
535 addRegG8RCOperands(Inst, N);
537 addRegGPRCOperands(Inst, N);
540 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
542 addRegG8RCNoX0Operands(Inst, N);
544 addRegGPRCNoR0Operands(Inst, N);
547 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
548 assert(N == 1 && "Invalid number of operands!");
549 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
552 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
553 assert(N == 1 && "Invalid number of operands!");
554 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
557 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
558 assert(N == 1 && "Invalid number of operands!");
559 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
562 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
563 assert(N == 1 && "Invalid number of operands!");
564 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
567 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
568 assert(N == 1 && "Invalid number of operands!");
569 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
572 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
573 assert(N == 1 && "Invalid number of operands!");
574 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
577 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
578 assert(N == 1 && "Invalid number of operands!");
579 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
582 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
583 assert(N == 1 && "Invalid number of operands!");
584 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
587 void addImmOperands(MCInst &Inst, unsigned N) const {
588 assert(N == 1 && "Invalid number of operands!");
589 if (Kind == Immediate)
590 Inst.addOperand(MCOperand::CreateImm(getImm()));
592 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
595 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
596 assert(N == 1 && "Invalid number of operands!");
599 Inst.addOperand(MCOperand::CreateImm(getImm()));
601 case ContextImmediate:
602 Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
605 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
610 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
611 assert(N == 1 && "Invalid number of operands!");
614 Inst.addOperand(MCOperand::CreateImm(getImm()));
616 case ContextImmediate:
617 Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
620 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
625 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
626 assert(N == 1 && "Invalid number of operands!");
627 if (Kind == Immediate)
628 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
630 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
633 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
634 assert(N == 1 && "Invalid number of operands!");
635 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
638 StringRef getToken() const {
639 assert(Kind == Token && "Invalid access!");
640 return StringRef(Tok.Data, Tok.Length);
643 void print(raw_ostream &OS) const override;
645 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
647 auto Op = make_unique<PPCOperand>(Token);
648 Op->Tok.Data = Str.data();
649 Op->Tok.Length = Str.size();
652 Op->IsPPC64 = IsPPC64;
656 static std::unique_ptr<PPCOperand>
657 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
658 // Allocate extra memory for the string and copy it.
659 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
660 // deleter which will destroy them by simply using "delete", not correctly
661 // calling operator delete on this extra memory after calling the dtor
663 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
664 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
665 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
666 Op->Tok.Length = Str.size();
667 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
670 Op->IsPPC64 = IsPPC64;
674 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
676 auto Op = make_unique<PPCOperand>(Immediate);
680 Op->IsPPC64 = IsPPC64;
684 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
685 SMLoc E, bool IsPPC64) {
686 auto Op = make_unique<PPCOperand>(Expression);
688 Op->Expr.CRVal = EvaluateCRExpr(Val);
691 Op->IsPPC64 = IsPPC64;
695 static std::unique_ptr<PPCOperand>
696 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
697 auto Op = make_unique<PPCOperand>(TLSRegister);
698 Op->TLSReg.Sym = Sym;
701 Op->IsPPC64 = IsPPC64;
705 static std::unique_ptr<PPCOperand>
706 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
707 auto Op = make_unique<PPCOperand>(ContextImmediate);
711 Op->IsPPC64 = IsPPC64;
715 static std::unique_ptr<PPCOperand>
716 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
717 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
718 return CreateImm(CE->getValue(), S, E, IsPPC64);
720 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
721 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
722 return CreateTLSReg(SRE, S, E, IsPPC64);
724 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
726 if (TE->EvaluateAsConstant(Res))
727 return CreateContextImm(Res, S, E, IsPPC64);
730 return CreateExpr(Val, S, E, IsPPC64);
734 } // end anonymous namespace.
736 void PPCOperand::print(raw_ostream &OS) const {
739 OS << "'" << getToken() << "'";
742 case ContextImmediate:
746 getExpr()->print(OS);
749 getTLSReg()->print(OS);
755 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
757 Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
760 const MCExpr *Expr = Op.getExpr();
761 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
762 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
763 Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
766 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
767 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
768 const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
769 BinExpr->getLHS(), Ctx);
770 Inst.addOperand(MCOperand::CreateExpr(NE));
774 Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
777 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
778 const OperandVector &Operands) {
779 int Opcode = Inst.getOpcode();
783 TmpInst.setOpcode(PPC::LA);
784 TmpInst.addOperand(Inst.getOperand(0));
785 TmpInst.addOperand(Inst.getOperand(2));
786 TmpInst.addOperand(Inst.getOperand(1));
792 TmpInst.setOpcode(PPC::ADDI);
793 TmpInst.addOperand(Inst.getOperand(0));
794 TmpInst.addOperand(Inst.getOperand(1));
795 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
801 TmpInst.setOpcode(PPC::ADDIS);
802 TmpInst.addOperand(Inst.getOperand(0));
803 TmpInst.addOperand(Inst.getOperand(1));
804 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
810 TmpInst.setOpcode(PPC::ADDIC);
811 TmpInst.addOperand(Inst.getOperand(0));
812 TmpInst.addOperand(Inst.getOperand(1));
813 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
819 TmpInst.setOpcode(PPC::ADDICo);
820 TmpInst.addOperand(Inst.getOperand(0));
821 TmpInst.addOperand(Inst.getOperand(1));
822 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
829 int64_t N = Inst.getOperand(2).getImm();
830 int64_t B = Inst.getOperand(3).getImm();
831 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
832 TmpInst.addOperand(Inst.getOperand(0));
833 TmpInst.addOperand(Inst.getOperand(1));
834 TmpInst.addOperand(MCOperand::CreateImm(B));
835 TmpInst.addOperand(MCOperand::CreateImm(0));
836 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
843 int64_t N = Inst.getOperand(2).getImm();
844 int64_t B = Inst.getOperand(3).getImm();
845 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
846 TmpInst.addOperand(Inst.getOperand(0));
847 TmpInst.addOperand(Inst.getOperand(1));
848 TmpInst.addOperand(MCOperand::CreateImm(B + N));
849 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
850 TmpInst.addOperand(MCOperand::CreateImm(31));
857 int64_t N = Inst.getOperand(2).getImm();
858 int64_t B = Inst.getOperand(3).getImm();
859 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
860 TmpInst.addOperand(Inst.getOperand(0));
861 TmpInst.addOperand(Inst.getOperand(0));
862 TmpInst.addOperand(Inst.getOperand(1));
863 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
864 TmpInst.addOperand(MCOperand::CreateImm(B));
865 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
872 int64_t N = Inst.getOperand(2).getImm();
873 int64_t B = Inst.getOperand(3).getImm();
874 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
875 TmpInst.addOperand(Inst.getOperand(0));
876 TmpInst.addOperand(Inst.getOperand(0));
877 TmpInst.addOperand(Inst.getOperand(1));
878 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
879 TmpInst.addOperand(MCOperand::CreateImm(B));
880 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
887 int64_t N = Inst.getOperand(2).getImm();
888 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
889 TmpInst.addOperand(Inst.getOperand(0));
890 TmpInst.addOperand(Inst.getOperand(1));
891 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
892 TmpInst.addOperand(MCOperand::CreateImm(0));
893 TmpInst.addOperand(MCOperand::CreateImm(31));
900 int64_t N = Inst.getOperand(2).getImm();
901 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
902 TmpInst.addOperand(Inst.getOperand(0));
903 TmpInst.addOperand(Inst.getOperand(1));
904 TmpInst.addOperand(MCOperand::CreateImm(N));
905 TmpInst.addOperand(MCOperand::CreateImm(0));
906 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
913 int64_t N = Inst.getOperand(2).getImm();
914 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
915 TmpInst.addOperand(Inst.getOperand(0));
916 TmpInst.addOperand(Inst.getOperand(1));
917 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
918 TmpInst.addOperand(MCOperand::CreateImm(N));
919 TmpInst.addOperand(MCOperand::CreateImm(31));
926 int64_t N = Inst.getOperand(2).getImm();
927 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
928 TmpInst.addOperand(Inst.getOperand(0));
929 TmpInst.addOperand(Inst.getOperand(1));
930 TmpInst.addOperand(MCOperand::CreateImm(0));
931 TmpInst.addOperand(MCOperand::CreateImm(0));
932 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
937 case PPC::CLRLSLWIo: {
939 int64_t B = Inst.getOperand(2).getImm();
940 int64_t N = Inst.getOperand(3).getImm();
941 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
942 TmpInst.addOperand(Inst.getOperand(0));
943 TmpInst.addOperand(Inst.getOperand(1));
944 TmpInst.addOperand(MCOperand::CreateImm(N));
945 TmpInst.addOperand(MCOperand::CreateImm(B - N));
946 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
953 int64_t N = Inst.getOperand(2).getImm();
954 int64_t B = Inst.getOperand(3).getImm();
955 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
956 TmpInst.addOperand(Inst.getOperand(0));
957 TmpInst.addOperand(Inst.getOperand(1));
958 TmpInst.addOperand(MCOperand::CreateImm(B));
959 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
966 int64_t N = Inst.getOperand(2).getImm();
967 int64_t B = Inst.getOperand(3).getImm();
968 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
969 TmpInst.addOperand(Inst.getOperand(0));
970 TmpInst.addOperand(Inst.getOperand(1));
971 TmpInst.addOperand(MCOperand::CreateImm(B + N));
972 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
979 int64_t N = Inst.getOperand(2).getImm();
980 int64_t B = Inst.getOperand(3).getImm();
981 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
982 TmpInst.addOperand(Inst.getOperand(0));
983 TmpInst.addOperand(Inst.getOperand(0));
984 TmpInst.addOperand(Inst.getOperand(1));
985 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
986 TmpInst.addOperand(MCOperand::CreateImm(B));
993 int64_t N = Inst.getOperand(2).getImm();
994 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
995 TmpInst.addOperand(Inst.getOperand(0));
996 TmpInst.addOperand(Inst.getOperand(1));
997 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
998 TmpInst.addOperand(MCOperand::CreateImm(0));
1005 int64_t N = Inst.getOperand(2).getImm();
1006 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1007 TmpInst.addOperand(Inst.getOperand(0));
1008 TmpInst.addOperand(Inst.getOperand(1));
1009 TmpInst.addOperand(MCOperand::CreateImm(N));
1010 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1017 int64_t N = Inst.getOperand(2).getImm();
1018 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1019 TmpInst.addOperand(Inst.getOperand(0));
1020 TmpInst.addOperand(Inst.getOperand(1));
1021 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1022 TmpInst.addOperand(MCOperand::CreateImm(N));
1027 case PPC::CLRRDIo: {
1029 int64_t N = Inst.getOperand(2).getImm();
1030 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1031 TmpInst.addOperand(Inst.getOperand(0));
1032 TmpInst.addOperand(Inst.getOperand(1));
1033 TmpInst.addOperand(MCOperand::CreateImm(0));
1034 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1039 case PPC::CLRLSLDIo: {
1041 int64_t B = Inst.getOperand(2).getImm();
1042 int64_t N = Inst.getOperand(3).getImm();
1043 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1044 TmpInst.addOperand(Inst.getOperand(0));
1045 TmpInst.addOperand(Inst.getOperand(1));
1046 TmpInst.addOperand(MCOperand::CreateImm(N));
1047 TmpInst.addOperand(MCOperand::CreateImm(B - N));
1054 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1055 OperandVector &Operands,
1056 MCStreamer &Out, uint64_t &ErrorInfo,
1057 bool MatchingInlineAsm) {
1060 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1063 // Post-process instructions (typically extended mnemonics)
1064 ProcessInstruction(Inst, Operands);
1066 Out.EmitInstruction(Inst, STI);
1068 case Match_MissingFeature:
1069 return Error(IDLoc, "instruction use requires an option to be enabled");
1070 case Match_MnemonicFail:
1071 return Error(IDLoc, "unrecognized instruction mnemonic");
1072 case Match_InvalidOperand: {
1073 SMLoc ErrorLoc = IDLoc;
1074 if (ErrorInfo != ~0ULL) {
1075 if (ErrorInfo >= Operands.size())
1076 return Error(IDLoc, "too few operands for instruction");
1078 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1079 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1082 return Error(ErrorLoc, "invalid operand for instruction");
1086 llvm_unreachable("Implement any new match types added!");
1090 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1091 if (Tok.is(AsmToken::Identifier)) {
1092 StringRef Name = Tok.getString();
1094 if (Name.equals_lower("lr")) {
1095 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1098 } else if (Name.equals_lower("ctr")) {
1099 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1102 } else if (Name.equals_lower("vrsave")) {
1103 RegNo = PPC::VRSAVE;
1106 } else if (Name.startswith_lower("r") &&
1107 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1108 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1110 } else if (Name.startswith_lower("f") &&
1111 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1112 RegNo = FRegs[IntVal];
1114 } else if (Name.startswith_lower("v") &&
1115 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1116 RegNo = VRegs[IntVal];
1118 } else if (Name.startswith_lower("cr") &&
1119 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1120 RegNo = CRRegs[IntVal];
1129 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1130 const AsmToken &Tok = Parser.getTok();
1131 StartLoc = Tok.getLoc();
1132 EndLoc = Tok.getEndLoc();
1136 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1137 Parser.Lex(); // Eat identifier token.
1141 return Error(StartLoc, "invalid register name");
1144 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1145 /// the expression and check for VK_PPC_LO/HI/HA
1146 /// symbol variants. If all symbols with modifier use the same
1147 /// variant, return the corresponding PPCMCExpr::VariantKind,
1148 /// and a modified expression using the default symbol variant.
1149 /// Otherwise, return NULL.
1150 const MCExpr *PPCAsmParser::
1151 ExtractModifierFromExpr(const MCExpr *E,
1152 PPCMCExpr::VariantKind &Variant) {
1153 MCContext &Context = getParser().getContext();
1154 Variant = PPCMCExpr::VK_PPC_None;
1156 switch (E->getKind()) {
1157 case MCExpr::Target:
1158 case MCExpr::Constant:
1161 case MCExpr::SymbolRef: {
1162 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1164 switch (SRE->getKind()) {
1165 case MCSymbolRefExpr::VK_PPC_LO:
1166 Variant = PPCMCExpr::VK_PPC_LO;
1168 case MCSymbolRefExpr::VK_PPC_HI:
1169 Variant = PPCMCExpr::VK_PPC_HI;
1171 case MCSymbolRefExpr::VK_PPC_HA:
1172 Variant = PPCMCExpr::VK_PPC_HA;
1174 case MCSymbolRefExpr::VK_PPC_HIGHER:
1175 Variant = PPCMCExpr::VK_PPC_HIGHER;
1177 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1178 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1180 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1181 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1183 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1184 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1190 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1193 case MCExpr::Unary: {
1194 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1195 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1198 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1201 case MCExpr::Binary: {
1202 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1203 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1204 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1205 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1210 if (!LHS) LHS = BE->getLHS();
1211 if (!RHS) RHS = BE->getRHS();
1213 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1214 Variant = RHSVariant;
1215 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1216 Variant = LHSVariant;
1217 else if (LHSVariant == RHSVariant)
1218 Variant = LHSVariant;
1222 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1226 llvm_unreachable("Invalid expression kind!");
1229 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1230 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1231 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1232 /// FIXME: This is a hack.
1233 const MCExpr *PPCAsmParser::
1234 FixupVariantKind(const MCExpr *E) {
1235 MCContext &Context = getParser().getContext();
1237 switch (E->getKind()) {
1238 case MCExpr::Target:
1239 case MCExpr::Constant:
1242 case MCExpr::SymbolRef: {
1243 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1244 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1246 switch (SRE->getKind()) {
1247 case MCSymbolRefExpr::VK_TLSGD:
1248 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1250 case MCSymbolRefExpr::VK_TLSLD:
1251 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1256 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1259 case MCExpr::Unary: {
1260 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1261 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1262 if (Sub == UE->getSubExpr())
1264 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1267 case MCExpr::Binary: {
1268 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1269 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1270 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1271 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1273 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1277 llvm_unreachable("Invalid expression kind!");
1280 /// ParseExpression. This differs from the default "parseExpression" in that
1281 /// it handles modifiers.
1283 ParseExpression(const MCExpr *&EVal) {
1286 return ParseDarwinExpression(EVal);
1289 // Handle \code @l/@ha \endcode
1290 if (getParser().parseExpression(EVal))
1293 EVal = FixupVariantKind(EVal);
1295 PPCMCExpr::VariantKind Variant;
1296 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1298 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1303 /// ParseDarwinExpression. (MachO Platforms)
1304 /// This differs from the default "parseExpression" in that it handles detection
1305 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1306 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1307 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1308 /// for this to be done at a higher level.
1310 ParseDarwinExpression(const MCExpr *&EVal) {
1311 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1312 switch (getLexer().getKind()) {
1315 case AsmToken::Identifier:
1316 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1317 // something starting with any other char should be part of the
1318 // asm syntax. If handwritten asm includes an identifier like lo16,
1319 // then all bets are off - but no-one would do that, right?
1320 StringRef poss = Parser.getTok().getString();
1321 if (poss.equals_lower("lo16")) {
1322 Variant = PPCMCExpr::VK_PPC_LO;
1323 } else if (poss.equals_lower("hi16")) {
1324 Variant = PPCMCExpr::VK_PPC_HI;
1325 } else if (poss.equals_lower("ha16")) {
1326 Variant = PPCMCExpr::VK_PPC_HA;
1328 if (Variant != PPCMCExpr::VK_PPC_None) {
1329 Parser.Lex(); // Eat the xx16
1330 if (getLexer().isNot(AsmToken::LParen))
1331 return Error(Parser.getTok().getLoc(), "expected '('");
1332 Parser.Lex(); // Eat the '('
1337 if (getParser().parseExpression(EVal))
1340 if (Variant != PPCMCExpr::VK_PPC_None) {
1341 if (getLexer().isNot(AsmToken::RParen))
1342 return Error(Parser.getTok().getLoc(), "expected ')'");
1343 Parser.Lex(); // Eat the ')'
1344 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1350 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1352 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1353 SMLoc S = Parser.getTok().getLoc();
1354 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1357 // Attempt to parse the next token as an immediate
1358 switch (getLexer().getKind()) {
1359 // Special handling for register names. These are interpreted
1360 // as immediates corresponding to the register number.
1361 case AsmToken::Percent:
1362 Parser.Lex(); // Eat the '%'.
1365 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1366 Parser.Lex(); // Eat the identifier token.
1367 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1370 return Error(S, "invalid register name");
1372 case AsmToken::Identifier:
1373 // Note that non-register-name identifiers from the compiler will begin
1374 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1375 // identifiers like r31foo - so we fall through in the event that parsing
1376 // a register name fails.
1380 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1381 Parser.Lex(); // Eat the identifier token.
1382 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1386 // Fall-through to process non-register-name identifiers as expression.
1387 // All other expressions
1388 case AsmToken::LParen:
1389 case AsmToken::Plus:
1390 case AsmToken::Minus:
1391 case AsmToken::Integer:
1393 case AsmToken::Dollar:
1394 case AsmToken::Exclaim:
1395 case AsmToken::Tilde:
1396 if (!ParseExpression(EVal))
1400 return Error(S, "unknown operand");
1403 // Push the parsed operand into the list of operands
1404 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1406 // Check whether this is a TLS call expression
1407 bool TLSCall = false;
1408 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1409 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1411 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1412 const MCExpr *TLSSym;
1414 Parser.Lex(); // Eat the '('.
1415 S = Parser.getTok().getLoc();
1416 if (ParseExpression(TLSSym))
1417 return Error(S, "invalid TLS call expression");
1418 if (getLexer().isNot(AsmToken::RParen))
1419 return Error(Parser.getTok().getLoc(), "missing ')'");
1420 E = Parser.getTok().getLoc();
1421 Parser.Lex(); // Eat the ')'.
1423 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1426 // Otherwise, check for D-form memory operands
1427 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1428 Parser.Lex(); // Eat the '('.
1429 S = Parser.getTok().getLoc();
1432 switch (getLexer().getKind()) {
1433 case AsmToken::Percent:
1434 Parser.Lex(); // Eat the '%'.
1436 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1437 return Error(S, "invalid register name");
1438 Parser.Lex(); // Eat the identifier token.
1441 case AsmToken::Integer:
1443 if (getParser().parseAbsoluteExpression(IntVal) ||
1444 IntVal < 0 || IntVal > 31)
1445 return Error(S, "invalid register number");
1447 return Error(S, "unexpected integer value");
1451 case AsmToken::Identifier:
1454 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1455 Parser.Lex(); // Eat the identifier token.
1462 return Error(S, "invalid memory operand");
1465 if (getLexer().isNot(AsmToken::RParen))
1466 return Error(Parser.getTok().getLoc(), "missing ')'");
1467 E = Parser.getTok().getLoc();
1468 Parser.Lex(); // Eat the ')'.
1470 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1476 /// Parse an instruction mnemonic followed by its operands.
1477 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1478 SMLoc NameLoc, OperandVector &Operands) {
1479 // The first operand is the token for the instruction name.
1480 // If the next character is a '+' or '-', we need to add it to the
1481 // instruction name, to match what TableGen is doing.
1482 std::string NewOpcode;
1483 if (getLexer().is(AsmToken::Plus)) {
1489 if (getLexer().is(AsmToken::Minus)) {
1495 // If the instruction ends in a '.', we need to create a separate
1496 // token for it, to match what TableGen is doing.
1497 size_t Dot = Name.find('.');
1498 StringRef Mnemonic = Name.slice(0, Dot);
1499 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1501 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1503 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1504 if (Dot != StringRef::npos) {
1505 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1506 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1507 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1509 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1511 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1514 // If there are no more operands then finish
1515 if (getLexer().is(AsmToken::EndOfStatement))
1518 // Parse the first operand
1519 if (ParseOperand(Operands))
1522 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1523 getLexer().is(AsmToken::Comma)) {
1524 // Consume the comma token
1527 // Parse the next operand
1528 if (ParseOperand(Operands))
1535 /// ParseDirective parses the PPC specific directives
1536 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1537 StringRef IDVal = DirectiveID.getIdentifier();
1539 if (IDVal == ".word")
1540 return ParseDirectiveWord(2, DirectiveID.getLoc());
1541 if (IDVal == ".llong")
1542 return ParseDirectiveWord(8, DirectiveID.getLoc());
1544 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1545 if (IDVal == ".machine")
1546 return ParseDirectiveMachine(DirectiveID.getLoc());
1547 if (IDVal == ".abiversion")
1548 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1549 if (IDVal == ".localentry")
1550 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1552 if (IDVal == ".machine")
1553 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1558 /// ParseDirectiveWord
1559 /// ::= .word [ expression (, expression)* ]
1560 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1561 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1563 const MCExpr *Value;
1564 if (getParser().parseExpression(Value))
1567 getParser().getStreamer().EmitValue(Value, Size);
1569 if (getLexer().is(AsmToken::EndOfStatement))
1572 if (getLexer().isNot(AsmToken::Comma))
1573 return Error(L, "unexpected token in directive");
1582 /// ParseDirectiveTC
1583 /// ::= .tc [ symbol (, expression)* ]
1584 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1585 // Skip TC symbol, which is only used with XCOFF.
1586 while (getLexer().isNot(AsmToken::EndOfStatement)
1587 && getLexer().isNot(AsmToken::Comma))
1589 if (getLexer().isNot(AsmToken::Comma)) {
1590 Error(L, "unexpected token in directive");
1595 // Align to word size.
1596 getParser().getStreamer().EmitValueToAlignment(Size);
1598 // Emit expressions.
1599 return ParseDirectiveWord(Size, L);
1602 /// ParseDirectiveMachine (ELF platforms)
1603 /// ::= .machine [ cpu | "push" | "pop" ]
1604 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1605 if (getLexer().isNot(AsmToken::Identifier) &&
1606 getLexer().isNot(AsmToken::String)) {
1607 Error(L, "unexpected token in directive");
1611 StringRef CPU = Parser.getTok().getIdentifier();
1614 // FIXME: Right now, the parser always allows any available
1615 // instruction, so the .machine directive is not useful.
1616 // Implement ".machine any" (by doing nothing) for the benefit
1617 // of existing assembler code. Likewise, we can then implement
1618 // ".machine push" and ".machine pop" as no-op.
1619 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1620 Error(L, "unrecognized machine type");
1624 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1625 Error(L, "unexpected token in directive");
1628 PPCTargetStreamer &TStreamer =
1629 *static_cast<PPCTargetStreamer *>(
1630 getParser().getStreamer().getTargetStreamer());
1631 TStreamer.emitMachine(CPU);
1636 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1637 /// ::= .machine cpu-identifier
1638 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1639 if (getLexer().isNot(AsmToken::Identifier) &&
1640 getLexer().isNot(AsmToken::String)) {
1641 Error(L, "unexpected token in directive");
1645 StringRef CPU = Parser.getTok().getIdentifier();
1648 // FIXME: this is only the 'default' set of cpu variants.
1649 // However we don't act on this information at present, this is simply
1650 // allowing parsing to proceed with minimal sanity checking.
1651 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1652 Error(L, "unrecognized cpu type");
1656 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1657 Error(L, "wrong cpu type specified for 64bit");
1660 if (!isPPC64() && CPU == "ppc64") {
1661 Error(L, "wrong cpu type specified for 32bit");
1665 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1666 Error(L, "unexpected token in directive");
1673 /// ParseDirectiveAbiVersion
1674 /// ::= .abiversion constant-expression
1675 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1677 if (getParser().parseAbsoluteExpression(AbiVersion)){
1678 Error(L, "expected constant expression");
1681 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1682 Error(L, "unexpected token in directive");
1686 PPCTargetStreamer &TStreamer =
1687 *static_cast<PPCTargetStreamer *>(
1688 getParser().getStreamer().getTargetStreamer());
1689 TStreamer.emitAbiVersion(AbiVersion);
1694 /// ParseDirectiveLocalEntry
1695 /// ::= .localentry symbol, expression
1696 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1698 if (getParser().parseIdentifier(Name)) {
1699 Error(L, "expected identifier in directive");
1702 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1704 if (getLexer().isNot(AsmToken::Comma)) {
1705 Error(L, "unexpected token in directive");
1711 if (getParser().parseExpression(Expr)) {
1712 Error(L, "expected expression");
1716 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1717 Error(L, "unexpected token in directive");
1721 PPCTargetStreamer &TStreamer =
1722 *static_cast<PPCTargetStreamer *>(
1723 getParser().getStreamer().getTargetStreamer());
1724 TStreamer.emitLocalEntry(Sym, Expr);
1731 /// Force static initialization.
1732 extern "C" void LLVMInitializePowerPCAsmParser() {
1733 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1734 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1735 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1738 #define GET_REGISTER_MATCHER
1739 #define GET_MATCHER_IMPLEMENTATION
1740 #include "PPCGenAsmMatcher.inc"
1742 // Define this matcher function after the auto-generated include so we
1743 // have the match class enum definitions.
1744 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1746 // If the kind is a token for a literal immediate, check if our asm
1747 // operand matches. This is for InstAliases which have a fixed-value
1748 // immediate in the syntax.
1751 case MCK_0: ImmVal = 0; break;
1752 case MCK_1: ImmVal = 1; break;
1753 case MCK_2: ImmVal = 2; break;
1754 case MCK_3: ImmVal = 3; break;
1755 case MCK_4: ImmVal = 4; break;
1756 case MCK_5: ImmVal = 5; break;
1757 case MCK_6: ImmVal = 6; break;
1758 case MCK_7: ImmVal = 7; break;
1759 default: return Match_InvalidOperand;
1762 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1763 if (Op.isImm() && Op.getImm() == ImmVal)
1764 return Match_Success;
1766 return Match_InvalidOperand;
1770 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1771 MCSymbolRefExpr::VariantKind Variant,
1774 case MCSymbolRefExpr::VK_PPC_LO:
1775 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1776 case MCSymbolRefExpr::VK_PPC_HI:
1777 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1778 case MCSymbolRefExpr::VK_PPC_HA:
1779 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1780 case MCSymbolRefExpr::VK_PPC_HIGHER:
1781 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1782 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1783 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1784 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1785 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1786 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1787 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);