1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
34 static unsigned RRegs[32] = {
35 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42 PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 static unsigned RRegsNoR0[32] = {
46 PPC::R1, PPC::R2, PPC::R3,
47 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
48 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53 PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 static unsigned XRegs[32] = {
56 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
57 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
58 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
59 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63 PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 static unsigned XRegsNoX0[32] = {
67 PPC::X1, PPC::X2, PPC::X3,
68 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
69 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
70 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74 PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 static unsigned FRegs[32] = {
77 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84 PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 static unsigned VRegs[32] = {
87 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
88 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
89 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
90 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
91 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
92 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
93 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
94 PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 static unsigned CRBITRegs[32] = {
97 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
98 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
99 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
100 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
101 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
102 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
103 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
104 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
106 static unsigned CRRegs[8] = {
107 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
108 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
111 // Evaluate an expression containing condition register
112 // or condition register field symbols. Returns positive
113 // value on success, or -1 on error.
115 EvaluateCRExpr(const MCExpr *E) {
116 switch (E->getKind()) {
120 case MCExpr::Constant: {
121 int64_t Res = cast<MCConstantExpr>(E)->getValue();
122 return Res < 0 ? -1 : Res;
125 case MCExpr::SymbolRef: {
126 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
127 StringRef Name = SRE->getSymbol().getName();
129 if (Name == "lt") return 0;
130 if (Name == "gt") return 1;
131 if (Name == "eq") return 2;
132 if (Name == "so") return 3;
133 if (Name == "un") return 3;
135 if (Name == "cr0") return 0;
136 if (Name == "cr1") return 1;
137 if (Name == "cr2") return 2;
138 if (Name == "cr3") return 3;
139 if (Name == "cr4") return 4;
140 if (Name == "cr5") return 5;
141 if (Name == "cr6") return 6;
142 if (Name == "cr7") return 7;
150 case MCExpr::Binary: {
151 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
152 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
153 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
156 if (LHSVal < 0 || RHSVal < 0)
159 switch (BE->getOpcode()) {
161 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
162 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
165 return Res < 0 ? -1 : Res;
169 llvm_unreachable("Invalid expression kind!");
174 class PPCAsmParser : public MCTargetAsmParser {
175 MCSubtargetInfo &STI;
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
183 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
185 bool isPPC64() const { return IsPPC64; }
187 bool MatchRegisterName(const AsmToken &Tok,
188 unsigned &RegNo, int64_t &IntVal);
190 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
192 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
193 PPCMCExpr::VariantKind &Variant);
194 const MCExpr *FixupVariantKind(const MCExpr *E);
195 bool ParseExpression(const MCExpr *&EVal);
197 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
199 bool ParseDirectiveWord(unsigned Size, SMLoc L);
200 bool ParseDirectiveTC(unsigned Size, SMLoc L);
201 bool ParseDirectiveMachine(SMLoc L);
203 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
204 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
205 MCStreamer &Out, unsigned &ErrorInfo,
206 bool MatchingInlineAsm);
208 void ProcessInstruction(MCInst &Inst,
209 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
211 /// @name Auto-generated Match Functions
214 #define GET_ASSEMBLER_HEADER
215 #include "PPCGenAsmMatcher.inc"
221 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
222 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
223 // Check for 64-bit vs. 32-bit pointer mode.
224 Triple TheTriple(STI.getTargetTriple());
225 IsPPC64 = TheTriple.getArch() == Triple::ppc64;
226 // Initialize the set of available features.
227 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
230 virtual bool ParseInstruction(ParseInstructionInfo &Info,
231 StringRef Name, SMLoc NameLoc,
232 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
234 virtual bool ParseDirective(AsmToken DirectiveID);
236 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
239 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
241 struct PPCOperand : public MCParsedAsmOperand {
249 SMLoc StartLoc, EndLoc;
263 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
267 const MCSymbolRefExpr *Sym;
274 struct TLSRegOp TLSReg;
277 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
279 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
281 StartLoc = o.StartLoc;
300 /// getStartLoc - Get the location of the first token of this operand.
301 SMLoc getStartLoc() const { return StartLoc; }
303 /// getEndLoc - Get the location of the last token of this operand.
304 SMLoc getEndLoc() const { return EndLoc; }
306 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
307 bool isPPC64() const { return IsPPC64; }
309 int64_t getImm() const {
310 assert(Kind == Immediate && "Invalid access!");
314 const MCExpr *getExpr() const {
315 assert(Kind == Expression && "Invalid access!");
319 int64_t getExprCRVal() const {
320 assert(Kind == Expression && "Invalid access!");
324 const MCExpr *getTLSReg() const {
325 assert(Kind == TLSRegister && "Invalid access!");
329 unsigned getReg() const {
330 assert(isRegNumber() && "Invalid access!");
331 return (unsigned) Imm.Val;
334 unsigned getCCReg() const {
335 assert(isCCRegNumber() && "Invalid access!");
336 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
339 unsigned getCRBit() const {
340 assert(isCRBitNumber() && "Invalid access!");
341 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
344 unsigned getCRBitMask() const {
345 assert(isCRBitMask() && "Invalid access!");
346 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
349 bool isToken() const { return Kind == Token; }
350 bool isImm() const { return Kind == Immediate || Kind == Expression; }
351 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
352 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
353 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
354 bool isU16Imm() const { return Kind == Expression ||
355 (Kind == Immediate && isUInt<16>(getImm())); }
356 bool isS16Imm() const { return Kind == Expression ||
357 (Kind == Immediate && isInt<16>(getImm())); }
358 bool isS16ImmX4() const { return Kind == Expression ||
359 (Kind == Immediate && isInt<16>(getImm()) &&
360 (getImm() & 3) == 0); }
361 bool isS17Imm() const { return Kind == Expression ||
362 (Kind == Immediate && isInt<17>(getImm())); }
363 bool isTLSReg() const { return Kind == TLSRegister; }
364 bool isDirectBr() const { return Kind == Expression ||
365 (Kind == Immediate && isInt<26>(getImm()) &&
366 (getImm() & 3) == 0); }
367 bool isCondBr() const { return Kind == Expression ||
368 (Kind == Immediate && isInt<16>(getImm()) &&
369 (getImm() & 3) == 0); }
370 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
371 bool isCCRegNumber() const { return (Kind == Expression
372 && isUInt<3>(getExprCRVal())) ||
374 && isUInt<3>(getImm())); }
375 bool isCRBitNumber() const { return (Kind == Expression
376 && isUInt<5>(getExprCRVal())) ||
378 && isUInt<5>(getImm())); }
379 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
380 isPowerOf2_32(getImm()); }
381 bool isMem() const { return false; }
382 bool isReg() const { return false; }
384 void addRegOperands(MCInst &Inst, unsigned N) const {
385 llvm_unreachable("addRegOperands");
388 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
389 assert(N == 1 && "Invalid number of operands!");
390 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
393 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
394 assert(N == 1 && "Invalid number of operands!");
395 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
398 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
399 assert(N == 1 && "Invalid number of operands!");
400 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
403 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
404 assert(N == 1 && "Invalid number of operands!");
405 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
408 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
410 addRegG8RCOperands(Inst, N);
412 addRegGPRCOperands(Inst, N);
415 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
417 addRegG8RCNoX0Operands(Inst, N);
419 addRegGPRCNoR0Operands(Inst, N);
422 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
423 assert(N == 1 && "Invalid number of operands!");
424 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
427 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
428 assert(N == 1 && "Invalid number of operands!");
429 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
432 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
433 assert(N == 1 && "Invalid number of operands!");
434 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
437 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
438 assert(N == 1 && "Invalid number of operands!");
439 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
442 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
443 assert(N == 1 && "Invalid number of operands!");
444 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
447 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
448 assert(N == 1 && "Invalid number of operands!");
449 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
452 void addImmOperands(MCInst &Inst, unsigned N) const {
453 assert(N == 1 && "Invalid number of operands!");
454 if (Kind == Immediate)
455 Inst.addOperand(MCOperand::CreateImm(getImm()));
457 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
460 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
461 assert(N == 1 && "Invalid number of operands!");
462 if (Kind == Immediate)
463 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
465 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
468 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
469 assert(N == 1 && "Invalid number of operands!");
470 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
473 StringRef getToken() const {
474 assert(Kind == Token && "Invalid access!");
475 return StringRef(Tok.Data, Tok.Length);
478 virtual void print(raw_ostream &OS) const;
480 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
481 PPCOperand *Op = new PPCOperand(Token);
482 Op->Tok.Data = Str.data();
483 Op->Tok.Length = Str.size();
486 Op->IsPPC64 = IsPPC64;
490 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
491 PPCOperand *Op = new PPCOperand(Immediate);
495 Op->IsPPC64 = IsPPC64;
499 static PPCOperand *CreateExpr(const MCExpr *Val,
500 SMLoc S, SMLoc E, bool IsPPC64) {
501 PPCOperand *Op = new PPCOperand(Expression);
503 Op->Expr.CRVal = EvaluateCRExpr(Val);
506 Op->IsPPC64 = IsPPC64;
510 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
511 SMLoc S, SMLoc E, bool IsPPC64) {
512 PPCOperand *Op = new PPCOperand(TLSRegister);
513 Op->TLSReg.Sym = Sym;
516 Op->IsPPC64 = IsPPC64;
520 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
521 SMLoc S, SMLoc E, bool IsPPC64) {
522 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
523 return CreateImm(CE->getValue(), S, E, IsPPC64);
525 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
526 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
527 return CreateTLSReg(SRE, S, E, IsPPC64);
529 return CreateExpr(Val, S, E, IsPPC64);
533 } // end anonymous namespace.
535 void PPCOperand::print(raw_ostream &OS) const {
538 OS << "'" << getToken() << "'";
544 getExpr()->print(OS);
547 getTLSReg()->print(OS);
554 ProcessInstruction(MCInst &Inst,
555 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
556 int Opcode = Inst.getOpcode();
560 TmpInst.setOpcode(PPC::LA);
561 TmpInst.addOperand(Inst.getOperand(0));
562 TmpInst.addOperand(Inst.getOperand(2));
563 TmpInst.addOperand(Inst.getOperand(1));
569 int64_t N = Inst.getOperand(2).getImm();
570 TmpInst.setOpcode(PPC::ADDI);
571 TmpInst.addOperand(Inst.getOperand(0));
572 TmpInst.addOperand(Inst.getOperand(1));
573 TmpInst.addOperand(MCOperand::CreateImm(-N));
579 int64_t N = Inst.getOperand(2).getImm();
580 TmpInst.setOpcode(PPC::ADDIS);
581 TmpInst.addOperand(Inst.getOperand(0));
582 TmpInst.addOperand(Inst.getOperand(1));
583 TmpInst.addOperand(MCOperand::CreateImm(-N));
589 int64_t N = Inst.getOperand(2).getImm();
590 TmpInst.setOpcode(PPC::ADDIC);
591 TmpInst.addOperand(Inst.getOperand(0));
592 TmpInst.addOperand(Inst.getOperand(1));
593 TmpInst.addOperand(MCOperand::CreateImm(-N));
599 int64_t N = Inst.getOperand(2).getImm();
600 TmpInst.setOpcode(PPC::ADDICo);
601 TmpInst.addOperand(Inst.getOperand(0));
602 TmpInst.addOperand(Inst.getOperand(1));
603 TmpInst.addOperand(MCOperand::CreateImm(-N));
610 int64_t N = Inst.getOperand(2).getImm();
611 int64_t B = Inst.getOperand(3).getImm();
612 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
613 TmpInst.addOperand(Inst.getOperand(0));
614 TmpInst.addOperand(Inst.getOperand(1));
615 TmpInst.addOperand(MCOperand::CreateImm(B));
616 TmpInst.addOperand(MCOperand::CreateImm(0));
617 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
624 int64_t N = Inst.getOperand(2).getImm();
625 int64_t B = Inst.getOperand(3).getImm();
626 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
627 TmpInst.addOperand(Inst.getOperand(0));
628 TmpInst.addOperand(Inst.getOperand(1));
629 TmpInst.addOperand(MCOperand::CreateImm(B + N));
630 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
631 TmpInst.addOperand(MCOperand::CreateImm(31));
638 int64_t N = Inst.getOperand(2).getImm();
639 int64_t B = Inst.getOperand(3).getImm();
640 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
641 TmpInst.addOperand(Inst.getOperand(0));
642 TmpInst.addOperand(Inst.getOperand(0));
643 TmpInst.addOperand(Inst.getOperand(1));
644 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
645 TmpInst.addOperand(MCOperand::CreateImm(B));
646 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
653 int64_t N = Inst.getOperand(2).getImm();
654 int64_t B = Inst.getOperand(3).getImm();
655 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
656 TmpInst.addOperand(Inst.getOperand(0));
657 TmpInst.addOperand(Inst.getOperand(0));
658 TmpInst.addOperand(Inst.getOperand(1));
659 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
660 TmpInst.addOperand(MCOperand::CreateImm(B));
661 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
668 int64_t N = Inst.getOperand(2).getImm();
669 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
670 TmpInst.addOperand(Inst.getOperand(0));
671 TmpInst.addOperand(Inst.getOperand(1));
672 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
673 TmpInst.addOperand(MCOperand::CreateImm(0));
674 TmpInst.addOperand(MCOperand::CreateImm(31));
681 int64_t N = Inst.getOperand(2).getImm();
682 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
683 TmpInst.addOperand(Inst.getOperand(0));
684 TmpInst.addOperand(Inst.getOperand(1));
685 TmpInst.addOperand(MCOperand::CreateImm(N));
686 TmpInst.addOperand(MCOperand::CreateImm(0));
687 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
694 int64_t N = Inst.getOperand(2).getImm();
695 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
696 TmpInst.addOperand(Inst.getOperand(0));
697 TmpInst.addOperand(Inst.getOperand(1));
698 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
699 TmpInst.addOperand(MCOperand::CreateImm(N));
700 TmpInst.addOperand(MCOperand::CreateImm(31));
707 int64_t N = Inst.getOperand(2).getImm();
708 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
709 TmpInst.addOperand(Inst.getOperand(0));
710 TmpInst.addOperand(Inst.getOperand(1));
711 TmpInst.addOperand(MCOperand::CreateImm(0));
712 TmpInst.addOperand(MCOperand::CreateImm(0));
713 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
718 case PPC::CLRLSLWIo: {
720 int64_t B = Inst.getOperand(2).getImm();
721 int64_t N = Inst.getOperand(3).getImm();
722 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
723 TmpInst.addOperand(Inst.getOperand(0));
724 TmpInst.addOperand(Inst.getOperand(1));
725 TmpInst.addOperand(MCOperand::CreateImm(N));
726 TmpInst.addOperand(MCOperand::CreateImm(B - N));
727 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
734 int64_t N = Inst.getOperand(2).getImm();
735 int64_t B = Inst.getOperand(3).getImm();
736 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
737 TmpInst.addOperand(Inst.getOperand(0));
738 TmpInst.addOperand(Inst.getOperand(1));
739 TmpInst.addOperand(MCOperand::CreateImm(B));
740 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
747 int64_t N = Inst.getOperand(2).getImm();
748 int64_t B = Inst.getOperand(3).getImm();
749 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
750 TmpInst.addOperand(Inst.getOperand(0));
751 TmpInst.addOperand(Inst.getOperand(1));
752 TmpInst.addOperand(MCOperand::CreateImm(B + N));
753 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
760 int64_t N = Inst.getOperand(2).getImm();
761 int64_t B = Inst.getOperand(3).getImm();
762 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
763 TmpInst.addOperand(Inst.getOperand(0));
764 TmpInst.addOperand(Inst.getOperand(0));
765 TmpInst.addOperand(Inst.getOperand(1));
766 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
767 TmpInst.addOperand(MCOperand::CreateImm(B));
774 int64_t N = Inst.getOperand(2).getImm();
775 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
776 TmpInst.addOperand(Inst.getOperand(0));
777 TmpInst.addOperand(Inst.getOperand(1));
778 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
779 TmpInst.addOperand(MCOperand::CreateImm(0));
786 int64_t N = Inst.getOperand(2).getImm();
787 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
788 TmpInst.addOperand(Inst.getOperand(0));
789 TmpInst.addOperand(Inst.getOperand(1));
790 TmpInst.addOperand(MCOperand::CreateImm(N));
791 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
798 int64_t N = Inst.getOperand(2).getImm();
799 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
800 TmpInst.addOperand(Inst.getOperand(0));
801 TmpInst.addOperand(Inst.getOperand(1));
802 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
803 TmpInst.addOperand(MCOperand::CreateImm(N));
810 int64_t N = Inst.getOperand(2).getImm();
811 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
812 TmpInst.addOperand(Inst.getOperand(0));
813 TmpInst.addOperand(Inst.getOperand(1));
814 TmpInst.addOperand(MCOperand::CreateImm(0));
815 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
820 case PPC::CLRLSLDIo: {
822 int64_t B = Inst.getOperand(2).getImm();
823 int64_t N = Inst.getOperand(3).getImm();
824 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
825 TmpInst.addOperand(Inst.getOperand(0));
826 TmpInst.addOperand(Inst.getOperand(1));
827 TmpInst.addOperand(MCOperand::CreateImm(N));
828 TmpInst.addOperand(MCOperand::CreateImm(B - N));
836 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
837 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
838 MCStreamer &Out, unsigned &ErrorInfo,
839 bool MatchingInlineAsm) {
842 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
845 // Post-process instructions (typically extended mnemonics)
846 ProcessInstruction(Inst, Operands);
848 Out.EmitInstruction(Inst);
850 case Match_MissingFeature:
851 return Error(IDLoc, "instruction use requires an option to be enabled");
852 case Match_MnemonicFail:
853 return Error(IDLoc, "unrecognized instruction mnemonic");
854 case Match_InvalidOperand: {
855 SMLoc ErrorLoc = IDLoc;
856 if (ErrorInfo != ~0U) {
857 if (ErrorInfo >= Operands.size())
858 return Error(IDLoc, "too few operands for instruction");
860 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
861 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
864 return Error(ErrorLoc, "invalid operand for instruction");
868 llvm_unreachable("Implement any new match types added!");
872 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
873 if (Tok.is(AsmToken::Identifier)) {
874 StringRef Name = Tok.getString();
876 if (Name.equals_lower("lr")) {
877 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
880 } else if (Name.equals_lower("ctr")) {
881 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
884 } else if (Name.equals_lower("vrsave")) {
888 } else if (Name.substr(0, 1).equals_lower("r") &&
889 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
890 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
892 } else if (Name.substr(0, 1).equals_lower("f") &&
893 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
894 RegNo = FRegs[IntVal];
896 } else if (Name.substr(0, 1).equals_lower("v") &&
897 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
898 RegNo = VRegs[IntVal];
900 } else if (Name.substr(0, 2).equals_lower("cr") &&
901 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
902 RegNo = CRRegs[IntVal];
911 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
912 const AsmToken &Tok = Parser.getTok();
913 StartLoc = Tok.getLoc();
914 EndLoc = Tok.getEndLoc();
918 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
919 Parser.Lex(); // Eat identifier token.
923 return Error(StartLoc, "invalid register name");
926 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
927 /// the expression and check for VK_PPC_LO/HI/HA
928 /// symbol variants. If all symbols with modifier use the same
929 /// variant, return the corresponding PPCMCExpr::VariantKind,
930 /// and a modified expression using the default symbol variant.
931 /// Otherwise, return NULL.
932 const MCExpr *PPCAsmParser::
933 ExtractModifierFromExpr(const MCExpr *E,
934 PPCMCExpr::VariantKind &Variant) {
935 MCContext &Context = getParser().getContext();
936 Variant = PPCMCExpr::VK_PPC_None;
938 switch (E->getKind()) {
940 case MCExpr::Constant:
943 case MCExpr::SymbolRef: {
944 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
946 switch (SRE->getKind()) {
947 case MCSymbolRefExpr::VK_PPC_LO:
948 Variant = PPCMCExpr::VK_PPC_LO;
950 case MCSymbolRefExpr::VK_PPC_HI:
951 Variant = PPCMCExpr::VK_PPC_HI;
953 case MCSymbolRefExpr::VK_PPC_HA:
954 Variant = PPCMCExpr::VK_PPC_HA;
956 case MCSymbolRefExpr::VK_PPC_HIGHER:
957 Variant = PPCMCExpr::VK_PPC_HIGHER;
959 case MCSymbolRefExpr::VK_PPC_HIGHERA:
960 Variant = PPCMCExpr::VK_PPC_HIGHERA;
962 case MCSymbolRefExpr::VK_PPC_HIGHEST:
963 Variant = PPCMCExpr::VK_PPC_HIGHEST;
965 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
966 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
972 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
975 case MCExpr::Unary: {
976 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
977 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
980 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
983 case MCExpr::Binary: {
984 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
985 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
986 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
987 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
992 if (!LHS) LHS = BE->getLHS();
993 if (!RHS) RHS = BE->getRHS();
995 if (LHSVariant == PPCMCExpr::VK_PPC_None)
996 Variant = RHSVariant;
997 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
998 Variant = LHSVariant;
999 else if (LHSVariant == RHSVariant)
1000 Variant = LHSVariant;
1004 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1008 llvm_unreachable("Invalid expression kind!");
1011 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1012 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1013 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1014 /// FIXME: This is a hack.
1015 const MCExpr *PPCAsmParser::
1016 FixupVariantKind(const MCExpr *E) {
1017 MCContext &Context = getParser().getContext();
1019 switch (E->getKind()) {
1020 case MCExpr::Target:
1021 case MCExpr::Constant:
1024 case MCExpr::SymbolRef: {
1025 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1026 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1028 switch (SRE->getKind()) {
1029 case MCSymbolRefExpr::VK_TLSGD:
1030 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1032 case MCSymbolRefExpr::VK_TLSLD:
1033 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1038 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1041 case MCExpr::Unary: {
1042 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1043 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1044 if (Sub == UE->getSubExpr())
1046 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1049 case MCExpr::Binary: {
1050 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1051 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1052 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1053 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1055 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1059 llvm_unreachable("Invalid expression kind!");
1062 /// Parse an expression. This differs from the default "parseExpression"
1063 /// in that it handles complex \code @l/@ha \endcode modifiers.
1065 ParseExpression(const MCExpr *&EVal) {
1066 if (getParser().parseExpression(EVal))
1069 EVal = FixupVariantKind(EVal);
1071 PPCMCExpr::VariantKind Variant;
1072 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1074 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1080 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1081 SMLoc S = Parser.getTok().getLoc();
1082 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1086 // Attempt to parse the next token as an immediate
1087 switch (getLexer().getKind()) {
1088 // Special handling for register names. These are interpreted
1089 // as immediates corresponding to the register number.
1090 case AsmToken::Percent:
1091 Parser.Lex(); // Eat the '%'.
1094 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1095 Parser.Lex(); // Eat the identifier token.
1096 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1097 Operands.push_back(Op);
1100 return Error(S, "invalid register name");
1102 // All other expressions
1103 case AsmToken::LParen:
1104 case AsmToken::Plus:
1105 case AsmToken::Minus:
1106 case AsmToken::Integer:
1107 case AsmToken::Identifier:
1109 case AsmToken::Dollar:
1110 if (!ParseExpression(EVal))
1114 return Error(S, "unknown operand");
1117 // Push the parsed operand into the list of operands
1118 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1119 Operands.push_back(Op);
1121 // Check whether this is a TLS call expression
1122 bool TLSCall = false;
1123 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1124 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1126 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1127 const MCExpr *TLSSym;
1129 Parser.Lex(); // Eat the '('.
1130 S = Parser.getTok().getLoc();
1131 if (ParseExpression(TLSSym))
1132 return Error(S, "invalid TLS call expression");
1133 if (getLexer().isNot(AsmToken::RParen))
1134 return Error(Parser.getTok().getLoc(), "missing ')'");
1135 E = Parser.getTok().getLoc();
1136 Parser.Lex(); // Eat the ')'.
1138 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1139 Operands.push_back(Op);
1142 // Otherwise, check for D-form memory operands
1143 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1144 Parser.Lex(); // Eat the '('.
1145 S = Parser.getTok().getLoc();
1148 switch (getLexer().getKind()) {
1149 case AsmToken::Percent:
1150 Parser.Lex(); // Eat the '%'.
1152 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1153 return Error(S, "invalid register name");
1154 Parser.Lex(); // Eat the identifier token.
1157 case AsmToken::Integer:
1158 if (getParser().parseAbsoluteExpression(IntVal) ||
1159 IntVal < 0 || IntVal > 31)
1160 return Error(S, "invalid register number");
1164 return Error(S, "invalid memory operand");
1167 if (getLexer().isNot(AsmToken::RParen))
1168 return Error(Parser.getTok().getLoc(), "missing ')'");
1169 E = Parser.getTok().getLoc();
1170 Parser.Lex(); // Eat the ')'.
1172 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1173 Operands.push_back(Op);
1179 /// Parse an instruction mnemonic followed by its operands.
1181 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1182 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1183 // The first operand is the token for the instruction name.
1184 // If the next character is a '+' or '-', we need to add it to the
1185 // instruction name, to match what TableGen is doing.
1186 if (getLexer().is(AsmToken::Plus)) {
1188 char *NewOpcode = new char[Name.size() + 1];
1189 memcpy(NewOpcode, Name.data(), Name.size());
1190 NewOpcode[Name.size()] = '+';
1191 Name = StringRef(NewOpcode, Name.size() + 1);
1193 if (getLexer().is(AsmToken::Minus)) {
1195 char *NewOpcode = new char[Name.size() + 1];
1196 memcpy(NewOpcode, Name.data(), Name.size());
1197 NewOpcode[Name.size()] = '-';
1198 Name = StringRef(NewOpcode, Name.size() + 1);
1200 // If the instruction ends in a '.', we need to create a separate
1201 // token for it, to match what TableGen is doing.
1202 size_t Dot = Name.find('.');
1203 StringRef Mnemonic = Name.slice(0, Dot);
1204 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1205 if (Dot != StringRef::npos) {
1206 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1207 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1208 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1211 // If there are no more operands then finish
1212 if (getLexer().is(AsmToken::EndOfStatement))
1215 // Parse the first operand
1216 if (ParseOperand(Operands))
1219 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1220 getLexer().is(AsmToken::Comma)) {
1221 // Consume the comma token
1224 // Parse the next operand
1225 if (ParseOperand(Operands))
1232 /// ParseDirective parses the PPC specific directives
1233 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1234 StringRef IDVal = DirectiveID.getIdentifier();
1235 if (IDVal == ".word")
1236 return ParseDirectiveWord(2, DirectiveID.getLoc());
1237 if (IDVal == ".llong")
1238 return ParseDirectiveWord(8, DirectiveID.getLoc());
1240 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1241 if (IDVal == ".machine")
1242 return ParseDirectiveMachine(DirectiveID.getLoc());
1246 /// ParseDirectiveWord
1247 /// ::= .word [ expression (, expression)* ]
1248 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1249 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1251 const MCExpr *Value;
1252 if (getParser().parseExpression(Value))
1255 getParser().getStreamer().EmitValue(Value, Size);
1257 if (getLexer().is(AsmToken::EndOfStatement))
1260 if (getLexer().isNot(AsmToken::Comma))
1261 return Error(L, "unexpected token in directive");
1270 /// ParseDirectiveTC
1271 /// ::= .tc [ symbol (, expression)* ]
1272 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1273 // Skip TC symbol, which is only used with XCOFF.
1274 while (getLexer().isNot(AsmToken::EndOfStatement)
1275 && getLexer().isNot(AsmToken::Comma))
1277 if (getLexer().isNot(AsmToken::Comma))
1278 return Error(L, "unexpected token in directive");
1281 // Align to word size.
1282 getParser().getStreamer().EmitValueToAlignment(Size);
1284 // Emit expressions.
1285 return ParseDirectiveWord(Size, L);
1288 /// ParseDirectiveMachine
1289 /// ::= .machine [ cpu | "push" | "pop" ]
1290 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1291 if (getLexer().isNot(AsmToken::Identifier) &&
1292 getLexer().isNot(AsmToken::String))
1293 return Error(L, "unexpected token in directive");
1295 StringRef CPU = Parser.getTok().getIdentifier();
1298 // FIXME: Right now, the parser always allows any available
1299 // instruction, so the .machine directive is not useful.
1300 // Implement ".machine any" (by doing nothing) for the benefit
1301 // of existing assembler code. Likewise, we can then implement
1302 // ".machine push" and ".machine pop" as no-op.
1303 if (CPU != "any" && CPU != "push" && CPU != "pop")
1304 return Error(L, "unrecognized machine type");
1306 if (getLexer().isNot(AsmToken::EndOfStatement))
1307 return Error(L, "unexpected token in directive");
1312 /// Force static initialization.
1313 extern "C" void LLVMInitializePowerPCAsmParser() {
1314 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1315 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1318 #define GET_REGISTER_MATCHER
1319 #define GET_MATCHER_IMPLEMENTATION
1320 #include "PPCGenAsmMatcher.inc"
1322 // Define this matcher function after the auto-generated include so we
1323 // have the match class enum definitions.
1324 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1326 // If the kind is a token for a literal immediate, check if our asm
1327 // operand matches. This is for InstAliases which have a fixed-value
1328 // immediate in the syntax.
1331 case MCK_0: ImmVal = 0; break;
1332 case MCK_1: ImmVal = 1; break;
1333 default: return Match_InvalidOperand;
1336 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1337 if (Op->isImm() && Op->getImm() == ImmVal)
1338 return Match_Success;
1340 return Match_InvalidOperand;