1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
37 static unsigned RRegs[32] = {
38 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
39 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
40 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
41 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
42 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
43 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
44 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
45 PPC::R28, PPC::R29, PPC::R30, PPC::R31
47 static unsigned RRegsNoR0[32] = {
49 PPC::R1, PPC::R2, PPC::R3,
50 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
51 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
52 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
53 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
54 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
55 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
56 PPC::R28, PPC::R29, PPC::R30, PPC::R31
58 static unsigned XRegs[32] = {
59 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
60 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
61 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
62 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
63 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
64 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
65 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
66 PPC::X28, PPC::X29, PPC::X30, PPC::X31
68 static unsigned XRegsNoX0[32] = {
70 PPC::X1, PPC::X2, PPC::X3,
71 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
72 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
73 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
74 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
75 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
76 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
77 PPC::X28, PPC::X29, PPC::X30, PPC::X31
79 static unsigned FRegs[32] = {
80 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
81 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
82 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
83 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
84 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
85 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
86 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
87 PPC::F28, PPC::F29, PPC::F30, PPC::F31
89 static unsigned VRegs[32] = {
90 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
91 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
92 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
93 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
94 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
95 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
96 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
97 PPC::V28, PPC::V29, PPC::V30, PPC::V31
99 static unsigned VSRegs[64] = {
100 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
101 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
102 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
103 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
104 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
105 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
106 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
107 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
109 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
110 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
111 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
112 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
113 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
114 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
115 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
116 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
118 static unsigned VSFRegs[64] = {
119 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
120 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
121 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
122 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
123 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
124 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
125 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
126 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
128 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
129 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
130 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
131 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
132 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
133 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
134 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
135 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
137 static unsigned CRBITRegs[32] = {
138 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
139 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
140 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
141 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
142 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
143 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
144 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
145 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
147 static unsigned CRRegs[8] = {
148 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
149 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
152 // Evaluate an expression containing condition register
153 // or condition register field symbols. Returns positive
154 // value on success, or -1 on error.
156 EvaluateCRExpr(const MCExpr *E) {
157 switch (E->getKind()) {
161 case MCExpr::Constant: {
162 int64_t Res = cast<MCConstantExpr>(E)->getValue();
163 return Res < 0 ? -1 : Res;
166 case MCExpr::SymbolRef: {
167 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
168 StringRef Name = SRE->getSymbol().getName();
170 if (Name == "lt") return 0;
171 if (Name == "gt") return 1;
172 if (Name == "eq") return 2;
173 if (Name == "so") return 3;
174 if (Name == "un") return 3;
176 if (Name == "cr0") return 0;
177 if (Name == "cr1") return 1;
178 if (Name == "cr2") return 2;
179 if (Name == "cr3") return 3;
180 if (Name == "cr4") return 4;
181 if (Name == "cr5") return 5;
182 if (Name == "cr6") return 6;
183 if (Name == "cr7") return 7;
191 case MCExpr::Binary: {
192 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
193 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
194 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
197 if (LHSVal < 0 || RHSVal < 0)
200 switch (BE->getOpcode()) {
202 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
203 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
206 return Res < 0 ? -1 : Res;
210 llvm_unreachable("Invalid expression kind!");
215 class PPCAsmParser : public MCTargetAsmParser {
216 MCSubtargetInfo &STI;
218 const MCInstrInfo &MII;
222 MCAsmParser &getParser() const { return Parser; }
223 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
225 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
226 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
228 bool isPPC64() const { return IsPPC64; }
229 bool isDarwin() const { return IsDarwin; }
231 bool MatchRegisterName(const AsmToken &Tok,
232 unsigned &RegNo, int64_t &IntVal);
234 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
236 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
237 PPCMCExpr::VariantKind &Variant);
238 const MCExpr *FixupVariantKind(const MCExpr *E);
239 bool ParseExpression(const MCExpr *&EVal);
240 bool ParseDarwinExpression(const MCExpr *&EVal);
242 bool ParseOperand(OperandVector &Operands);
244 bool ParseDirectiveWord(unsigned Size, SMLoc L);
245 bool ParseDirectiveTC(unsigned Size, SMLoc L);
246 bool ParseDirectiveMachine(SMLoc L);
247 bool ParseDarwinDirectiveMachine(SMLoc L);
248 bool ParseDirectiveAbiVersion(SMLoc L);
249 bool ParseDirectiveLocalEntry(SMLoc L);
251 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
252 OperandVector &Operands, MCStreamer &Out,
254 bool MatchingInlineAsm) override;
256 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
258 /// @name Auto-generated Match Functions
261 #define GET_ASSEMBLER_HEADER
262 #include "PPCGenAsmMatcher.inc"
268 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
269 const MCInstrInfo &_MII,
270 const MCTargetOptions &Options)
271 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
272 // Check for 64-bit vs. 32-bit pointer mode.
273 Triple TheTriple(STI.getTargetTriple());
274 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
275 TheTriple.getArch() == Triple::ppc64le);
276 IsDarwin = TheTriple.isMacOSX();
277 // Initialize the set of available features.
278 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
281 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
282 SMLoc NameLoc, OperandVector &Operands) override;
284 bool ParseDirective(AsmToken DirectiveID) override;
286 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
287 unsigned Kind) override;
289 const MCExpr *applyModifierToExpr(const MCExpr *E,
290 MCSymbolRefExpr::VariantKind,
291 MCContext &Ctx) override;
294 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
296 struct PPCOperand : public MCParsedAsmOperand {
304 SMLoc StartLoc, EndLoc;
318 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
322 const MCSymbolRefExpr *Sym;
329 struct TLSRegOp TLSReg;
332 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
334 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
336 StartLoc = o.StartLoc;
355 /// getStartLoc - Get the location of the first token of this operand.
356 SMLoc getStartLoc() const override { return StartLoc; }
358 /// getEndLoc - Get the location of the last token of this operand.
359 SMLoc getEndLoc() const override { return EndLoc; }
361 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
362 bool isPPC64() const { return IsPPC64; }
364 int64_t getImm() const {
365 assert(Kind == Immediate && "Invalid access!");
369 const MCExpr *getExpr() const {
370 assert(Kind == Expression && "Invalid access!");
374 int64_t getExprCRVal() const {
375 assert(Kind == Expression && "Invalid access!");
379 const MCExpr *getTLSReg() const {
380 assert(Kind == TLSRegister && "Invalid access!");
384 unsigned getReg() const override {
385 assert(isRegNumber() && "Invalid access!");
386 return (unsigned) Imm.Val;
389 unsigned getVSReg() const {
390 assert(isVSRegNumber() && "Invalid access!");
391 return (unsigned) Imm.Val;
394 unsigned getCCReg() const {
395 assert(isCCRegNumber() && "Invalid access!");
396 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
399 unsigned getCRBit() const {
400 assert(isCRBitNumber() && "Invalid access!");
401 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
404 unsigned getCRBitMask() const {
405 assert(isCRBitMask() && "Invalid access!");
406 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
409 bool isToken() const override { return Kind == Token; }
410 bool isImm() const override { return Kind == Immediate || Kind == Expression; }
411 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
412 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
413 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
414 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
415 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
416 bool isU6ImmX2() const { return Kind == Immediate &&
417 isUInt<6>(getImm()) &&
418 (getImm() & 1) == 0; }
419 bool isU7ImmX4() const { return Kind == Immediate &&
420 isUInt<7>(getImm()) &&
421 (getImm() & 3) == 0; }
422 bool isU8ImmX8() const { return Kind == Immediate &&
423 isUInt<8>(getImm()) &&
424 (getImm() & 7) == 0; }
425 bool isU16Imm() const { return Kind == Expression ||
426 (Kind == Immediate && isUInt<16>(getImm())); }
427 bool isS16Imm() const { return Kind == Expression ||
428 (Kind == Immediate && isInt<16>(getImm())); }
429 bool isS16ImmX4() const { return Kind == Expression ||
430 (Kind == Immediate && isInt<16>(getImm()) &&
431 (getImm() & 3) == 0); }
432 bool isS17Imm() const { return Kind == Expression ||
433 (Kind == Immediate && isInt<17>(getImm())); }
434 bool isTLSReg() const { return Kind == TLSRegister; }
435 bool isDirectBr() const { return Kind == Expression ||
436 (Kind == Immediate && isInt<26>(getImm()) &&
437 (getImm() & 3) == 0); }
438 bool isCondBr() const { return Kind == Expression ||
439 (Kind == Immediate && isInt<16>(getImm()) &&
440 (getImm() & 3) == 0); }
441 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
442 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
443 bool isCCRegNumber() const { return (Kind == Expression
444 && isUInt<3>(getExprCRVal())) ||
446 && isUInt<3>(getImm())); }
447 bool isCRBitNumber() const { return (Kind == Expression
448 && isUInt<5>(getExprCRVal())) ||
450 && isUInt<5>(getImm())); }
451 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
452 isPowerOf2_32(getImm()); }
453 bool isMem() const override { return false; }
454 bool isReg() const override { return false; }
456 void addRegOperands(MCInst &Inst, unsigned N) const {
457 llvm_unreachable("addRegOperands");
460 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
461 assert(N == 1 && "Invalid number of operands!");
462 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
465 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
466 assert(N == 1 && "Invalid number of operands!");
467 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
470 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
471 assert(N == 1 && "Invalid number of operands!");
472 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
475 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
476 assert(N == 1 && "Invalid number of operands!");
477 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
480 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
482 addRegG8RCOperands(Inst, N);
484 addRegGPRCOperands(Inst, N);
487 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
489 addRegG8RCNoX0Operands(Inst, N);
491 addRegGPRCNoR0Operands(Inst, N);
494 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
495 assert(N == 1 && "Invalid number of operands!");
496 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
499 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
500 assert(N == 1 && "Invalid number of operands!");
501 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
504 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
505 assert(N == 1 && "Invalid number of operands!");
506 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
509 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
510 assert(N == 1 && "Invalid number of operands!");
511 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
514 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
515 assert(N == 1 && "Invalid number of operands!");
516 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
519 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
520 assert(N == 1 && "Invalid number of operands!");
521 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
524 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
525 assert(N == 1 && "Invalid number of operands!");
526 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
529 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
530 assert(N == 1 && "Invalid number of operands!");
531 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
534 void addImmOperands(MCInst &Inst, unsigned N) const {
535 assert(N == 1 && "Invalid number of operands!");
536 if (Kind == Immediate)
537 Inst.addOperand(MCOperand::CreateImm(getImm()));
539 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
542 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
543 assert(N == 1 && "Invalid number of operands!");
544 if (Kind == Immediate)
545 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
547 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
550 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
551 assert(N == 1 && "Invalid number of operands!");
552 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
555 StringRef getToken() const {
556 assert(Kind == Token && "Invalid access!");
557 return StringRef(Tok.Data, Tok.Length);
560 void print(raw_ostream &OS) const override;
562 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
564 auto Op = make_unique<PPCOperand>(Token);
565 Op->Tok.Data = Str.data();
566 Op->Tok.Length = Str.size();
569 Op->IsPPC64 = IsPPC64;
573 static std::unique_ptr<PPCOperand>
574 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
575 // Allocate extra memory for the string and copy it.
576 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
577 // deleter which will destroy them by simply using "delete", not correctly
578 // calling operator delete on this extra memory after calling the dtor
580 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
581 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
582 Op->Tok.Data = (const char *)(Op.get() + 1);
583 Op->Tok.Length = Str.size();
584 std::memcpy((void *)Op->Tok.Data, Str.data(), Str.size());
587 Op->IsPPC64 = IsPPC64;
591 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
593 auto Op = make_unique<PPCOperand>(Immediate);
597 Op->IsPPC64 = IsPPC64;
601 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
602 SMLoc E, bool IsPPC64) {
603 auto Op = make_unique<PPCOperand>(Expression);
605 Op->Expr.CRVal = EvaluateCRExpr(Val);
608 Op->IsPPC64 = IsPPC64;
612 static std::unique_ptr<PPCOperand>
613 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
614 auto Op = make_unique<PPCOperand>(TLSRegister);
615 Op->TLSReg.Sym = Sym;
618 Op->IsPPC64 = IsPPC64;
622 static std::unique_ptr<PPCOperand>
623 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
624 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
625 return CreateImm(CE->getValue(), S, E, IsPPC64);
627 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
628 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
629 return CreateTLSReg(SRE, S, E, IsPPC64);
631 return CreateExpr(Val, S, E, IsPPC64);
635 } // end anonymous namespace.
637 void PPCOperand::print(raw_ostream &OS) const {
640 OS << "'" << getToken() << "'";
646 getExpr()->print(OS);
649 getTLSReg()->print(OS);
654 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
655 const OperandVector &Operands) {
656 int Opcode = Inst.getOpcode();
660 TmpInst.setOpcode(PPC::LA);
661 TmpInst.addOperand(Inst.getOperand(0));
662 TmpInst.addOperand(Inst.getOperand(2));
663 TmpInst.addOperand(Inst.getOperand(1));
669 int64_t N = Inst.getOperand(2).getImm();
670 TmpInst.setOpcode(PPC::ADDI);
671 TmpInst.addOperand(Inst.getOperand(0));
672 TmpInst.addOperand(Inst.getOperand(1));
673 TmpInst.addOperand(MCOperand::CreateImm(-N));
679 int64_t N = Inst.getOperand(2).getImm();
680 TmpInst.setOpcode(PPC::ADDIS);
681 TmpInst.addOperand(Inst.getOperand(0));
682 TmpInst.addOperand(Inst.getOperand(1));
683 TmpInst.addOperand(MCOperand::CreateImm(-N));
689 int64_t N = Inst.getOperand(2).getImm();
690 TmpInst.setOpcode(PPC::ADDIC);
691 TmpInst.addOperand(Inst.getOperand(0));
692 TmpInst.addOperand(Inst.getOperand(1));
693 TmpInst.addOperand(MCOperand::CreateImm(-N));
699 int64_t N = Inst.getOperand(2).getImm();
700 TmpInst.setOpcode(PPC::ADDICo);
701 TmpInst.addOperand(Inst.getOperand(0));
702 TmpInst.addOperand(Inst.getOperand(1));
703 TmpInst.addOperand(MCOperand::CreateImm(-N));
710 int64_t N = Inst.getOperand(2).getImm();
711 int64_t B = Inst.getOperand(3).getImm();
712 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
713 TmpInst.addOperand(Inst.getOperand(0));
714 TmpInst.addOperand(Inst.getOperand(1));
715 TmpInst.addOperand(MCOperand::CreateImm(B));
716 TmpInst.addOperand(MCOperand::CreateImm(0));
717 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
724 int64_t N = Inst.getOperand(2).getImm();
725 int64_t B = Inst.getOperand(3).getImm();
726 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
727 TmpInst.addOperand(Inst.getOperand(0));
728 TmpInst.addOperand(Inst.getOperand(1));
729 TmpInst.addOperand(MCOperand::CreateImm(B + N));
730 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
731 TmpInst.addOperand(MCOperand::CreateImm(31));
738 int64_t N = Inst.getOperand(2).getImm();
739 int64_t B = Inst.getOperand(3).getImm();
740 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
741 TmpInst.addOperand(Inst.getOperand(0));
742 TmpInst.addOperand(Inst.getOperand(0));
743 TmpInst.addOperand(Inst.getOperand(1));
744 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
745 TmpInst.addOperand(MCOperand::CreateImm(B));
746 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
753 int64_t N = Inst.getOperand(2).getImm();
754 int64_t B = Inst.getOperand(3).getImm();
755 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
756 TmpInst.addOperand(Inst.getOperand(0));
757 TmpInst.addOperand(Inst.getOperand(0));
758 TmpInst.addOperand(Inst.getOperand(1));
759 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
760 TmpInst.addOperand(MCOperand::CreateImm(B));
761 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
768 int64_t N = Inst.getOperand(2).getImm();
769 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
770 TmpInst.addOperand(Inst.getOperand(0));
771 TmpInst.addOperand(Inst.getOperand(1));
772 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
773 TmpInst.addOperand(MCOperand::CreateImm(0));
774 TmpInst.addOperand(MCOperand::CreateImm(31));
781 int64_t N = Inst.getOperand(2).getImm();
782 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
783 TmpInst.addOperand(Inst.getOperand(0));
784 TmpInst.addOperand(Inst.getOperand(1));
785 TmpInst.addOperand(MCOperand::CreateImm(N));
786 TmpInst.addOperand(MCOperand::CreateImm(0));
787 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
794 int64_t N = Inst.getOperand(2).getImm();
795 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
796 TmpInst.addOperand(Inst.getOperand(0));
797 TmpInst.addOperand(Inst.getOperand(1));
798 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
799 TmpInst.addOperand(MCOperand::CreateImm(N));
800 TmpInst.addOperand(MCOperand::CreateImm(31));
807 int64_t N = Inst.getOperand(2).getImm();
808 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
809 TmpInst.addOperand(Inst.getOperand(0));
810 TmpInst.addOperand(Inst.getOperand(1));
811 TmpInst.addOperand(MCOperand::CreateImm(0));
812 TmpInst.addOperand(MCOperand::CreateImm(0));
813 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
818 case PPC::CLRLSLWIo: {
820 int64_t B = Inst.getOperand(2).getImm();
821 int64_t N = Inst.getOperand(3).getImm();
822 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
823 TmpInst.addOperand(Inst.getOperand(0));
824 TmpInst.addOperand(Inst.getOperand(1));
825 TmpInst.addOperand(MCOperand::CreateImm(N));
826 TmpInst.addOperand(MCOperand::CreateImm(B - N));
827 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
834 int64_t N = Inst.getOperand(2).getImm();
835 int64_t B = Inst.getOperand(3).getImm();
836 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
837 TmpInst.addOperand(Inst.getOperand(0));
838 TmpInst.addOperand(Inst.getOperand(1));
839 TmpInst.addOperand(MCOperand::CreateImm(B));
840 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
847 int64_t N = Inst.getOperand(2).getImm();
848 int64_t B = Inst.getOperand(3).getImm();
849 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
850 TmpInst.addOperand(Inst.getOperand(0));
851 TmpInst.addOperand(Inst.getOperand(1));
852 TmpInst.addOperand(MCOperand::CreateImm(B + N));
853 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
860 int64_t N = Inst.getOperand(2).getImm();
861 int64_t B = Inst.getOperand(3).getImm();
862 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
863 TmpInst.addOperand(Inst.getOperand(0));
864 TmpInst.addOperand(Inst.getOperand(0));
865 TmpInst.addOperand(Inst.getOperand(1));
866 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
867 TmpInst.addOperand(MCOperand::CreateImm(B));
874 int64_t N = Inst.getOperand(2).getImm();
875 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
876 TmpInst.addOperand(Inst.getOperand(0));
877 TmpInst.addOperand(Inst.getOperand(1));
878 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
879 TmpInst.addOperand(MCOperand::CreateImm(0));
886 int64_t N = Inst.getOperand(2).getImm();
887 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
888 TmpInst.addOperand(Inst.getOperand(0));
889 TmpInst.addOperand(Inst.getOperand(1));
890 TmpInst.addOperand(MCOperand::CreateImm(N));
891 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
898 int64_t N = Inst.getOperand(2).getImm();
899 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
900 TmpInst.addOperand(Inst.getOperand(0));
901 TmpInst.addOperand(Inst.getOperand(1));
902 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
903 TmpInst.addOperand(MCOperand::CreateImm(N));
910 int64_t N = Inst.getOperand(2).getImm();
911 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
912 TmpInst.addOperand(Inst.getOperand(0));
913 TmpInst.addOperand(Inst.getOperand(1));
914 TmpInst.addOperand(MCOperand::CreateImm(0));
915 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
920 case PPC::CLRLSLDIo: {
922 int64_t B = Inst.getOperand(2).getImm();
923 int64_t N = Inst.getOperand(3).getImm();
924 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
925 TmpInst.addOperand(Inst.getOperand(0));
926 TmpInst.addOperand(Inst.getOperand(1));
927 TmpInst.addOperand(MCOperand::CreateImm(N));
928 TmpInst.addOperand(MCOperand::CreateImm(B - N));
935 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
936 OperandVector &Operands,
937 MCStreamer &Out, unsigned &ErrorInfo,
938 bool MatchingInlineAsm) {
941 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
944 // Post-process instructions (typically extended mnemonics)
945 ProcessInstruction(Inst, Operands);
947 Out.EmitInstruction(Inst, STI);
949 case Match_MissingFeature:
950 return Error(IDLoc, "instruction use requires an option to be enabled");
951 case Match_MnemonicFail:
952 return Error(IDLoc, "unrecognized instruction mnemonic");
953 case Match_InvalidOperand: {
954 SMLoc ErrorLoc = IDLoc;
955 if (ErrorInfo != ~0U) {
956 if (ErrorInfo >= Operands.size())
957 return Error(IDLoc, "too few operands for instruction");
959 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
960 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
963 return Error(ErrorLoc, "invalid operand for instruction");
967 llvm_unreachable("Implement any new match types added!");
971 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
972 if (Tok.is(AsmToken::Identifier)) {
973 StringRef Name = Tok.getString();
975 if (Name.equals_lower("lr")) {
976 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
979 } else if (Name.equals_lower("ctr")) {
980 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
983 } else if (Name.equals_lower("vrsave")) {
987 } else if (Name.startswith_lower("r") &&
988 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
989 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
991 } else if (Name.startswith_lower("f") &&
992 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
993 RegNo = FRegs[IntVal];
995 } else if (Name.startswith_lower("v") &&
996 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
997 RegNo = VRegs[IntVal];
999 } else if (Name.startswith_lower("cr") &&
1000 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1001 RegNo = CRRegs[IntVal];
1010 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1011 const AsmToken &Tok = Parser.getTok();
1012 StartLoc = Tok.getLoc();
1013 EndLoc = Tok.getEndLoc();
1017 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1018 Parser.Lex(); // Eat identifier token.
1022 return Error(StartLoc, "invalid register name");
1025 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1026 /// the expression and check for VK_PPC_LO/HI/HA
1027 /// symbol variants. If all symbols with modifier use the same
1028 /// variant, return the corresponding PPCMCExpr::VariantKind,
1029 /// and a modified expression using the default symbol variant.
1030 /// Otherwise, return NULL.
1031 const MCExpr *PPCAsmParser::
1032 ExtractModifierFromExpr(const MCExpr *E,
1033 PPCMCExpr::VariantKind &Variant) {
1034 MCContext &Context = getParser().getContext();
1035 Variant = PPCMCExpr::VK_PPC_None;
1037 switch (E->getKind()) {
1038 case MCExpr::Target:
1039 case MCExpr::Constant:
1042 case MCExpr::SymbolRef: {
1043 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1045 switch (SRE->getKind()) {
1046 case MCSymbolRefExpr::VK_PPC_LO:
1047 Variant = PPCMCExpr::VK_PPC_LO;
1049 case MCSymbolRefExpr::VK_PPC_HI:
1050 Variant = PPCMCExpr::VK_PPC_HI;
1052 case MCSymbolRefExpr::VK_PPC_HA:
1053 Variant = PPCMCExpr::VK_PPC_HA;
1055 case MCSymbolRefExpr::VK_PPC_HIGHER:
1056 Variant = PPCMCExpr::VK_PPC_HIGHER;
1058 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1059 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1061 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1062 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1064 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1065 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1071 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1074 case MCExpr::Unary: {
1075 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1076 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1079 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1082 case MCExpr::Binary: {
1083 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1084 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1085 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1086 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1091 if (!LHS) LHS = BE->getLHS();
1092 if (!RHS) RHS = BE->getRHS();
1094 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1095 Variant = RHSVariant;
1096 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1097 Variant = LHSVariant;
1098 else if (LHSVariant == RHSVariant)
1099 Variant = LHSVariant;
1103 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1107 llvm_unreachable("Invalid expression kind!");
1110 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1111 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1112 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1113 /// FIXME: This is a hack.
1114 const MCExpr *PPCAsmParser::
1115 FixupVariantKind(const MCExpr *E) {
1116 MCContext &Context = getParser().getContext();
1118 switch (E->getKind()) {
1119 case MCExpr::Target:
1120 case MCExpr::Constant:
1123 case MCExpr::SymbolRef: {
1124 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1125 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1127 switch (SRE->getKind()) {
1128 case MCSymbolRefExpr::VK_TLSGD:
1129 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1131 case MCSymbolRefExpr::VK_TLSLD:
1132 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1137 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1140 case MCExpr::Unary: {
1141 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1142 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1143 if (Sub == UE->getSubExpr())
1145 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1148 case MCExpr::Binary: {
1149 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1150 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1151 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1152 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1154 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1158 llvm_unreachable("Invalid expression kind!");
1161 /// ParseExpression. This differs from the default "parseExpression" in that
1162 /// it handles modifiers.
1164 ParseExpression(const MCExpr *&EVal) {
1167 return ParseDarwinExpression(EVal);
1170 // Handle \code @l/@ha \endcode
1171 if (getParser().parseExpression(EVal))
1174 EVal = FixupVariantKind(EVal);
1176 PPCMCExpr::VariantKind Variant;
1177 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1179 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1184 /// ParseDarwinExpression. (MachO Platforms)
1185 /// This differs from the default "parseExpression" in that it handles detection
1186 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1187 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1188 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1189 /// for this to be done at a higher level.
1191 ParseDarwinExpression(const MCExpr *&EVal) {
1192 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1193 switch (getLexer().getKind()) {
1196 case AsmToken::Identifier:
1197 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1198 // something starting with any other char should be part of the
1199 // asm syntax. If handwritten asm includes an identifier like lo16,
1200 // then all bets are off - but no-one would do that, right?
1201 StringRef poss = Parser.getTok().getString();
1202 if (poss.equals_lower("lo16")) {
1203 Variant = PPCMCExpr::VK_PPC_LO;
1204 } else if (poss.equals_lower("hi16")) {
1205 Variant = PPCMCExpr::VK_PPC_HI;
1206 } else if (poss.equals_lower("ha16")) {
1207 Variant = PPCMCExpr::VK_PPC_HA;
1209 if (Variant != PPCMCExpr::VK_PPC_None) {
1210 Parser.Lex(); // Eat the xx16
1211 if (getLexer().isNot(AsmToken::LParen))
1212 return Error(Parser.getTok().getLoc(), "expected '('");
1213 Parser.Lex(); // Eat the '('
1218 if (getParser().parseExpression(EVal))
1221 if (Variant != PPCMCExpr::VK_PPC_None) {
1222 if (getLexer().isNot(AsmToken::RParen))
1223 return Error(Parser.getTok().getLoc(), "expected ')'");
1224 Parser.Lex(); // Eat the ')'
1225 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1231 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1233 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1234 SMLoc S = Parser.getTok().getLoc();
1235 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1238 // Attempt to parse the next token as an immediate
1239 switch (getLexer().getKind()) {
1240 // Special handling for register names. These are interpreted
1241 // as immediates corresponding to the register number.
1242 case AsmToken::Percent:
1243 Parser.Lex(); // Eat the '%'.
1246 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1247 Parser.Lex(); // Eat the identifier token.
1248 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1251 return Error(S, "invalid register name");
1253 case AsmToken::Identifier:
1254 // Note that non-register-name identifiers from the compiler will begin
1255 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1256 // identifiers like r31foo - so we fall through in the event that parsing
1257 // a register name fails.
1261 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1262 Parser.Lex(); // Eat the identifier token.
1263 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1267 // Fall-through to process non-register-name identifiers as expression.
1268 // All other expressions
1269 case AsmToken::LParen:
1270 case AsmToken::Plus:
1271 case AsmToken::Minus:
1272 case AsmToken::Integer:
1274 case AsmToken::Dollar:
1275 case AsmToken::Exclaim:
1276 case AsmToken::Tilde:
1277 if (!ParseExpression(EVal))
1281 return Error(S, "unknown operand");
1284 // Push the parsed operand into the list of operands
1285 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1287 // Check whether this is a TLS call expression
1288 bool TLSCall = false;
1289 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1290 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1292 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1293 const MCExpr *TLSSym;
1295 Parser.Lex(); // Eat the '('.
1296 S = Parser.getTok().getLoc();
1297 if (ParseExpression(TLSSym))
1298 return Error(S, "invalid TLS call expression");
1299 if (getLexer().isNot(AsmToken::RParen))
1300 return Error(Parser.getTok().getLoc(), "missing ')'");
1301 E = Parser.getTok().getLoc();
1302 Parser.Lex(); // Eat the ')'.
1304 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1307 // Otherwise, check for D-form memory operands
1308 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1309 Parser.Lex(); // Eat the '('.
1310 S = Parser.getTok().getLoc();
1313 switch (getLexer().getKind()) {
1314 case AsmToken::Percent:
1315 Parser.Lex(); // Eat the '%'.
1317 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1318 return Error(S, "invalid register name");
1319 Parser.Lex(); // Eat the identifier token.
1322 case AsmToken::Integer:
1324 if (getParser().parseAbsoluteExpression(IntVal) ||
1325 IntVal < 0 || IntVal > 31)
1326 return Error(S, "invalid register number");
1328 return Error(S, "unexpected integer value");
1332 case AsmToken::Identifier:
1335 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1336 Parser.Lex(); // Eat the identifier token.
1343 return Error(S, "invalid memory operand");
1346 if (getLexer().isNot(AsmToken::RParen))
1347 return Error(Parser.getTok().getLoc(), "missing ')'");
1348 E = Parser.getTok().getLoc();
1349 Parser.Lex(); // Eat the ')'.
1351 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1357 /// Parse an instruction mnemonic followed by its operands.
1358 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1359 SMLoc NameLoc, OperandVector &Operands) {
1360 // The first operand is the token for the instruction name.
1361 // If the next character is a '+' or '-', we need to add it to the
1362 // instruction name, to match what TableGen is doing.
1363 std::string NewOpcode;
1364 if (getLexer().is(AsmToken::Plus)) {
1370 if (getLexer().is(AsmToken::Minus)) {
1376 // If the instruction ends in a '.', we need to create a separate
1377 // token for it, to match what TableGen is doing.
1378 size_t Dot = Name.find('.');
1379 StringRef Mnemonic = Name.slice(0, Dot);
1380 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1382 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1384 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1385 if (Dot != StringRef::npos) {
1386 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1387 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1388 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1390 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1392 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1395 // If there are no more operands then finish
1396 if (getLexer().is(AsmToken::EndOfStatement))
1399 // Parse the first operand
1400 if (ParseOperand(Operands))
1403 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1404 getLexer().is(AsmToken::Comma)) {
1405 // Consume the comma token
1408 // Parse the next operand
1409 if (ParseOperand(Operands))
1416 /// ParseDirective parses the PPC specific directives
1417 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1418 StringRef IDVal = DirectiveID.getIdentifier();
1420 if (IDVal == ".word")
1421 return ParseDirectiveWord(2, DirectiveID.getLoc());
1422 if (IDVal == ".llong")
1423 return ParseDirectiveWord(8, DirectiveID.getLoc());
1425 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1426 if (IDVal == ".machine")
1427 return ParseDirectiveMachine(DirectiveID.getLoc());
1428 if (IDVal == ".abiversion")
1429 return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1430 if (IDVal == ".localentry")
1431 return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1433 if (IDVal == ".machine")
1434 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1439 /// ParseDirectiveWord
1440 /// ::= .word [ expression (, expression)* ]
1441 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1442 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1444 const MCExpr *Value;
1445 if (getParser().parseExpression(Value))
1448 getParser().getStreamer().EmitValue(Value, Size);
1450 if (getLexer().is(AsmToken::EndOfStatement))
1453 if (getLexer().isNot(AsmToken::Comma))
1454 return Error(L, "unexpected token in directive");
1463 /// ParseDirectiveTC
1464 /// ::= .tc [ symbol (, expression)* ]
1465 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1466 // Skip TC symbol, which is only used with XCOFF.
1467 while (getLexer().isNot(AsmToken::EndOfStatement)
1468 && getLexer().isNot(AsmToken::Comma))
1470 if (getLexer().isNot(AsmToken::Comma)) {
1471 Error(L, "unexpected token in directive");
1476 // Align to word size.
1477 getParser().getStreamer().EmitValueToAlignment(Size);
1479 // Emit expressions.
1480 return ParseDirectiveWord(Size, L);
1483 /// ParseDirectiveMachine (ELF platforms)
1484 /// ::= .machine [ cpu | "push" | "pop" ]
1485 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1486 if (getLexer().isNot(AsmToken::Identifier) &&
1487 getLexer().isNot(AsmToken::String)) {
1488 Error(L, "unexpected token in directive");
1492 StringRef CPU = Parser.getTok().getIdentifier();
1495 // FIXME: Right now, the parser always allows any available
1496 // instruction, so the .machine directive is not useful.
1497 // Implement ".machine any" (by doing nothing) for the benefit
1498 // of existing assembler code. Likewise, we can then implement
1499 // ".machine push" and ".machine pop" as no-op.
1500 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1501 Error(L, "unrecognized machine type");
1505 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1506 Error(L, "unexpected token in directive");
1509 PPCTargetStreamer &TStreamer =
1510 *static_cast<PPCTargetStreamer *>(
1511 getParser().getStreamer().getTargetStreamer());
1512 TStreamer.emitMachine(CPU);
1517 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1518 /// ::= .machine cpu-identifier
1519 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1520 if (getLexer().isNot(AsmToken::Identifier) &&
1521 getLexer().isNot(AsmToken::String)) {
1522 Error(L, "unexpected token in directive");
1526 StringRef CPU = Parser.getTok().getIdentifier();
1529 // FIXME: this is only the 'default' set of cpu variants.
1530 // However we don't act on this information at present, this is simply
1531 // allowing parsing to proceed with minimal sanity checking.
1532 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1533 Error(L, "unrecognized cpu type");
1537 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1538 Error(L, "wrong cpu type specified for 64bit");
1541 if (!isPPC64() && CPU == "ppc64") {
1542 Error(L, "wrong cpu type specified for 32bit");
1546 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1547 Error(L, "unexpected token in directive");
1554 /// ParseDirectiveAbiVersion
1555 /// ::= .abiversion constant-expression
1556 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1558 if (getParser().parseAbsoluteExpression(AbiVersion)){
1559 Error(L, "expected constant expression");
1562 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1563 Error(L, "unexpected token in directive");
1567 PPCTargetStreamer &TStreamer =
1568 *static_cast<PPCTargetStreamer *>(
1569 getParser().getStreamer().getTargetStreamer());
1570 TStreamer.emitAbiVersion(AbiVersion);
1575 /// ParseDirectiveLocalEntry
1576 /// ::= .localentry symbol, expression
1577 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1579 if (getParser().parseIdentifier(Name)) {
1580 Error(L, "expected identifier in directive");
1583 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1585 if (getLexer().isNot(AsmToken::Comma)) {
1586 Error(L, "unexpected token in directive");
1592 if (getParser().parseExpression(Expr)) {
1593 Error(L, "expected expression");
1597 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1598 Error(L, "unexpected token in directive");
1602 PPCTargetStreamer &TStreamer =
1603 *static_cast<PPCTargetStreamer *>(
1604 getParser().getStreamer().getTargetStreamer());
1605 TStreamer.emitLocalEntry(Sym, Expr);
1612 /// Force static initialization.
1613 extern "C" void LLVMInitializePowerPCAsmParser() {
1614 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1615 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1616 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1619 #define GET_REGISTER_MATCHER
1620 #define GET_MATCHER_IMPLEMENTATION
1621 #include "PPCGenAsmMatcher.inc"
1623 // Define this matcher function after the auto-generated include so we
1624 // have the match class enum definitions.
1625 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1627 // If the kind is a token for a literal immediate, check if our asm
1628 // operand matches. This is for InstAliases which have a fixed-value
1629 // immediate in the syntax.
1632 case MCK_0: ImmVal = 0; break;
1633 case MCK_1: ImmVal = 1; break;
1634 case MCK_2: ImmVal = 2; break;
1635 case MCK_3: ImmVal = 3; break;
1636 case MCK_4: ImmVal = 4; break;
1637 case MCK_5: ImmVal = 5; break;
1638 case MCK_6: ImmVal = 6; break;
1639 case MCK_7: ImmVal = 7; break;
1640 default: return Match_InvalidOperand;
1643 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1644 if (Op.isImm() && Op.getImm() == ImmVal)
1645 return Match_Success;
1647 return Match_InvalidOperand;
1651 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1652 MCSymbolRefExpr::VariantKind Variant,
1655 case MCSymbolRefExpr::VK_PPC_LO:
1656 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1657 case MCSymbolRefExpr::VK_PPC_HI:
1658 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1659 case MCSymbolRefExpr::VK_PPC_HA:
1660 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1661 case MCSymbolRefExpr::VK_PPC_HIGHER:
1662 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1663 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1664 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1665 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1666 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1667 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1668 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);