1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
33 static unsigned RRegs[32] = {
34 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
35 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
36 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
37 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
38 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
39 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
40 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
41 PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 static unsigned RRegsNoR0[32] = {
45 PPC::R1, PPC::R2, PPC::R3,
46 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
47 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
48 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
49 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
50 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
51 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
52 PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 static unsigned XRegs[32] = {
55 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
56 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
57 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
58 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
59 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
60 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
61 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
62 PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 static unsigned XRegsNoX0[32] = {
66 PPC::X1, PPC::X2, PPC::X3,
67 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
68 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
69 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
70 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
71 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
72 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73 PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 static unsigned FRegs[32] = {
76 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
77 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
78 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
79 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
80 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
81 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
82 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
83 PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 static unsigned VRegs[32] = {
86 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
87 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
88 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
89 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
90 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
91 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
92 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
93 PPC::V28, PPC::V29, PPC::V30, PPC::V31
95 static unsigned CRBITRegs[32] = {
96 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
97 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
98 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
99 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
100 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
101 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
102 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
103 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
105 static unsigned CRRegs[8] = {
106 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
107 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
110 // Evaluate an expression containing condition register
111 // or condition register field symbols. Returns positive
112 // value on success, or -1 on error.
114 EvaluateCRExpr(const MCExpr *E) {
115 switch (E->getKind()) {
119 case MCExpr::Constant: {
120 int64_t Res = cast<MCConstantExpr>(E)->getValue();
121 return Res < 0 ? -1 : Res;
124 case MCExpr::SymbolRef: {
125 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
126 StringRef Name = SRE->getSymbol().getName();
128 if (Name == "lt") return 0;
129 if (Name == "gt") return 1;
130 if (Name == "eq") return 2;
131 if (Name == "so") return 3;
132 if (Name == "un") return 3;
134 if (Name == "cr0") return 0;
135 if (Name == "cr1") return 1;
136 if (Name == "cr2") return 2;
137 if (Name == "cr3") return 3;
138 if (Name == "cr4") return 4;
139 if (Name == "cr5") return 5;
140 if (Name == "cr6") return 6;
141 if (Name == "cr7") return 7;
149 case MCExpr::Binary: {
150 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
151 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
152 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
155 if (LHSVal < 0 || RHSVal < 0)
158 switch (BE->getOpcode()) {
160 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
161 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
164 return Res < 0 ? -1 : Res;
168 llvm_unreachable("Invalid expression kind!");
173 class PPCAsmParser : public MCTargetAsmParser {
174 MCSubtargetInfo &STI;
178 MCAsmParser &getParser() const { return Parser; }
179 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
182 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
184 bool isPPC64() const { return IsPPC64; }
186 bool MatchRegisterName(const AsmToken &Tok,
187 unsigned &RegNo, int64_t &IntVal);
189 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
191 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
192 PPCMCExpr::VariantKind &Variant);
193 bool ParseExpression(const MCExpr *&EVal);
195 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
197 bool ParseDirectiveWord(unsigned Size, SMLoc L);
198 bool ParseDirectiveTC(unsigned Size, SMLoc L);
200 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
201 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
202 MCStreamer &Out, unsigned &ErrorInfo,
203 bool MatchingInlineAsm);
205 void ProcessInstruction(MCInst &Inst,
206 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
208 /// @name Auto-generated Match Functions
211 #define GET_ASSEMBLER_HEADER
212 #include "PPCGenAsmMatcher.inc"
218 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
219 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
220 // Check for 64-bit vs. 32-bit pointer mode.
221 Triple TheTriple(STI.getTargetTriple());
222 IsPPC64 = TheTriple.getArch() == Triple::ppc64;
223 // Initialize the set of available features.
224 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
227 virtual bool ParseInstruction(ParseInstructionInfo &Info,
228 StringRef Name, SMLoc NameLoc,
229 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
231 virtual bool ParseDirective(AsmToken DirectiveID);
233 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
236 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
238 struct PPCOperand : public MCParsedAsmOperand {
246 SMLoc StartLoc, EndLoc;
260 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
264 const MCSymbolRefExpr *Sym;
271 struct TLSRegOp TLSReg;
274 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
276 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
278 StartLoc = o.StartLoc;
297 /// getStartLoc - Get the location of the first token of this operand.
298 SMLoc getStartLoc() const { return StartLoc; }
300 /// getEndLoc - Get the location of the last token of this operand.
301 SMLoc getEndLoc() const { return EndLoc; }
303 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
304 bool isPPC64() const { return IsPPC64; }
306 int64_t getImm() const {
307 assert(Kind == Immediate && "Invalid access!");
311 const MCExpr *getExpr() const {
312 assert(Kind == Expression && "Invalid access!");
316 int64_t getExprCRVal() const {
317 assert(Kind == Expression && "Invalid access!");
321 const MCExpr *getTLSReg() const {
322 assert(Kind == TLSRegister && "Invalid access!");
326 unsigned getReg() const {
327 assert(isRegNumber() && "Invalid access!");
328 return (unsigned) Imm.Val;
331 unsigned getCCReg() const {
332 assert(isCCRegNumber() && "Invalid access!");
333 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
336 unsigned getCRBit() const {
337 assert(isCRBitNumber() && "Invalid access!");
338 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
341 unsigned getCRBitMask() const {
342 assert(isCRBitMask() && "Invalid access!");
343 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
346 bool isToken() const { return Kind == Token; }
347 bool isImm() const { return Kind == Immediate || Kind == Expression; }
348 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
349 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
350 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
351 bool isU16Imm() const { return Kind == Expression ||
352 (Kind == Immediate && isUInt<16>(getImm())); }
353 bool isS16Imm() const { return Kind == Expression ||
354 (Kind == Immediate && isInt<16>(getImm())); }
355 bool isS16ImmX4() const { return Kind == Expression ||
356 (Kind == Immediate && isInt<16>(getImm()) &&
357 (getImm() & 3) == 0); }
358 bool isS17Imm() const { return Kind == Expression ||
359 (Kind == Immediate && isInt<17>(getImm())); }
360 bool isTLSReg() const { return Kind == TLSRegister; }
361 bool isDirectBr() const { return Kind == Expression ||
362 (Kind == Immediate && isInt<26>(getImm()) &&
363 (getImm() & 3) == 0); }
364 bool isCondBr() const { return Kind == Expression ||
365 (Kind == Immediate && isInt<16>(getImm()) &&
366 (getImm() & 3) == 0); }
367 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
368 bool isCCRegNumber() const { return (Kind == Expression
369 && isUInt<3>(getExprCRVal())) ||
371 && isUInt<3>(getImm())); }
372 bool isCRBitNumber() const { return (Kind == Expression
373 && isUInt<5>(getExprCRVal())) ||
375 && isUInt<5>(getImm())); }
376 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
377 isPowerOf2_32(getImm()); }
378 bool isMem() const { return false; }
379 bool isReg() const { return false; }
381 void addRegOperands(MCInst &Inst, unsigned N) const {
382 llvm_unreachable("addRegOperands");
385 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
386 assert(N == 1 && "Invalid number of operands!");
387 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
390 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
391 assert(N == 1 && "Invalid number of operands!");
392 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
395 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
396 assert(N == 1 && "Invalid number of operands!");
397 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
400 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
401 assert(N == 1 && "Invalid number of operands!");
402 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
405 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
407 addRegG8RCOperands(Inst, N);
409 addRegGPRCOperands(Inst, N);
412 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
414 addRegG8RCNoX0Operands(Inst, N);
416 addRegGPRCNoR0Operands(Inst, N);
419 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
420 assert(N == 1 && "Invalid number of operands!");
421 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
424 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
425 assert(N == 1 && "Invalid number of operands!");
426 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
429 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
430 assert(N == 1 && "Invalid number of operands!");
431 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
434 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
435 assert(N == 1 && "Invalid number of operands!");
436 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
439 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
440 assert(N == 1 && "Invalid number of operands!");
441 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
444 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
445 assert(N == 1 && "Invalid number of operands!");
446 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
449 void addImmOperands(MCInst &Inst, unsigned N) const {
450 assert(N == 1 && "Invalid number of operands!");
451 if (Kind == Immediate)
452 Inst.addOperand(MCOperand::CreateImm(getImm()));
454 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
457 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
458 assert(N == 1 && "Invalid number of operands!");
459 if (Kind == Immediate)
460 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
462 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
465 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
466 assert(N == 1 && "Invalid number of operands!");
467 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
470 StringRef getToken() const {
471 assert(Kind == Token && "Invalid access!");
472 return StringRef(Tok.Data, Tok.Length);
475 virtual void print(raw_ostream &OS) const;
477 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
478 PPCOperand *Op = new PPCOperand(Token);
479 Op->Tok.Data = Str.data();
480 Op->Tok.Length = Str.size();
483 Op->IsPPC64 = IsPPC64;
487 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
488 PPCOperand *Op = new PPCOperand(Immediate);
492 Op->IsPPC64 = IsPPC64;
496 static PPCOperand *CreateExpr(const MCExpr *Val,
497 SMLoc S, SMLoc E, bool IsPPC64) {
498 PPCOperand *Op = new PPCOperand(Expression);
500 Op->Expr.CRVal = EvaluateCRExpr(Val);
503 Op->IsPPC64 = IsPPC64;
507 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
508 SMLoc S, SMLoc E, bool IsPPC64) {
509 PPCOperand *Op = new PPCOperand(TLSRegister);
510 Op->TLSReg.Sym = Sym;
513 Op->IsPPC64 = IsPPC64;
517 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
518 SMLoc S, SMLoc E, bool IsPPC64) {
519 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
520 return CreateImm(CE->getValue(), S, E, IsPPC64);
522 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
523 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
524 return CreateTLSReg(SRE, S, E, IsPPC64);
526 return CreateExpr(Val, S, E, IsPPC64);
530 } // end anonymous namespace.
532 void PPCOperand::print(raw_ostream &OS) const {
535 OS << "'" << getToken() << "'";
541 getExpr()->print(OS);
544 getTLSReg()->print(OS);
551 ProcessInstruction(MCInst &Inst,
552 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
553 int Opcode = Inst.getOpcode();
557 TmpInst.setOpcode(PPC::LA);
558 TmpInst.addOperand(Inst.getOperand(0));
559 TmpInst.addOperand(Inst.getOperand(2));
560 TmpInst.addOperand(Inst.getOperand(1));
566 int64_t N = Inst.getOperand(2).getImm();
567 TmpInst.setOpcode(PPC::ADDI);
568 TmpInst.addOperand(Inst.getOperand(0));
569 TmpInst.addOperand(Inst.getOperand(1));
570 TmpInst.addOperand(MCOperand::CreateImm(-N));
576 int64_t N = Inst.getOperand(2).getImm();
577 TmpInst.setOpcode(PPC::ADDIS);
578 TmpInst.addOperand(Inst.getOperand(0));
579 TmpInst.addOperand(Inst.getOperand(1));
580 TmpInst.addOperand(MCOperand::CreateImm(-N));
586 int64_t N = Inst.getOperand(2).getImm();
587 TmpInst.setOpcode(PPC::ADDIC);
588 TmpInst.addOperand(Inst.getOperand(0));
589 TmpInst.addOperand(Inst.getOperand(1));
590 TmpInst.addOperand(MCOperand::CreateImm(-N));
596 int64_t N = Inst.getOperand(2).getImm();
597 TmpInst.setOpcode(PPC::ADDICo);
598 TmpInst.addOperand(Inst.getOperand(0));
599 TmpInst.addOperand(Inst.getOperand(1));
600 TmpInst.addOperand(MCOperand::CreateImm(-N));
607 int64_t N = Inst.getOperand(2).getImm();
608 int64_t B = Inst.getOperand(3).getImm();
609 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
610 TmpInst.addOperand(Inst.getOperand(0));
611 TmpInst.addOperand(Inst.getOperand(1));
612 TmpInst.addOperand(MCOperand::CreateImm(B));
613 TmpInst.addOperand(MCOperand::CreateImm(0));
614 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
621 int64_t N = Inst.getOperand(2).getImm();
622 int64_t B = Inst.getOperand(3).getImm();
623 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
624 TmpInst.addOperand(Inst.getOperand(0));
625 TmpInst.addOperand(Inst.getOperand(1));
626 TmpInst.addOperand(MCOperand::CreateImm(B + N));
627 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
628 TmpInst.addOperand(MCOperand::CreateImm(31));
635 int64_t N = Inst.getOperand(2).getImm();
636 int64_t B = Inst.getOperand(3).getImm();
637 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
638 TmpInst.addOperand(Inst.getOperand(0));
639 TmpInst.addOperand(Inst.getOperand(0));
640 TmpInst.addOperand(Inst.getOperand(1));
641 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
642 TmpInst.addOperand(MCOperand::CreateImm(B));
643 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
650 int64_t N = Inst.getOperand(2).getImm();
651 int64_t B = Inst.getOperand(3).getImm();
652 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
653 TmpInst.addOperand(Inst.getOperand(0));
654 TmpInst.addOperand(Inst.getOperand(0));
655 TmpInst.addOperand(Inst.getOperand(1));
656 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
657 TmpInst.addOperand(MCOperand::CreateImm(B));
658 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
665 int64_t N = Inst.getOperand(2).getImm();
666 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
667 TmpInst.addOperand(Inst.getOperand(0));
668 TmpInst.addOperand(Inst.getOperand(1));
669 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
670 TmpInst.addOperand(MCOperand::CreateImm(0));
671 TmpInst.addOperand(MCOperand::CreateImm(31));
678 int64_t N = Inst.getOperand(2).getImm();
679 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
680 TmpInst.addOperand(Inst.getOperand(0));
681 TmpInst.addOperand(Inst.getOperand(1));
682 TmpInst.addOperand(MCOperand::CreateImm(N));
683 TmpInst.addOperand(MCOperand::CreateImm(0));
684 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
691 int64_t N = Inst.getOperand(2).getImm();
692 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
693 TmpInst.addOperand(Inst.getOperand(0));
694 TmpInst.addOperand(Inst.getOperand(1));
695 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
696 TmpInst.addOperand(MCOperand::CreateImm(N));
697 TmpInst.addOperand(MCOperand::CreateImm(31));
704 int64_t N = Inst.getOperand(2).getImm();
705 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
706 TmpInst.addOperand(Inst.getOperand(0));
707 TmpInst.addOperand(Inst.getOperand(1));
708 TmpInst.addOperand(MCOperand::CreateImm(0));
709 TmpInst.addOperand(MCOperand::CreateImm(0));
710 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
715 case PPC::CLRLSLWIo: {
717 int64_t B = Inst.getOperand(2).getImm();
718 int64_t N = Inst.getOperand(3).getImm();
719 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
720 TmpInst.addOperand(Inst.getOperand(0));
721 TmpInst.addOperand(Inst.getOperand(1));
722 TmpInst.addOperand(MCOperand::CreateImm(N));
723 TmpInst.addOperand(MCOperand::CreateImm(B - N));
724 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
731 int64_t N = Inst.getOperand(2).getImm();
732 int64_t B = Inst.getOperand(3).getImm();
733 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
734 TmpInst.addOperand(Inst.getOperand(0));
735 TmpInst.addOperand(Inst.getOperand(1));
736 TmpInst.addOperand(MCOperand::CreateImm(B));
737 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
744 int64_t N = Inst.getOperand(2).getImm();
745 int64_t B = Inst.getOperand(3).getImm();
746 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
747 TmpInst.addOperand(Inst.getOperand(0));
748 TmpInst.addOperand(Inst.getOperand(1));
749 TmpInst.addOperand(MCOperand::CreateImm(B + N));
750 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
757 int64_t N = Inst.getOperand(2).getImm();
758 int64_t B = Inst.getOperand(3).getImm();
759 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
760 TmpInst.addOperand(Inst.getOperand(0));
761 TmpInst.addOperand(Inst.getOperand(0));
762 TmpInst.addOperand(Inst.getOperand(1));
763 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
764 TmpInst.addOperand(MCOperand::CreateImm(B));
771 int64_t N = Inst.getOperand(2).getImm();
772 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
773 TmpInst.addOperand(Inst.getOperand(0));
774 TmpInst.addOperand(Inst.getOperand(1));
775 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
776 TmpInst.addOperand(MCOperand::CreateImm(0));
783 int64_t N = Inst.getOperand(2).getImm();
784 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
785 TmpInst.addOperand(Inst.getOperand(0));
786 TmpInst.addOperand(Inst.getOperand(1));
787 TmpInst.addOperand(MCOperand::CreateImm(N));
788 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
795 int64_t N = Inst.getOperand(2).getImm();
796 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
797 TmpInst.addOperand(Inst.getOperand(0));
798 TmpInst.addOperand(Inst.getOperand(1));
799 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
800 TmpInst.addOperand(MCOperand::CreateImm(N));
807 int64_t N = Inst.getOperand(2).getImm();
808 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
809 TmpInst.addOperand(Inst.getOperand(0));
810 TmpInst.addOperand(Inst.getOperand(1));
811 TmpInst.addOperand(MCOperand::CreateImm(0));
812 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
817 case PPC::CLRLSLDIo: {
819 int64_t B = Inst.getOperand(2).getImm();
820 int64_t N = Inst.getOperand(3).getImm();
821 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
822 TmpInst.addOperand(Inst.getOperand(0));
823 TmpInst.addOperand(Inst.getOperand(1));
824 TmpInst.addOperand(MCOperand::CreateImm(N));
825 TmpInst.addOperand(MCOperand::CreateImm(B - N));
833 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
834 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
835 MCStreamer &Out, unsigned &ErrorInfo,
836 bool MatchingInlineAsm) {
839 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
842 // Post-process instructions (typically extended mnemonics)
843 ProcessInstruction(Inst, Operands);
845 Out.EmitInstruction(Inst);
847 case Match_MissingFeature:
848 return Error(IDLoc, "instruction use requires an option to be enabled");
849 case Match_MnemonicFail:
850 return Error(IDLoc, "unrecognized instruction mnemonic");
851 case Match_InvalidOperand: {
852 SMLoc ErrorLoc = IDLoc;
853 if (ErrorInfo != ~0U) {
854 if (ErrorInfo >= Operands.size())
855 return Error(IDLoc, "too few operands for instruction");
857 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
858 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
861 return Error(ErrorLoc, "invalid operand for instruction");
865 llvm_unreachable("Implement any new match types added!");
869 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
870 if (Tok.is(AsmToken::Identifier)) {
871 StringRef Name = Tok.getString();
873 if (Name.equals_lower("lr")) {
874 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
877 } else if (Name.equals_lower("ctr")) {
878 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
881 } else if (Name.equals_lower("vrsave")) {
885 } else if (Name.substr(0, 1).equals_lower("r") &&
886 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
887 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
889 } else if (Name.substr(0, 1).equals_lower("f") &&
890 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
891 RegNo = FRegs[IntVal];
893 } else if (Name.substr(0, 1).equals_lower("v") &&
894 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
895 RegNo = VRegs[IntVal];
897 } else if (Name.substr(0, 2).equals_lower("cr") &&
898 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
899 RegNo = CRRegs[IntVal];
908 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
909 const AsmToken &Tok = Parser.getTok();
910 StartLoc = Tok.getLoc();
911 EndLoc = Tok.getEndLoc();
915 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
916 Parser.Lex(); // Eat identifier token.
920 return Error(StartLoc, "invalid register name");
923 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
924 /// the expression and check for VK_PPC_LO/HI/HA
925 /// symbol variants. If all symbols with modifier use the same
926 /// variant, return the corresponding PPCMCExpr::VariantKind,
927 /// and a modified expression using the default symbol variant.
928 /// Otherwise, return NULL.
929 const MCExpr *PPCAsmParser::
930 ExtractModifierFromExpr(const MCExpr *E,
931 PPCMCExpr::VariantKind &Variant) {
932 MCContext &Context = getParser().getContext();
933 Variant = PPCMCExpr::VK_PPC_None;
935 switch (E->getKind()) {
937 case MCExpr::Constant:
940 case MCExpr::SymbolRef: {
941 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
943 switch (SRE->getKind()) {
944 case MCSymbolRefExpr::VK_PPC_LO:
945 Variant = PPCMCExpr::VK_PPC_LO;
947 case MCSymbolRefExpr::VK_PPC_HI:
948 Variant = PPCMCExpr::VK_PPC_HI;
950 case MCSymbolRefExpr::VK_PPC_HA:
951 Variant = PPCMCExpr::VK_PPC_HA;
953 case MCSymbolRefExpr::VK_PPC_HIGHER:
954 Variant = PPCMCExpr::VK_PPC_HIGHER;
956 case MCSymbolRefExpr::VK_PPC_HIGHERA:
957 Variant = PPCMCExpr::VK_PPC_HIGHERA;
959 case MCSymbolRefExpr::VK_PPC_HIGHEST:
960 Variant = PPCMCExpr::VK_PPC_HIGHEST;
962 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
963 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
969 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
972 case MCExpr::Unary: {
973 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
974 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
977 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
980 case MCExpr::Binary: {
981 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
982 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
983 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
984 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
989 if (!LHS) LHS = BE->getLHS();
990 if (!RHS) RHS = BE->getRHS();
992 if (LHSVariant == PPCMCExpr::VK_PPC_None)
993 Variant = RHSVariant;
994 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
995 Variant = LHSVariant;
996 else if (LHSVariant == RHSVariant)
997 Variant = LHSVariant;
1001 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1005 llvm_unreachable("Invalid expression kind!");
1008 /// Parse an expression. This differs from the default "parseExpression"
1009 /// in that it handles complex \code @l/@ha \endcode modifiers.
1011 ParseExpression(const MCExpr *&EVal) {
1012 if (getParser().parseExpression(EVal))
1015 PPCMCExpr::VariantKind Variant;
1016 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1018 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1024 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1025 SMLoc S = Parser.getTok().getLoc();
1026 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1030 // Attempt to parse the next token as an immediate
1031 switch (getLexer().getKind()) {
1032 // Special handling for register names. These are interpreted
1033 // as immediates corresponding to the register number.
1034 case AsmToken::Percent:
1035 Parser.Lex(); // Eat the '%'.
1038 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1039 Parser.Lex(); // Eat the identifier token.
1040 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1041 Operands.push_back(Op);
1044 return Error(S, "invalid register name");
1046 // All other expressions
1047 case AsmToken::LParen:
1048 case AsmToken::Plus:
1049 case AsmToken::Minus:
1050 case AsmToken::Integer:
1051 case AsmToken::Identifier:
1053 case AsmToken::Dollar:
1054 if (!ParseExpression(EVal))
1058 return Error(S, "unknown operand");
1061 // Push the parsed operand into the list of operands
1062 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1063 Operands.push_back(Op);
1065 // Check whether this is a TLS call expression
1066 bool TLSCall = false;
1067 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1068 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1070 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1071 const MCExpr *TLSSym;
1073 Parser.Lex(); // Eat the '('.
1074 S = Parser.getTok().getLoc();
1075 if (ParseExpression(TLSSym))
1076 return Error(S, "invalid TLS call expression");
1077 if (getLexer().isNot(AsmToken::RParen))
1078 return Error(Parser.getTok().getLoc(), "missing ')'");
1079 E = Parser.getTok().getLoc();
1080 Parser.Lex(); // Eat the ')'.
1082 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1083 Operands.push_back(Op);
1086 // Otherwise, check for D-form memory operands
1087 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1088 Parser.Lex(); // Eat the '('.
1089 S = Parser.getTok().getLoc();
1092 switch (getLexer().getKind()) {
1093 case AsmToken::Percent:
1094 Parser.Lex(); // Eat the '%'.
1096 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1097 return Error(S, "invalid register name");
1098 Parser.Lex(); // Eat the identifier token.
1101 case AsmToken::Integer:
1102 if (getParser().parseAbsoluteExpression(IntVal) ||
1103 IntVal < 0 || IntVal > 31)
1104 return Error(S, "invalid register number");
1108 return Error(S, "invalid memory operand");
1111 if (getLexer().isNot(AsmToken::RParen))
1112 return Error(Parser.getTok().getLoc(), "missing ')'");
1113 E = Parser.getTok().getLoc();
1114 Parser.Lex(); // Eat the ')'.
1116 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1117 Operands.push_back(Op);
1123 /// Parse an instruction mnemonic followed by its operands.
1125 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1126 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1127 // The first operand is the token for the instruction name.
1128 // If the next character is a '+' or '-', we need to add it to the
1129 // instruction name, to match what TableGen is doing.
1130 if (getLexer().is(AsmToken::Plus)) {
1132 char *NewOpcode = new char[Name.size() + 1];
1133 memcpy(NewOpcode, Name.data(), Name.size());
1134 NewOpcode[Name.size()] = '+';
1135 Name = StringRef(NewOpcode, Name.size() + 1);
1137 if (getLexer().is(AsmToken::Minus)) {
1139 char *NewOpcode = new char[Name.size() + 1];
1140 memcpy(NewOpcode, Name.data(), Name.size());
1141 NewOpcode[Name.size()] = '-';
1142 Name = StringRef(NewOpcode, Name.size() + 1);
1144 // If the instruction ends in a '.', we need to create a separate
1145 // token for it, to match what TableGen is doing.
1146 size_t Dot = Name.find('.');
1147 StringRef Mnemonic = Name.slice(0, Dot);
1148 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1149 if (Dot != StringRef::npos) {
1150 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1151 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1152 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1155 // If there are no more operands then finish
1156 if (getLexer().is(AsmToken::EndOfStatement))
1159 // Parse the first operand
1160 if (ParseOperand(Operands))
1163 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1164 getLexer().is(AsmToken::Comma)) {
1165 // Consume the comma token
1168 // Parse the next operand
1169 if (ParseOperand(Operands))
1176 /// ParseDirective parses the PPC specific directives
1177 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1178 StringRef IDVal = DirectiveID.getIdentifier();
1179 if (IDVal == ".word")
1180 return ParseDirectiveWord(2, DirectiveID.getLoc());
1181 if (IDVal == ".llong")
1182 return ParseDirectiveWord(8, DirectiveID.getLoc());
1184 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1188 /// ParseDirectiveWord
1189 /// ::= .word [ expression (, expression)* ]
1190 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1191 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1193 const MCExpr *Value;
1194 if (getParser().parseExpression(Value))
1197 getParser().getStreamer().EmitValue(Value, Size);
1199 if (getLexer().is(AsmToken::EndOfStatement))
1202 if (getLexer().isNot(AsmToken::Comma))
1203 return Error(L, "unexpected token in directive");
1212 /// ParseDirectiveTC
1213 /// ::= .tc [ symbol (, expression)* ]
1214 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1215 // Skip TC symbol, which is only used with XCOFF.
1216 while (getLexer().isNot(AsmToken::EndOfStatement)
1217 && getLexer().isNot(AsmToken::Comma))
1219 if (getLexer().isNot(AsmToken::Comma))
1220 return Error(L, "unexpected token in directive");
1223 // Align to word size.
1224 getParser().getStreamer().EmitValueToAlignment(Size);
1226 // Emit expressions.
1227 return ParseDirectiveWord(Size, L);
1230 /// Force static initialization.
1231 extern "C" void LLVMInitializePowerPCAsmParser() {
1232 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1233 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1236 #define GET_REGISTER_MATCHER
1237 #define GET_MATCHER_IMPLEMENTATION
1238 #include "PPCGenAsmMatcher.inc"
1240 // Define this matcher function after the auto-generated include so we
1241 // have the match class enum definitions.
1242 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1244 // If the kind is a token for a literal immediate, check if our asm
1245 // operand matches. This is for InstAliases which have a fixed-value
1246 // immediate in the syntax.
1249 case MCK_0: ImmVal = 0; break;
1250 case MCK_1: ImmVal = 1; break;
1251 default: return Match_InvalidOperand;
1254 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1255 if (Op->isImm() && Op->getImm() == ImmVal)
1256 return Match_Success;
1258 return Match_InvalidOperand;