1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstPrinter.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetOpcodes.h"
26 #define DEBUG_TYPE "asm-printer"
28 // FIXME: Once the integrated assembler supports full register names, tie this
29 // to the verbose-asm setting.
31 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
32 cl::desc("Use full register names when printing assembly"));
34 #include "PPCGenAsmWriter.inc"
36 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
37 const char *RegName = getRegisterName(RegNo);
38 if (RegName[0] == 'q' /* QPX */) {
39 // The system toolchain on the BG/Q does not understand QPX register names
40 // in .cfi_* directives, so print the name of the floating-point
41 // subregister instead.
42 std::string RN(RegName);
53 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
55 // Check for slwi/srwi mnemonics.
56 if (MI->getOpcode() == PPC::RLWINM) {
57 unsigned char SH = MI->getOperand(2).getImm();
58 unsigned char MB = MI->getOperand(3).getImm();
59 unsigned char ME = MI->getOperand(4).getImm();
60 bool useSubstituteMnemonic = false;
61 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
62 O << "\tslwi "; useSubstituteMnemonic = true;
64 if (SH <= 31 && MB == (32-SH) && ME == 31) {
65 O << "\tsrwi "; useSubstituteMnemonic = true;
68 if (useSubstituteMnemonic) {
69 printOperand(MI, 0, O);
71 printOperand(MI, 1, O);
72 O << ", " << (unsigned int)SH;
74 printAnnotation(O, Annot);
79 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
80 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
82 printOperand(MI, 0, O);
84 printOperand(MI, 1, O);
85 printAnnotation(O, Annot);
89 if (MI->getOpcode() == PPC::RLDICR) {
90 unsigned char SH = MI->getOperand(2).getImm();
91 unsigned char ME = MI->getOperand(3).getImm();
92 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
95 printOperand(MI, 0, O);
97 printOperand(MI, 1, O);
98 O << ", " << (unsigned int)SH;
99 printAnnotation(O, Annot);
104 // For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
105 // used when converting a 32-bit float to a 64-bit float as part of
106 // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
107 // as otherwise we have problems with incorrect register classes
108 // in machine instruction verification. For now, just avoid trying
109 // to print it as such an instruction has no effect (a 32-bit float
110 // in a register is already in 64-bit form, just with lower
111 // precision). FIXME: Is there a better solution?
112 if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
115 printInstruction(MI, O);
116 printAnnotation(O, Annot);
120 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
122 const char *Modifier) {
123 unsigned Code = MI->getOperand(OpNo).getImm();
125 if (StringRef(Modifier) == "cc") {
126 switch ((PPC::Predicate)Code) {
127 case PPC::PRED_LT_MINUS:
128 case PPC::PRED_LT_PLUS:
132 case PPC::PRED_LE_MINUS:
133 case PPC::PRED_LE_PLUS:
137 case PPC::PRED_EQ_MINUS:
138 case PPC::PRED_EQ_PLUS:
142 case PPC::PRED_GE_MINUS:
143 case PPC::PRED_GE_PLUS:
147 case PPC::PRED_GT_MINUS:
148 case PPC::PRED_GT_PLUS:
152 case PPC::PRED_NE_MINUS:
153 case PPC::PRED_NE_PLUS:
157 case PPC::PRED_UN_MINUS:
158 case PPC::PRED_UN_PLUS:
162 case PPC::PRED_NU_MINUS:
163 case PPC::PRED_NU_PLUS:
167 case PPC::PRED_BIT_SET:
168 case PPC::PRED_BIT_UNSET:
169 llvm_unreachable("Invalid use of bit predicate code");
171 llvm_unreachable("Invalid predicate code");
174 if (StringRef(Modifier) == "pm") {
175 switch ((PPC::Predicate)Code) {
185 case PPC::PRED_LT_MINUS:
186 case PPC::PRED_LE_MINUS:
187 case PPC::PRED_EQ_MINUS:
188 case PPC::PRED_GE_MINUS:
189 case PPC::PRED_GT_MINUS:
190 case PPC::PRED_NE_MINUS:
191 case PPC::PRED_UN_MINUS:
192 case PPC::PRED_NU_MINUS:
195 case PPC::PRED_LT_PLUS:
196 case PPC::PRED_LE_PLUS:
197 case PPC::PRED_EQ_PLUS:
198 case PPC::PRED_GE_PLUS:
199 case PPC::PRED_GT_PLUS:
200 case PPC::PRED_NE_PLUS:
201 case PPC::PRED_UN_PLUS:
202 case PPC::PRED_NU_PLUS:
205 case PPC::PRED_BIT_SET:
206 case PPC::PRED_BIT_UNSET:
207 llvm_unreachable("Invalid use of bit predicate code");
209 llvm_unreachable("Invalid predicate code");
212 assert(StringRef(Modifier) == "reg" &&
213 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
214 printOperand(MI, OpNo+1, O);
217 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
219 unsigned int Value = MI->getOperand(OpNo).getImm();
220 assert(Value <= 3 && "Invalid u2imm argument!");
221 O << (unsigned int)Value;
224 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
226 unsigned int Value = MI->getOperand(OpNo).getImm();
227 assert(Value <= 15 && "Invalid u4imm argument!");
228 O << (unsigned int)Value;
231 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
233 int Value = MI->getOperand(OpNo).getImm();
234 Value = SignExtend32<5>(Value);
238 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
240 unsigned int Value = MI->getOperand(OpNo).getImm();
241 assert(Value <= 31 && "Invalid u5imm argument!");
242 O << (unsigned int)Value;
245 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
247 unsigned int Value = MI->getOperand(OpNo).getImm();
248 assert(Value <= 63 && "Invalid u6imm argument!");
249 O << (unsigned int)Value;
252 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
254 unsigned short Value = MI->getOperand(OpNo).getImm();
255 assert(Value <= 4095 && "Invalid u12imm argument!");
256 O << (unsigned short)Value;
259 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
261 if (MI->getOperand(OpNo).isImm())
262 O << (short)MI->getOperand(OpNo).getImm();
264 printOperand(MI, OpNo, O);
267 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
269 if (MI->getOperand(OpNo).isImm())
270 O << (unsigned short)MI->getOperand(OpNo).getImm();
272 printOperand(MI, OpNo, O);
275 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
277 if (!MI->getOperand(OpNo).isImm())
278 return printOperand(MI, OpNo, O);
280 // Branches can take an immediate operand. This is used by the branch
281 // selection pass to print .+8, an eight byte displacement from the PC.
283 printAbsBranchOperand(MI, OpNo, O);
286 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
288 if (!MI->getOperand(OpNo).isImm())
289 return printOperand(MI, OpNo, O);
291 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
295 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
297 unsigned CCReg = MI->getOperand(OpNo).getReg();
300 default: llvm_unreachable("Unknown CR register");
301 case PPC::CR0: RegNo = 0; break;
302 case PPC::CR1: RegNo = 1; break;
303 case PPC::CR2: RegNo = 2; break;
304 case PPC::CR3: RegNo = 3; break;
305 case PPC::CR4: RegNo = 4; break;
306 case PPC::CR5: RegNo = 5; break;
307 case PPC::CR6: RegNo = 6; break;
308 case PPC::CR7: RegNo = 7; break;
310 O << (0x80 >> RegNo);
313 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
315 printS16ImmOperand(MI, OpNo, O);
317 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
320 printOperand(MI, OpNo+1, O);
324 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
326 // When used as the base register, r0 reads constant zero rather than
327 // the value contained in the register. For this reason, the darwin
328 // assembler requires that we print r0 as 0 (no r) when used as the base.
329 if (MI->getOperand(OpNo).getReg() == PPC::R0)
332 printOperand(MI, OpNo, O);
334 printOperand(MI, OpNo+1, O);
337 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
339 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
340 // come at the _end_ of the expression.
341 const MCOperand &Op = MI->getOperand(OpNo);
342 const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
343 O << refExp.getSymbol().getName();
345 printOperand(MI, OpNo+1, O);
347 if (refExp.getKind() != MCSymbolRefExpr::VK_None)
348 O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
352 /// stripRegisterPrefix - This method strips the character prefix from a
353 /// register name so that only the number is left. Used by for linux asm.
354 static const char *stripRegisterPrefix(const char *RegName) {
358 switch (RegName[0]) {
363 if (RegName[1] == 's')
366 case 'c': if (RegName[1] == 'r') return RegName + 2;
372 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
374 const MCOperand &Op = MI->getOperand(OpNo);
376 const char *RegName = getRegisterName(Op.getReg());
377 // The linux and AIX assembler does not take register prefixes.
378 if (!isDarwinSyntax())
379 RegName = stripRegisterPrefix(RegName);
390 assert(Op.isExpr() && "unknown operand kind in printOperand");