1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstPrinter.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/MC/MCSymbol.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetOpcodes.h"
28 #define DEBUG_TYPE "asm-printer"
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34 cl::desc("Use full register names when printing assembly"));
36 #define PRINT_ALIAS_INSTR
37 #include "PPCGenAsmWriter.inc"
39 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
40 const char *RegName = getRegisterName(RegNo);
41 if (RegName[0] == 'q' /* QPX */) {
42 // The system toolchain on the BG/Q does not understand QPX register names
43 // in .cfi_* directives, so print the name of the floating-point
44 // subregister instead.
45 std::string RN(RegName);
56 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
57 StringRef Annot, const MCSubtargetInfo &STI) {
58 // Check for slwi/srwi mnemonics.
59 if (MI->getOpcode() == PPC::RLWINM) {
60 unsigned char SH = MI->getOperand(2).getImm();
61 unsigned char MB = MI->getOperand(3).getImm();
62 unsigned char ME = MI->getOperand(4).getImm();
63 bool useSubstituteMnemonic = false;
64 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
65 O << "\tslwi "; useSubstituteMnemonic = true;
67 if (SH <= 31 && MB == (32-SH) && ME == 31) {
68 O << "\tsrwi "; useSubstituteMnemonic = true;
71 if (useSubstituteMnemonic) {
72 printOperand(MI, 0, O);
74 printOperand(MI, 1, O);
75 O << ", " << (unsigned int)SH;
77 printAnnotation(O, Annot);
82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
83 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
85 printOperand(MI, 0, O);
87 printOperand(MI, 1, O);
88 printAnnotation(O, Annot);
92 if (MI->getOpcode() == PPC::RLDICR) {
93 unsigned char SH = MI->getOperand(2).getImm();
94 unsigned char ME = MI->getOperand(3).getImm();
95 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
98 printOperand(MI, 0, O);
100 printOperand(MI, 1, O);
101 O << ", " << (unsigned int)SH;
102 printAnnotation(O, Annot);
107 // dcbt[st] is printed manually here because:
108 // 1. The assembly syntax is different between embedded and server targets
109 // 2. We must print the short mnemonics for TH == 0 because the
110 // embedded/server syntax default will not be stable across assemblers
111 // The syntax for dcbt is:
112 // dcbt ra, rb, th [server]
113 // dcbt th, ra, rb [embedded]
114 // where th can be omitted when it is 0. dcbtst is the same.
115 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
116 unsigned char TH = MI->getOperand(0).getImm();
118 if (MI->getOpcode() == PPC::DCBTST)
124 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
125 if (IsBookE && TH != 0 && TH != 16)
126 O << (unsigned int) TH << ", ";
128 printOperand(MI, 1, O);
130 printOperand(MI, 2, O);
132 if (!IsBookE && TH != 0 && TH != 16)
133 O << ", " << (unsigned int) TH;
135 printAnnotation(O, Annot);
139 // For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
140 // used when converting a 32-bit float to a 64-bit float as part of
141 // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
142 // as otherwise we have problems with incorrect register classes
143 // in machine instruction verification. For now, just avoid trying
144 // to print it as such an instruction has no effect (a 32-bit float
145 // in a register is already in 64-bit form, just with lower
146 // precision). FIXME: Is there a better solution?
147 if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
150 if (!printAliasInstr(MI, O))
151 printInstruction(MI, O);
152 printAnnotation(O, Annot);
156 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
158 const char *Modifier) {
159 unsigned Code = MI->getOperand(OpNo).getImm();
161 if (StringRef(Modifier) == "cc") {
162 switch ((PPC::Predicate)Code) {
163 case PPC::PRED_LT_MINUS:
164 case PPC::PRED_LT_PLUS:
168 case PPC::PRED_LE_MINUS:
169 case PPC::PRED_LE_PLUS:
173 case PPC::PRED_EQ_MINUS:
174 case PPC::PRED_EQ_PLUS:
178 case PPC::PRED_GE_MINUS:
179 case PPC::PRED_GE_PLUS:
183 case PPC::PRED_GT_MINUS:
184 case PPC::PRED_GT_PLUS:
188 case PPC::PRED_NE_MINUS:
189 case PPC::PRED_NE_PLUS:
193 case PPC::PRED_UN_MINUS:
194 case PPC::PRED_UN_PLUS:
198 case PPC::PRED_NU_MINUS:
199 case PPC::PRED_NU_PLUS:
203 case PPC::PRED_BIT_SET:
204 case PPC::PRED_BIT_UNSET:
205 llvm_unreachable("Invalid use of bit predicate code");
207 llvm_unreachable("Invalid predicate code");
210 if (StringRef(Modifier) == "pm") {
211 switch ((PPC::Predicate)Code) {
221 case PPC::PRED_LT_MINUS:
222 case PPC::PRED_LE_MINUS:
223 case PPC::PRED_EQ_MINUS:
224 case PPC::PRED_GE_MINUS:
225 case PPC::PRED_GT_MINUS:
226 case PPC::PRED_NE_MINUS:
227 case PPC::PRED_UN_MINUS:
228 case PPC::PRED_NU_MINUS:
231 case PPC::PRED_LT_PLUS:
232 case PPC::PRED_LE_PLUS:
233 case PPC::PRED_EQ_PLUS:
234 case PPC::PRED_GE_PLUS:
235 case PPC::PRED_GT_PLUS:
236 case PPC::PRED_NE_PLUS:
237 case PPC::PRED_UN_PLUS:
238 case PPC::PRED_NU_PLUS:
241 case PPC::PRED_BIT_SET:
242 case PPC::PRED_BIT_UNSET:
243 llvm_unreachable("Invalid use of bit predicate code");
245 llvm_unreachable("Invalid predicate code");
248 assert(StringRef(Modifier) == "reg" &&
249 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
250 printOperand(MI, OpNo+1, O);
253 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
255 unsigned int Value = MI->getOperand(OpNo).getImm();
256 assert(Value <= 1 && "Invalid u1imm argument!");
257 O << (unsigned int)Value;
260 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
262 unsigned int Value = MI->getOperand(OpNo).getImm();
263 assert(Value <= 3 && "Invalid u2imm argument!");
264 O << (unsigned int)Value;
267 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
269 unsigned int Value = MI->getOperand(OpNo).getImm();
270 assert(Value <= 8 && "Invalid u3imm argument!");
271 O << (unsigned int)Value;
274 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
276 unsigned int Value = MI->getOperand(OpNo).getImm();
277 assert(Value <= 15 && "Invalid u4imm argument!");
278 O << (unsigned int)Value;
281 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
283 int Value = MI->getOperand(OpNo).getImm();
284 Value = SignExtend32<5>(Value);
288 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
290 unsigned int Value = MI->getOperand(OpNo).getImm();
291 assert(Value <= 31 && "Invalid u5imm argument!");
292 O << (unsigned int)Value;
295 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
297 unsigned int Value = MI->getOperand(OpNo).getImm();
298 assert(Value <= 63 && "Invalid u6imm argument!");
299 O << (unsigned int)Value;
302 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
304 unsigned short Value = MI->getOperand(OpNo).getImm();
305 assert(Value <= 1023 && "Invalid u10imm argument!");
306 O << (unsigned short)Value;
309 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
311 unsigned short Value = MI->getOperand(OpNo).getImm();
312 assert(Value <= 4095 && "Invalid u12imm argument!");
313 O << (unsigned short)Value;
316 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
318 if (MI->getOperand(OpNo).isImm())
319 O << (short)MI->getOperand(OpNo).getImm();
321 printOperand(MI, OpNo, O);
324 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
326 if (MI->getOperand(OpNo).isImm())
327 O << (unsigned short)MI->getOperand(OpNo).getImm();
329 printOperand(MI, OpNo, O);
332 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
334 if (!MI->getOperand(OpNo).isImm())
335 return printOperand(MI, OpNo, O);
337 // Branches can take an immediate operand. This is used by the branch
338 // selection pass to print .+8, an eight byte displacement from the PC.
340 printAbsBranchOperand(MI, OpNo, O);
343 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
345 if (!MI->getOperand(OpNo).isImm())
346 return printOperand(MI, OpNo, O);
348 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
352 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
354 unsigned CCReg = MI->getOperand(OpNo).getReg();
357 default: llvm_unreachable("Unknown CR register");
358 case PPC::CR0: RegNo = 0; break;
359 case PPC::CR1: RegNo = 1; break;
360 case PPC::CR2: RegNo = 2; break;
361 case PPC::CR3: RegNo = 3; break;
362 case PPC::CR4: RegNo = 4; break;
363 case PPC::CR5: RegNo = 5; break;
364 case PPC::CR6: RegNo = 6; break;
365 case PPC::CR7: RegNo = 7; break;
367 O << (0x80 >> RegNo);
370 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
372 printS16ImmOperand(MI, OpNo, O);
374 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
377 printOperand(MI, OpNo+1, O);
381 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
383 // When used as the base register, r0 reads constant zero rather than
384 // the value contained in the register. For this reason, the darwin
385 // assembler requires that we print r0 as 0 (no r) when used as the base.
386 if (MI->getOperand(OpNo).getReg() == PPC::R0)
389 printOperand(MI, OpNo, O);
391 printOperand(MI, OpNo+1, O);
394 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
396 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
397 // come at the _end_ of the expression.
398 const MCOperand &Op = MI->getOperand(OpNo);
399 const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
400 O << refExp.getSymbol().getName();
402 printOperand(MI, OpNo+1, O);
404 if (refExp.getKind() != MCSymbolRefExpr::VK_None)
405 O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
409 /// stripRegisterPrefix - This method strips the character prefix from a
410 /// register name so that only the number is left. Used by for linux asm.
411 static const char *stripRegisterPrefix(const char *RegName) {
415 switch (RegName[0]) {
420 if (RegName[1] == 's')
423 case 'c': if (RegName[1] == 'r') return RegName + 2;
429 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
431 const MCOperand &Op = MI->getOperand(OpNo);
433 const char *RegName = getRegisterName(Op.getReg());
434 // The linux and AIX assembler does not take register prefixes.
435 if (!isDarwinSyntax())
436 RegName = stripRegisterPrefix(RegName);
447 assert(Op.isExpr() && "unknown operand kind in printOperand");
448 Op.getExpr()->print(O, &MAI);