1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
31 class PPCMCCodeEmitter : public MCCodeEmitter {
32 PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 const MCSubtargetInfo &STI;
40 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
42 : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
45 ~PPCMCCodeEmitter() {}
47 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
48 SmallVectorImpl<MCFixup> &Fixups) const;
49 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
50 SmallVectorImpl<MCFixup> &Fixups) const;
51 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
52 SmallVectorImpl<MCFixup> &Fixups) const;
53 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
54 SmallVectorImpl<MCFixup> &Fixups) const;
55 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
56 SmallVectorImpl<MCFixup> &Fixups) const;
57 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
58 SmallVectorImpl<MCFixup> &Fixups) const;
59 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
60 SmallVectorImpl<MCFixup> &Fixups) const;
61 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
62 SmallVectorImpl<MCFixup> &Fixups) const;
63 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
64 SmallVectorImpl<MCFixup> &Fixups) const;
65 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 /// getMachineOpValue - Return binary encoding of operand. If the machine
69 /// operand requires relocation, record the relocation and return zero.
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 // getBinaryCodeForInstr - TableGen'erated function for getting the
74 // binary encoding for an instruction.
75 uint64_t getBinaryCodeForInstr(const MCInst &MI,
76 SmallVectorImpl<MCFixup> &Fixups) const;
77 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
78 SmallVectorImpl<MCFixup> &Fixups) const {
79 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
81 // BL8_NOP etc. all have a size of 8 because of the following 'nop'.
82 unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
83 unsigned Opcode = MI.getOpcode();
84 if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
85 Opcode == PPC::BL8_NOP_TLS)
88 // Output the constant in big endian byte order.
89 int ShiftValue = (Size * 8) - 8;
90 for (unsigned i = 0; i != Size; ++i) {
91 OS << (char)(Bits >> ShiftValue);
95 ++MCNumEmitted; // Keep track of the # of mi's emitted.
100 } // end anonymous namespace
102 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
103 const MCRegisterInfo &MRI,
104 const MCSubtargetInfo &STI,
106 return new PPCMCCodeEmitter(MCII, STI, Ctx);
109 unsigned PPCMCCodeEmitter::
110 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
111 SmallVectorImpl<MCFixup> &Fixups) const {
112 const MCOperand &MO = MI.getOperand(OpNo);
113 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
115 // Add a fixup for the branch target.
116 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
117 (MCFixupKind)PPC::fixup_ppc_br24));
121 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
122 SmallVectorImpl<MCFixup> &Fixups) const {
123 const MCOperand &MO = MI.getOperand(OpNo);
124 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
126 // Add a fixup for the branch target.
127 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
128 (MCFixupKind)PPC::fixup_ppc_brcond14));
132 unsigned PPCMCCodeEmitter::
133 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
134 SmallVectorImpl<MCFixup> &Fixups) const {
135 const MCOperand &MO = MI.getOperand(OpNo);
136 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
138 // Add a fixup for the branch target.
139 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
140 (MCFixupKind)PPC::fixup_ppc_br24abs));
144 unsigned PPCMCCodeEmitter::
145 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
146 SmallVectorImpl<MCFixup> &Fixups) const {
147 const MCOperand &MO = MI.getOperand(OpNo);
148 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
150 // Add a fixup for the branch target.
151 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
152 (MCFixupKind)PPC::fixup_ppc_brcond14abs));
156 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
157 SmallVectorImpl<MCFixup> &Fixups) const {
158 const MCOperand &MO = MI.getOperand(OpNo);
159 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
161 // Add a fixup for the immediate field.
162 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
163 (MCFixupKind)PPC::fixup_ppc_half16));
167 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
168 SmallVectorImpl<MCFixup> &Fixups) const {
169 // Encode (imm, reg) as a memri, which has the low 16-bits as the
170 // displacement and the next 5 bits as the register #.
171 assert(MI.getOperand(OpNo+1).isReg());
172 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
174 const MCOperand &MO = MI.getOperand(OpNo);
176 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
178 // Add a fixup for the displacement field.
179 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
180 (MCFixupKind)PPC::fixup_ppc_half16));
185 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
186 SmallVectorImpl<MCFixup> &Fixups) const {
187 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
188 // displacement and the next 5 bits as the register #.
189 assert(MI.getOperand(OpNo+1).isReg());
190 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
192 const MCOperand &MO = MI.getOperand(OpNo);
194 return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits;
196 // Add a fixup for the displacement field.
197 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
198 (MCFixupKind)PPC::fixup_ppc_half16ds));
203 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
204 SmallVectorImpl<MCFixup> &Fixups) const {
205 const MCOperand &MO = MI.getOperand(OpNo);
206 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
208 // Add a fixup for the TLS register, which simply provides a relocation
209 // hint to the linker that this statement is part of a relocation sequence.
210 // Return the thread-pointer register's encoding.
211 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
212 (MCFixupKind)PPC::fixup_ppc_tlsreg));
213 return CTX.getRegisterInfo()->getEncodingValue(PPC::X13);
216 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
217 SmallVectorImpl<MCFixup> &Fixups) const {
218 // For special TLS calls, we need two fixups; one for the branch target
219 // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
220 // and one for the TLSGD or TLSLD symbol, which is emitted here.
221 const MCOperand &MO = MI.getOperand(OpNo+1);
222 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
223 (MCFixupKind)PPC::fixup_ppc_nofixup));
224 return getDirectBrEncoding(MI, OpNo, Fixups);
227 unsigned PPCMCCodeEmitter::
228 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
229 SmallVectorImpl<MCFixup> &Fixups) const {
230 const MCOperand &MO = MI.getOperand(OpNo);
231 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
232 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
233 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
234 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
238 unsigned PPCMCCodeEmitter::
239 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
240 SmallVectorImpl<MCFixup> &Fixups) const {
242 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
243 // The GPR operand should come through here though.
244 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
245 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
246 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
247 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
251 "Relocation required in an instruction that we cannot encode!");
256 #include "PPCGenMCCodeEmitter.inc"