1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
31 class PPCMCCodeEmitter : public MCCodeEmitter {
32 PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 const MCSubtargetInfo &STI;
40 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
42 : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
45 ~PPCMCCodeEmitter() {}
47 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
48 SmallVectorImpl<MCFixup> &Fixups) const;
49 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
50 SmallVectorImpl<MCFixup> &Fixups) const;
51 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
52 SmallVectorImpl<MCFixup> &Fixups) const;
53 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
54 SmallVectorImpl<MCFixup> &Fixups) const;
55 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
56 SmallVectorImpl<MCFixup> &Fixups) const;
57 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
58 SmallVectorImpl<MCFixup> &Fixups) const;
59 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
60 SmallVectorImpl<MCFixup> &Fixups) const;
61 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
62 SmallVectorImpl<MCFixup> &Fixups) const;
64 /// getMachineOpValue - Return binary encoding of operand. If the machine
65 /// operand requires relocation, record the relocation and return zero.
66 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
67 SmallVectorImpl<MCFixup> &Fixups) const;
69 // getBinaryCodeForInstr - TableGen'erated function for getting the
70 // binary encoding for an instruction.
71 uint64_t getBinaryCodeForInstr(const MCInst &MI,
72 SmallVectorImpl<MCFixup> &Fixups) const;
73 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
74 SmallVectorImpl<MCFixup> &Fixups) const {
75 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
77 // BL8_NOP etc. all have a size of 8 because of the following 'nop'.
78 unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
79 unsigned Opcode = MI.getOpcode();
80 if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
81 Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD)
84 // Output the constant in big endian byte order.
85 int ShiftValue = (Size * 8) - 8;
86 for (unsigned i = 0; i != Size; ++i) {
87 OS << (char)(Bits >> ShiftValue);
91 ++MCNumEmitted; // Keep track of the # of mi's emitted.
96 } // end anonymous namespace
98 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
99 const MCRegisterInfo &MRI,
100 const MCSubtargetInfo &STI,
102 return new PPCMCCodeEmitter(MCII, STI, Ctx);
105 unsigned PPCMCCodeEmitter::
106 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
107 SmallVectorImpl<MCFixup> &Fixups) const {
108 const MCOperand &MO = MI.getOperand(OpNo);
109 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
111 // Add a fixup for the branch target.
112 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
113 (MCFixupKind)PPC::fixup_ppc_br24));
115 // For special TLS calls, add another fixup for the symbol. Apparently
116 // BL8_NOP, BL8_NOP_TLSGD, and BL8_NOP_TLSLD are sufficiently
117 // similar that TblGen will not generate a separate case for the latter
118 // two, so this is the only way to get the extra fixup generated.
119 unsigned Opcode = MI.getOpcode();
120 if (Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD) {
121 const MCOperand &MO2 = MI.getOperand(OpNo+1);
122 Fixups.push_back(MCFixup::Create(0, MO2.getExpr(),
123 (MCFixupKind)PPC::fixup_ppc_nofixup));
128 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
129 SmallVectorImpl<MCFixup> &Fixups) const {
130 const MCOperand &MO = MI.getOperand(OpNo);
131 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
133 // Add a fixup for the branch target.
134 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
135 (MCFixupKind)PPC::fixup_ppc_brcond14));
139 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
140 SmallVectorImpl<MCFixup> &Fixups) const {
141 const MCOperand &MO = MI.getOperand(OpNo);
142 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
144 // Add a fixup for the branch target.
145 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
146 (MCFixupKind)PPC::fixup_ppc_ha16));
150 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
151 SmallVectorImpl<MCFixup> &Fixups) const {
152 const MCOperand &MO = MI.getOperand(OpNo);
153 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
155 // Add a fixup for the branch target.
156 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
157 (MCFixupKind)PPC::fixup_ppc_lo16));
161 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
162 SmallVectorImpl<MCFixup> &Fixups) const {
163 // Encode (imm, reg) as a memri, which has the low 16-bits as the
164 // displacement and the next 5 bits as the register #.
165 assert(MI.getOperand(OpNo+1).isReg());
166 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
168 const MCOperand &MO = MI.getOperand(OpNo);
170 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
172 // Add a fixup for the displacement field.
173 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
174 (MCFixupKind)PPC::fixup_ppc_lo16));
179 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
180 SmallVectorImpl<MCFixup> &Fixups) const {
181 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
182 // displacement and the next 5 bits as the register #.
183 assert(MI.getOperand(OpNo+1).isReg());
184 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
186 const MCOperand &MO = MI.getOperand(OpNo);
188 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
190 // Add a fixup for the displacement field.
191 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
192 (MCFixupKind)PPC::fixup_ppc_lo16_ds));
197 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
198 SmallVectorImpl<MCFixup> &Fixups) const {
199 const MCOperand &MO = MI.getOperand(OpNo);
200 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
202 // Add a fixup for the TLS register, which simply provides a relocation
203 // hint to the linker that this statement is part of a relocation sequence.
204 // Return the thread-pointer register's encoding.
205 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
206 (MCFixupKind)PPC::fixup_ppc_tlsreg));
207 return CTX.getRegisterInfo().getEncodingValue(PPC::X13);
210 unsigned PPCMCCodeEmitter::
211 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
212 SmallVectorImpl<MCFixup> &Fixups) const {
213 const MCOperand &MO = MI.getOperand(OpNo);
214 assert((MI.getOpcode() == PPC::MTCRF ||
215 MI.getOpcode() == PPC::MFOCRF ||
216 MI.getOpcode() == PPC::MTCRF8) &&
217 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
218 return 0x80 >> CTX.getRegisterInfo().getEncodingValue(MO.getReg());
222 unsigned PPCMCCodeEmitter::
223 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
224 SmallVectorImpl<MCFixup> &Fixups) const {
226 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
227 // The GPR operand should come through here though.
228 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
229 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
230 return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
234 "Relocation required in an instruction that we cannot encode!");
239 #include "PPCGenMCCodeEmitter.inc"