1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
51 "Enable 64-bit instructions">;
52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53 "Enable 64-bit registers usage for ppc32 [beta]">;
54 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
55 "Use condition-register bits individually">;
56 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
57 "Enable Altivec instructions">;
58 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
59 "Enable the MFOCRF instruction">;
60 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
61 "Enable the fsqrt instruction">;
62 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
63 "Enable the fcpsgn instruction">;
64 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
65 "Enable the fre instruction">;
66 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
67 "Enable the fres instruction">;
68 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
69 "Enable the frsqrte instruction">;
70 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
71 "Enable the frsqrtes instruction">;
72 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
73 "Assume higher precision reciprocal estimates">;
74 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
75 "Enable the stfiwx instruction">;
76 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
77 "Enable the lfiwax instruction">;
78 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
79 "Enable the fri[mnpz] instructions">;
80 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
81 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
82 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
83 "Enable the isel instruction">;
84 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
85 "Enable the popcnt[dw] instructions">;
86 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
87 "Enable the ldbrx instruction">;
88 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
89 "Enable Book E instructions">;
90 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
91 "Enable QPX instructions">;
92 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
93 "Enable VSX instructions",
96 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
97 "Treat mftb as deprecated">;
98 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
99 "Treat vector data stream cache control instructions as deprecated">;
101 // Note: Future features to add when support is extended to more
102 // recent ISA levels:
104 // CMPB p6, p6x, p7 cmpb
105 // DFP p6, p6x, p7 decimal floating-point instructions
106 // POPCNTB p5 through p7 popcntb and related instructions
107 // VSX p7 vector-scalar instruction set
109 //===----------------------------------------------------------------------===//
110 // Classes used for relation maps.
111 //===----------------------------------------------------------------------===//
112 // RecFormRel - Filter class used to relate non-record-form instructions with
113 // their record-form variants.
116 //===----------------------------------------------------------------------===//
117 // Relation Map Definitions.
118 //===----------------------------------------------------------------------===//
120 def getRecordFormOpcode : InstrMapping {
121 let FilterClass = "RecFormRel";
122 // Instructions with the same BaseName and Interpretation64Bit values
124 let RowFields = ["BaseName", "Interpretation64Bit"];
125 // Instructions with the same RC value form a column.
126 let ColFields = ["RC"];
127 // The key column are the non-record-form instructions.
129 // Value columns RC=1
130 let ValueCols = [["1"]];
133 def getNonRecordFormOpcode : InstrMapping {
134 let FilterClass = "RecFormRel";
135 // Instructions with the same BaseName and Interpretation64Bit values
137 let RowFields = ["BaseName", "Interpretation64Bit"];
138 // Instructions with the same RC value form a column.
139 let ColFields = ["RC"];
140 // The key column are the record-form instructions.
142 // Value columns are RC=0
143 let ValueCols = [["0"]];
146 //===----------------------------------------------------------------------===//
147 // Register File Description
148 //===----------------------------------------------------------------------===//
150 include "PPCRegisterInfo.td"
151 include "PPCSchedule.td"
152 include "PPCInstrInfo.td"
154 //===----------------------------------------------------------------------===//
155 // PowerPC processors supported.
158 def : Processor<"generic", G3Itineraries, [Directive32]>;
159 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
160 FeatureFRES, FeatureFRSQRTE,
161 FeatureBookE, DeprecatedMFTB]>;
162 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
163 FeatureFRES, FeatureFRSQRTE,
164 FeatureBookE, DeprecatedMFTB]>;
165 def : Processor<"601", G3Itineraries, [Directive601]>;
166 def : Processor<"602", G3Itineraries, [Directive602]>;
167 def : Processor<"603", G3Itineraries, [Directive603,
168 FeatureFRES, FeatureFRSQRTE]>;
169 def : Processor<"603e", G3Itineraries, [Directive603,
170 FeatureFRES, FeatureFRSQRTE]>;
171 def : Processor<"603ev", G3Itineraries, [Directive603,
172 FeatureFRES, FeatureFRSQRTE]>;
173 def : Processor<"604", G3Itineraries, [Directive604,
174 FeatureFRES, FeatureFRSQRTE]>;
175 def : Processor<"604e", G3Itineraries, [Directive604,
176 FeatureFRES, FeatureFRSQRTE]>;
177 def : Processor<"620", G3Itineraries, [Directive620,
178 FeatureFRES, FeatureFRSQRTE]>;
179 def : Processor<"750", G4Itineraries, [Directive750,
180 FeatureFRES, FeatureFRSQRTE]>;
181 def : Processor<"g3", G3Itineraries, [Directive750,
182 FeatureFRES, FeatureFRSQRTE]>;
183 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
184 FeatureFRES, FeatureFRSQRTE]>;
185 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
186 FeatureFRES, FeatureFRSQRTE]>;
187 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
188 FeatureFRES, FeatureFRSQRTE]>;
189 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
190 FeatureFRES, FeatureFRSQRTE]>;
191 def : ProcessorModel<"970", G5Model,
192 [Directive970, FeatureAltivec,
193 FeatureMFOCRF, FeatureFSqrt,
194 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
195 Feature64Bit /*, Feature64BitRegs */]>;
196 def : ProcessorModel<"g5", G5Model,
197 [Directive970, FeatureAltivec,
198 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
199 FeatureFRES, FeatureFRSQRTE,
200 Feature64Bit /*, Feature64BitRegs */,
201 DeprecatedMFTB, DeprecatedDST]>;
202 def : ProcessorModel<"e500mc", PPCE500mcModel,
203 [DirectiveE500mc, FeatureMFOCRF,
204 FeatureSTFIWX, FeatureBookE, FeatureISEL,
206 def : ProcessorModel<"e5500", PPCE5500Model,
207 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
208 FeatureSTFIWX, FeatureBookE, FeatureISEL,
210 def : ProcessorModel<"a2", PPCA2Model,
211 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
212 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
213 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
214 FeatureSTFIWX, FeatureLFIWAX,
215 FeatureFPRND, FeatureFPCVT, FeatureISEL,
216 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
217 /*, Feature64BitRegs */, DeprecatedMFTB]>;
218 def : ProcessorModel<"a2q", PPCA2Model,
219 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
220 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
221 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
222 FeatureSTFIWX, FeatureLFIWAX,
223 FeatureFPRND, FeatureFPCVT, FeatureISEL,
224 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
225 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
226 def : ProcessorModel<"pwr3", G5Model,
227 [DirectivePwr3, FeatureAltivec,
228 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
229 FeatureSTFIWX, Feature64Bit]>;
230 def : ProcessorModel<"pwr4", G5Model,
231 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
232 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
233 FeatureSTFIWX, Feature64Bit]>;
234 def : ProcessorModel<"pwr5", G5Model,
235 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
236 FeatureFSqrt, FeatureFRE, FeatureFRES,
237 FeatureFRSQRTE, FeatureFRSQRTES,
238 FeatureSTFIWX, Feature64Bit,
239 DeprecatedMFTB, DeprecatedDST]>;
240 def : ProcessorModel<"pwr5x", G5Model,
241 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
242 FeatureFSqrt, FeatureFRE, FeatureFRES,
243 FeatureFRSQRTE, FeatureFRSQRTES,
244 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
245 DeprecatedMFTB, DeprecatedDST]>;
246 def : ProcessorModel<"pwr6", G5Model,
247 [DirectivePwr6, FeatureAltivec,
248 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
249 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
250 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
251 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
252 DeprecatedMFTB, DeprecatedDST]>;
253 def : ProcessorModel<"pwr6x", G5Model,
254 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
255 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
256 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
257 FeatureSTFIWX, FeatureLFIWAX,
258 FeatureFPRND, Feature64Bit,
259 DeprecatedMFTB, DeprecatedDST]>;
260 def : ProcessorModel<"pwr7", P7Model,
261 [DirectivePwr7, FeatureAltivec,
262 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
263 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
264 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
265 FeatureFPRND, FeatureFPCVT, FeatureISEL,
266 FeaturePOPCNTD, FeatureLDBRX,
267 Feature64Bit /*, Feature64BitRegs */,
268 DeprecatedMFTB, DeprecatedDST]>;
269 def : Processor<"ppc", G3Itineraries, [Directive32]>;
270 def : ProcessorModel<"ppc64", G5Model,
271 [Directive64, FeatureAltivec,
272 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
273 FeatureFRSQRTE, FeatureSTFIWX,
274 Feature64Bit /*, Feature64BitRegs */]>;
275 def : ProcessorModel<"ppc64le", G5Model,
276 [Directive64, FeatureAltivec,
277 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
278 FeatureFRSQRTE, FeatureSTFIWX,
279 Feature64Bit /*, Feature64BitRegs */]>;
281 //===----------------------------------------------------------------------===//
282 // Calling Conventions
283 //===----------------------------------------------------------------------===//
285 include "PPCCallingConv.td"
287 def PPCInstrInfo : InstrInfo {
288 let isLittleEndianEncoding = 1;
290 // FIXME: Unset this when no longer needed!
291 let decodePositionallyEncodedOperands = 1;
293 let noNamedPositionallyEncodedOperands = 1;
296 def PPCAsmParser : AsmParser {
297 let ShouldEmitMatchRegisterName = 0;
300 def PPCAsmParserVariant : AsmParserVariant {
303 // We do not use hard coded registers in asm strings. However, some
304 // InstAlias definitions use immediate literals. Set RegisterPrefix
305 // so that those are not misinterpreted as registers.
306 string RegisterPrefix = "%";
310 // Information about the instructions.
311 let InstructionSet = PPCInstrInfo;
313 let AssemblyParsers = [PPCAsmParser];
314 let AssemblyParserVariants = [PPCAsmParserVariant];