1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
60 "Enable SPE instructions">;
61 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
62 "Enable the MFOCRF instruction">;
63 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
64 "Enable the fsqrt instruction">;
65 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
66 "Enable the fcpsgn instruction">;
67 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
68 "Enable the fre instruction">;
69 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
70 "Enable the fres instruction">;
71 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
72 "Enable the frsqrte instruction">;
73 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
74 "Enable the frsqrtes instruction">;
75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
76 "Assume higher precision reciprocal estimates">;
77 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
78 "Enable the stfiwx instruction">;
79 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
80 "Enable the lfiwax instruction">;
81 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
82 "Enable the fri[mnpz] instructions">;
83 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
85 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
86 "Enable the isel instruction">;
87 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
88 "Enable the popcnt[dw] instructions">;
89 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
90 "Enable the ldbrx instruction">;
91 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
92 "Enable the cmpb instruction">;
93 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
94 "Enable icbt instruction">;
95 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
96 "Enable Book E instructions",
98 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
99 "Has only the msync instruction instead of sync",
101 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
102 "Enable E500/E500mc instructions">;
103 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
104 "Enable PPC 4xx instructions">;
105 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
106 "Enable PPC 6xx instructions">;
107 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
108 "Enable QPX instructions">;
109 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
110 "Enable VSX instructions",
112 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
113 "Enable POWER8 Altivec instructions",
115 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
116 "Enable POWER8 vector instructions",
117 [FeatureVSX, FeatureP8Altivec]>;
119 def FeatureInvariantFunctionDescriptors :
120 SubtargetFeature<"invariant-function-descriptors",
121 "HasInvariantFunctionDescriptors", "true",
122 "Assume function descriptors are invariant">;
124 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
125 "Treat mftb as deprecated">;
126 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
127 "Treat vector data stream cache control instructions as deprecated">;
129 // Note: Future features to add when support is extended to more
130 // recent ISA levels:
132 // DFP p6, p6x, p7 decimal floating-point instructions
133 // POPCNTB p5 through p7 popcntb and related instructions
135 //===----------------------------------------------------------------------===//
137 //===----------------------------------------------------------------------===//
139 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
140 "Use the ELFv1 ABI">;
142 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
143 "Use the ELFv2 ABI">;
145 //===----------------------------------------------------------------------===//
146 // Classes used for relation maps.
147 //===----------------------------------------------------------------------===//
148 // RecFormRel - Filter class used to relate non-record-form instructions with
149 // their record-form variants.
152 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
153 // FMA instruction forms with their corresponding factor-killing forms.
158 //===----------------------------------------------------------------------===//
159 // Relation Map Definitions.
160 //===----------------------------------------------------------------------===//
162 def getRecordFormOpcode : InstrMapping {
163 let FilterClass = "RecFormRel";
164 // Instructions with the same BaseName and Interpretation64Bit values
166 let RowFields = ["BaseName", "Interpretation64Bit"];
167 // Instructions with the same RC value form a column.
168 let ColFields = ["RC"];
169 // The key column are the non-record-form instructions.
171 // Value columns RC=1
172 let ValueCols = [["1"]];
175 def getNonRecordFormOpcode : InstrMapping {
176 let FilterClass = "RecFormRel";
177 // Instructions with the same BaseName and Interpretation64Bit values
179 let RowFields = ["BaseName", "Interpretation64Bit"];
180 // Instructions with the same RC value form a column.
181 let ColFields = ["RC"];
182 // The key column are the record-form instructions.
184 // Value columns are RC=0
185 let ValueCols = [["0"]];
188 def getAltVSXFMAOpcode : InstrMapping {
189 let FilterClass = "AltVSXFMARel";
190 // Instructions with the same BaseName and Interpretation64Bit values
192 let RowFields = ["BaseName"];
193 // Instructions with the same RC value form a column.
194 let ColFields = ["IsVSXFMAAlt"];
195 // The key column are the (default) addend-killing instructions.
197 // Value columns IsVSXFMAAlt=1
198 let ValueCols = [["1"]];
201 //===----------------------------------------------------------------------===//
202 // Register File Description
203 //===----------------------------------------------------------------------===//
205 include "PPCRegisterInfo.td"
206 include "PPCSchedule.td"
207 include "PPCInstrInfo.td"
209 //===----------------------------------------------------------------------===//
210 // PowerPC processors supported.
213 def : Processor<"generic", G3Itineraries, [Directive32]>;
214 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
215 FeatureFRES, FeatureFRSQRTE,
216 FeatureICBT, FeatureBookE,
217 FeatureMSYNC, DeprecatedMFTB]>;
218 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
219 FeatureFRES, FeatureFRSQRTE,
220 FeatureICBT, FeatureBookE,
221 FeatureMSYNC, DeprecatedMFTB]>;
222 def : Processor<"601", G3Itineraries, [Directive601]>;
223 def : Processor<"602", G3Itineraries, [Directive602]>;
224 def : Processor<"603", G3Itineraries, [Directive603,
225 FeatureFRES, FeatureFRSQRTE]>;
226 def : Processor<"603e", G3Itineraries, [Directive603,
227 FeatureFRES, FeatureFRSQRTE]>;
228 def : Processor<"603ev", G3Itineraries, [Directive603,
229 FeatureFRES, FeatureFRSQRTE]>;
230 def : Processor<"604", G3Itineraries, [Directive604,
231 FeatureFRES, FeatureFRSQRTE]>;
232 def : Processor<"604e", G3Itineraries, [Directive604,
233 FeatureFRES, FeatureFRSQRTE]>;
234 def : Processor<"620", G3Itineraries, [Directive620,
235 FeatureFRES, FeatureFRSQRTE]>;
236 def : Processor<"750", G4Itineraries, [Directive750,
237 FeatureFRES, FeatureFRSQRTE]>;
238 def : Processor<"g3", G3Itineraries, [Directive750,
239 FeatureFRES, FeatureFRSQRTE]>;
240 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
241 FeatureFRES, FeatureFRSQRTE]>;
242 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
243 FeatureFRES, FeatureFRSQRTE]>;
244 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
245 FeatureFRES, FeatureFRSQRTE]>;
246 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
247 FeatureFRES, FeatureFRSQRTE]>;
249 /* Since new processors generally contain a superset of features of those that
250 came before them, the idea is to make implementations of new processors
251 less error prone and easier to read.
253 list<SubtargetFeature> Power8FeatureList = ...
254 list<SubtargetFeature> FutureProcessorSpecificFeatureList =
255 [ features that Power8 does not support ]
256 list<SubtargetFeature> FutureProcessorFeatureList =
257 !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
259 Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
260 well as providing a single point of definition if the feature set will be
264 def ProcessorFeatures {
265 list<SubtargetFeature> Power8FeatureList =
266 [DirectivePwr8, FeatureAltivec, FeatureP8Altivec, FeatureVSX,
267 FeatureP8Vector, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt,
268 FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
269 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
270 FeatureFPRND, FeatureFPCVT, FeatureISEL,
271 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
272 Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
273 DeprecatedMFTB, DeprecatedDST];
276 def : ProcessorModel<"970", G5Model,
277 [Directive970, FeatureAltivec,
278 FeatureMFOCRF, FeatureFSqrt,
279 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
280 Feature64Bit /*, Feature64BitRegs */]>;
281 def : ProcessorModel<"g5", G5Model,
282 [Directive970, FeatureAltivec,
283 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
284 FeatureFRES, FeatureFRSQRTE,
285 Feature64Bit /*, Feature64BitRegs */,
286 DeprecatedMFTB, DeprecatedDST]>;
287 def : ProcessorModel<"e500mc", PPCE500mcModel,
288 [DirectiveE500mc, FeatureMFOCRF,
289 FeatureSTFIWX, FeatureICBT, FeatureBookE,
290 FeatureISEL, DeprecatedMFTB]>;
291 def : ProcessorModel<"e5500", PPCE5500Model,
292 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
293 FeatureSTFIWX, FeatureICBT, FeatureBookE,
294 FeatureISEL, DeprecatedMFTB]>;
295 def : ProcessorModel<"a2", PPCA2Model,
296 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
297 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
298 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
299 FeatureSTFIWX, FeatureLFIWAX,
300 FeatureFPRND, FeatureFPCVT, FeatureISEL,
301 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
302 /*, Feature64BitRegs */, DeprecatedMFTB]>;
303 def : ProcessorModel<"a2q", PPCA2Model,
304 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
305 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
306 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
307 FeatureSTFIWX, FeatureLFIWAX,
308 FeatureFPRND, FeatureFPCVT, FeatureISEL,
309 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
310 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
311 def : ProcessorModel<"pwr3", G5Model,
312 [DirectivePwr3, FeatureAltivec,
313 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
314 FeatureSTFIWX, Feature64Bit]>;
315 def : ProcessorModel<"pwr4", G5Model,
316 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
317 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
318 FeatureSTFIWX, Feature64Bit]>;
319 def : ProcessorModel<"pwr5", G5Model,
320 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
321 FeatureFSqrt, FeatureFRE, FeatureFRES,
322 FeatureFRSQRTE, FeatureFRSQRTES,
323 FeatureSTFIWX, Feature64Bit,
324 DeprecatedMFTB, DeprecatedDST]>;
325 def : ProcessorModel<"pwr5x", G5Model,
326 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
327 FeatureFSqrt, FeatureFRE, FeatureFRES,
328 FeatureFRSQRTE, FeatureFRSQRTES,
329 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
330 DeprecatedMFTB, DeprecatedDST]>;
331 def : ProcessorModel<"pwr6", G5Model,
332 [DirectivePwr6, FeatureAltivec,
333 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
334 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
335 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
336 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
337 DeprecatedMFTB, DeprecatedDST]>;
338 def : ProcessorModel<"pwr6x", G5Model,
339 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
340 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
341 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
342 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
343 FeatureFPRND, Feature64Bit,
344 DeprecatedMFTB, DeprecatedDST]>;
345 def : ProcessorModel<"pwr7", P7Model,
346 [DirectivePwr7, FeatureAltivec, FeatureVSX,
347 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
348 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
349 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
350 FeatureFPRND, FeatureFPCVT, FeatureISEL,
351 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
352 Feature64Bit /*, Feature64BitRegs */,
353 DeprecatedMFTB, DeprecatedDST]>;
354 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
355 def : Processor<"ppc", G3Itineraries, [Directive32]>;
356 def : ProcessorModel<"ppc64", G5Model,
357 [Directive64, FeatureAltivec,
358 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
359 FeatureFRSQRTE, FeatureSTFIWX,
360 Feature64Bit /*, Feature64BitRegs */]>;
361 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
363 //===----------------------------------------------------------------------===//
364 // Calling Conventions
365 //===----------------------------------------------------------------------===//
367 include "PPCCallingConv.td"
369 def PPCInstrInfo : InstrInfo {
370 let isLittleEndianEncoding = 1;
372 // FIXME: Unset this when no longer needed!
373 let decodePositionallyEncodedOperands = 1;
375 let noNamedPositionallyEncodedOperands = 1;
378 def PPCAsmParser : AsmParser {
379 let ShouldEmitMatchRegisterName = 0;
382 def PPCAsmParserVariant : AsmParserVariant {
385 // We do not use hard coded registers in asm strings. However, some
386 // InstAlias definitions use immediate literals. Set RegisterPrefix
387 // so that those are not misinterpreted as registers.
388 string RegisterPrefix = "%";
392 // Information about the instructions.
393 let InstructionSet = PPCInstrInfo;
395 let AssemblyParsers = [PPCAsmParser];
396 let AssemblyParserVariants = [PPCAsmParserVariant];