1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
60 "Enable SPE instructions">;
61 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
62 "Enable the MFOCRF instruction">;
63 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
64 "Enable the fsqrt instruction">;
65 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
66 "Enable the fcpsgn instruction">;
67 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
68 "Enable the fre instruction">;
69 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
70 "Enable the fres instruction">;
71 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
72 "Enable the frsqrte instruction">;
73 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
74 "Enable the frsqrtes instruction">;
75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
76 "Assume higher precision reciprocal estimates">;
77 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
78 "Enable the stfiwx instruction">;
79 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
80 "Enable the lfiwax instruction">;
81 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
82 "Enable the fri[mnpz] instructions">;
83 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
85 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
86 "Enable the isel instruction">;
87 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
88 "Enable the popcnt[dw] instructions">;
89 def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",
90 "Enable the bpermd instruction">;
91 def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true",
92 "Enable extended divide instructions">;
93 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
94 "Enable the ldbrx instruction">;
95 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
96 "Enable the cmpb instruction">;
97 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
98 "Enable icbt instruction">;
99 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
100 "Enable Book E instructions",
102 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
103 "Has only the msync instruction instead of sync",
105 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
106 "Enable E500/E500mc instructions">;
107 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
108 "Enable PPC 4xx instructions">;
109 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
110 "Enable PPC 6xx instructions">;
111 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
112 "Enable QPX instructions">;
113 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
114 "Enable VSX instructions",
116 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
117 "Enable POWER8 Altivec instructions",
119 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
120 "Enable POWER8 Crypto instructions",
122 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
123 "Enable POWER8 vector instructions",
124 [FeatureVSX, FeatureP8Altivec]>;
125 def FeatureDirectMove :
126 SubtargetFeature<"direct-move", "HasDirectMove", "true",
127 "Enable Power8 direct move instructions",
129 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
130 "HasPartwordAtomics", "true",
131 "Enable l[bh]arx and st[bh]cx.">;
132 def FeatureInvariantFunctionDescriptors :
133 SubtargetFeature<"invariant-function-descriptors",
134 "HasInvariantFunctionDescriptors", "true",
135 "Assume function descriptors are invariant">;
136 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
137 "Enable Hardware Transactional Memory instructions">;
138 def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true",
139 "Implement mftb using the mfspr instruction">;
141 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
142 "Treat vector data stream cache control instructions as deprecated">;
144 /* Since new processors generally contain a superset of features of those that
145 came before them, the idea is to make implementations of new processors
146 less error prone and easier to read.
148 list<SubtargetFeature> Power8FeatureList = ...
149 list<SubtargetFeature> FutureProcessorSpecificFeatureList =
150 [ features that Power8 does not support ]
151 list<SubtargetFeature> FutureProcessorFeatureList =
152 !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
154 Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
155 well as providing a single point of definition if the feature set will be
158 def ProcessorFeatures {
159 list<SubtargetFeature> Power7FeatureList =
160 [DirectivePwr7, FeatureAltivec, FeatureVSX,
161 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
162 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
163 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
164 FeatureFPRND, FeatureFPCVT, FeatureISEL,
165 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
166 Feature64Bit /*, Feature64BitRegs */,
167 FeatureBPERMD, FeatureExtDiv,
168 FeatureMFTB, DeprecatedDST];
169 list<SubtargetFeature> Power8SpecificFeatures =
170 [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
171 FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];
172 list<SubtargetFeature> Power8FeatureList =
173 !listconcat(Power7FeatureList, Power8SpecificFeatures);
176 // Note: Future features to add when support is extended to more
177 // recent ISA levels:
179 // DFP p6, p6x, p7 decimal floating-point instructions
180 // POPCNTB p5 through p7 popcntb and related instructions
182 //===----------------------------------------------------------------------===//
183 // Classes used for relation maps.
184 //===----------------------------------------------------------------------===//
185 // RecFormRel - Filter class used to relate non-record-form instructions with
186 // their record-form variants.
189 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
190 // FMA instruction forms with their corresponding factor-killing forms.
195 //===----------------------------------------------------------------------===//
196 // Relation Map Definitions.
197 //===----------------------------------------------------------------------===//
199 def getRecordFormOpcode : InstrMapping {
200 let FilterClass = "RecFormRel";
201 // Instructions with the same BaseName and Interpretation64Bit values
203 let RowFields = ["BaseName", "Interpretation64Bit"];
204 // Instructions with the same RC value form a column.
205 let ColFields = ["RC"];
206 // The key column are the non-record-form instructions.
208 // Value columns RC=1
209 let ValueCols = [["1"]];
212 def getNonRecordFormOpcode : InstrMapping {
213 let FilterClass = "RecFormRel";
214 // Instructions with the same BaseName and Interpretation64Bit values
216 let RowFields = ["BaseName", "Interpretation64Bit"];
217 // Instructions with the same RC value form a column.
218 let ColFields = ["RC"];
219 // The key column are the record-form instructions.
221 // Value columns are RC=0
222 let ValueCols = [["0"]];
225 def getAltVSXFMAOpcode : InstrMapping {
226 let FilterClass = "AltVSXFMARel";
227 // Instructions with the same BaseName and Interpretation64Bit values
229 let RowFields = ["BaseName"];
230 // Instructions with the same RC value form a column.
231 let ColFields = ["IsVSXFMAAlt"];
232 // The key column are the (default) addend-killing instructions.
234 // Value columns IsVSXFMAAlt=1
235 let ValueCols = [["1"]];
238 //===----------------------------------------------------------------------===//
239 // Register File Description
240 //===----------------------------------------------------------------------===//
242 include "PPCRegisterInfo.td"
243 include "PPCSchedule.td"
244 include "PPCInstrInfo.td"
246 //===----------------------------------------------------------------------===//
247 // PowerPC processors supported.
250 def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>;
251 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
252 FeatureFRES, FeatureFRSQRTE,
253 FeatureICBT, FeatureBookE,
254 FeatureMSYNC, FeatureMFTB]>;
255 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
256 FeatureFRES, FeatureFRSQRTE,
257 FeatureICBT, FeatureBookE,
258 FeatureMSYNC, FeatureMFTB]>;
259 def : Processor<"601", G3Itineraries, [Directive601]>;
260 def : Processor<"602", G3Itineraries, [Directive602,
262 def : Processor<"603", G3Itineraries, [Directive603,
263 FeatureFRES, FeatureFRSQRTE,
265 def : Processor<"603e", G3Itineraries, [Directive603,
266 FeatureFRES, FeatureFRSQRTE,
268 def : Processor<"603ev", G3Itineraries, [Directive603,
269 FeatureFRES, FeatureFRSQRTE,
271 def : Processor<"604", G3Itineraries, [Directive604,
272 FeatureFRES, FeatureFRSQRTE,
274 def : Processor<"604e", G3Itineraries, [Directive604,
275 FeatureFRES, FeatureFRSQRTE,
277 def : Processor<"620", G3Itineraries, [Directive620,
278 FeatureFRES, FeatureFRSQRTE,
280 def : Processor<"750", G4Itineraries, [Directive750,
281 FeatureFRES, FeatureFRSQRTE,
283 def : Processor<"g3", G3Itineraries, [Directive750,
284 FeatureFRES, FeatureFRSQRTE,
286 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
287 FeatureFRES, FeatureFRSQRTE,
289 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
290 FeatureFRES, FeatureFRSQRTE,
292 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
293 FeatureFRES, FeatureFRSQRTE,
295 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
296 FeatureFRES, FeatureFRSQRTE,
299 def : ProcessorModel<"970", G5Model,
300 [Directive970, FeatureAltivec,
301 FeatureMFOCRF, FeatureFSqrt,
302 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
303 Feature64Bit /*, Feature64BitRegs */,
305 def : ProcessorModel<"g5", G5Model,
306 [Directive970, FeatureAltivec,
307 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
308 FeatureFRES, FeatureFRSQRTE,
309 Feature64Bit /*, Feature64BitRegs */,
310 FeatureMFTB, DeprecatedDST]>;
311 def : ProcessorModel<"e500mc", PPCE500mcModel,
312 [DirectiveE500mc, FeatureMFOCRF,
313 FeatureSTFIWX, FeatureICBT, FeatureBookE,
314 FeatureISEL, FeatureMFTB]>;
315 def : ProcessorModel<"e5500", PPCE5500Model,
316 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
317 FeatureSTFIWX, FeatureICBT, FeatureBookE,
318 FeatureISEL, FeatureMFTB]>;
319 def : ProcessorModel<"a2", PPCA2Model,
320 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
321 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
322 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
323 FeatureSTFIWX, FeatureLFIWAX,
324 FeatureFPRND, FeatureFPCVT, FeatureISEL,
325 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
326 /*, Feature64BitRegs */, FeatureMFTB]>;
327 def : ProcessorModel<"a2q", PPCA2Model,
328 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
329 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
330 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
331 FeatureSTFIWX, FeatureLFIWAX,
332 FeatureFPRND, FeatureFPCVT, FeatureISEL,
333 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
334 /*, Feature64BitRegs */, FeatureQPX, FeatureMFTB]>;
335 def : ProcessorModel<"pwr3", G5Model,
336 [DirectivePwr3, FeatureAltivec,
337 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
338 FeatureSTFIWX, Feature64Bit]>;
339 def : ProcessorModel<"pwr4", G5Model,
340 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
341 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
342 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
343 def : ProcessorModel<"pwr5", G5Model,
344 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
345 FeatureFSqrt, FeatureFRE, FeatureFRES,
346 FeatureFRSQRTE, FeatureFRSQRTES,
347 FeatureSTFIWX, Feature64Bit,
348 FeatureMFTB, DeprecatedDST]>;
349 def : ProcessorModel<"pwr5x", G5Model,
350 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
351 FeatureFSqrt, FeatureFRE, FeatureFRES,
352 FeatureFRSQRTE, FeatureFRSQRTES,
353 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
354 FeatureMFTB, DeprecatedDST]>;
355 def : ProcessorModel<"pwr6", G5Model,
356 [DirectivePwr6, FeatureAltivec,
357 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
358 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
359 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
360 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
361 FeatureMFTB, DeprecatedDST]>;
362 def : ProcessorModel<"pwr6x", G5Model,
363 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
364 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
365 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
366 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
367 FeatureFPRND, Feature64Bit,
368 FeatureMFTB, DeprecatedDST]>;
369 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
370 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
371 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>;
372 def : ProcessorModel<"ppc64", G5Model,
373 [Directive64, FeatureAltivec,
374 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
375 FeatureFRSQRTE, FeatureSTFIWX,
376 Feature64Bit /*, Feature64BitRegs */,
378 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
380 //===----------------------------------------------------------------------===//
381 // Calling Conventions
382 //===----------------------------------------------------------------------===//
384 include "PPCCallingConv.td"
386 def PPCInstrInfo : InstrInfo {
387 let isLittleEndianEncoding = 1;
389 // FIXME: Unset this when no longer needed!
390 let decodePositionallyEncodedOperands = 1;
392 let noNamedPositionallyEncodedOperands = 1;
395 def PPCAsmParser : AsmParser {
396 let ShouldEmitMatchRegisterName = 0;
399 def PPCAsmParserVariant : AsmParserVariant {
402 // We do not use hard coded registers in asm strings. However, some
403 // InstAlias definitions use immediate literals. Set RegisterPrefix
404 // so that those are not misinterpreted as registers.
405 string RegisterPrefix = "%";
409 // Information about the instructions.
410 let InstructionSet = PPCInstrInfo;
412 let AssemblyParsers = [PPCAsmParser];
413 let AssemblyParserVariants = [PPCAsmParserVariant];