1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
60 "Enable SPE instructions">;
61 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
62 "Enable the MFOCRF instruction">;
63 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
64 "Enable the fsqrt instruction">;
65 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
66 "Enable the fcpsgn instruction">;
67 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
68 "Enable the fre instruction">;
69 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
70 "Enable the fres instruction">;
71 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
72 "Enable the frsqrte instruction">;
73 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
74 "Enable the frsqrtes instruction">;
75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
76 "Assume higher precision reciprocal estimates">;
77 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
78 "Enable the stfiwx instruction">;
79 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
80 "Enable the lfiwax instruction">;
81 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
82 "Enable the fri[mnpz] instructions">;
83 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
85 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
86 "Enable the isel instruction">;
87 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
88 "Enable the popcnt[dw] instructions">;
89 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
90 "Enable the ldbrx instruction">;
91 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
92 "Enable the cmpb instruction">;
93 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
94 "Enable icbt instruction">;
95 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
96 "Enable Book E instructions",
98 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
99 "Has only the msync instruction instead of sync",
101 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
102 "Enable E500/E500mc instructions">;
103 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
104 "Enable PPC 4xx instructions">;
105 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
106 "Enable PPC 6xx instructions">;
107 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
108 "Enable QPX instructions">;
109 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
110 "Enable VSX instructions",
112 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
113 "Enable POWER8 vector instructions",
114 [FeatureVSX, FeatureAltivec]>;
116 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
117 "Treat mftb as deprecated">;
118 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
119 "Treat vector data stream cache control instructions as deprecated">;
121 // Note: Future features to add when support is extended to more
122 // recent ISA levels:
124 // DFP p6, p6x, p7 decimal floating-point instructions
125 // POPCNTB p5 through p7 popcntb and related instructions
127 //===----------------------------------------------------------------------===//
129 //===----------------------------------------------------------------------===//
131 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
132 "Use the ELFv1 ABI">;
134 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
135 "Use the ELFv2 ABI">;
137 //===----------------------------------------------------------------------===//
138 // Classes used for relation maps.
139 //===----------------------------------------------------------------------===//
140 // RecFormRel - Filter class used to relate non-record-form instructions with
141 // their record-form variants.
144 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
145 // FMA instruction forms with their corresponding factor-killing forms.
150 //===----------------------------------------------------------------------===//
151 // Relation Map Definitions.
152 //===----------------------------------------------------------------------===//
154 def getRecordFormOpcode : InstrMapping {
155 let FilterClass = "RecFormRel";
156 // Instructions with the same BaseName and Interpretation64Bit values
158 let RowFields = ["BaseName", "Interpretation64Bit"];
159 // Instructions with the same RC value form a column.
160 let ColFields = ["RC"];
161 // The key column are the non-record-form instructions.
163 // Value columns RC=1
164 let ValueCols = [["1"]];
167 def getNonRecordFormOpcode : InstrMapping {
168 let FilterClass = "RecFormRel";
169 // Instructions with the same BaseName and Interpretation64Bit values
171 let RowFields = ["BaseName", "Interpretation64Bit"];
172 // Instructions with the same RC value form a column.
173 let ColFields = ["RC"];
174 // The key column are the record-form instructions.
176 // Value columns are RC=0
177 let ValueCols = [["0"]];
180 def getAltVSXFMAOpcode : InstrMapping {
181 let FilterClass = "AltVSXFMARel";
182 // Instructions with the same BaseName and Interpretation64Bit values
184 let RowFields = ["BaseName"];
185 // Instructions with the same RC value form a column.
186 let ColFields = ["IsVSXFMAAlt"];
187 // The key column are the (default) addend-killing instructions.
189 // Value columns IsVSXFMAAlt=1
190 let ValueCols = [["1"]];
193 //===----------------------------------------------------------------------===//
194 // Register File Description
195 //===----------------------------------------------------------------------===//
197 include "PPCRegisterInfo.td"
198 include "PPCSchedule.td"
199 include "PPCInstrInfo.td"
201 //===----------------------------------------------------------------------===//
202 // PowerPC processors supported.
205 def : Processor<"generic", G3Itineraries, [Directive32]>;
206 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
207 FeatureFRES, FeatureFRSQRTE,
208 FeatureICBT, FeatureBookE,
209 FeatureMSYNC, DeprecatedMFTB]>;
210 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
211 FeatureFRES, FeatureFRSQRTE,
212 FeatureICBT, FeatureBookE,
213 FeatureMSYNC, DeprecatedMFTB]>;
214 def : Processor<"601", G3Itineraries, [Directive601]>;
215 def : Processor<"602", G3Itineraries, [Directive602]>;
216 def : Processor<"603", G3Itineraries, [Directive603,
217 FeatureFRES, FeatureFRSQRTE]>;
218 def : Processor<"603e", G3Itineraries, [Directive603,
219 FeatureFRES, FeatureFRSQRTE]>;
220 def : Processor<"603ev", G3Itineraries, [Directive603,
221 FeatureFRES, FeatureFRSQRTE]>;
222 def : Processor<"604", G3Itineraries, [Directive604,
223 FeatureFRES, FeatureFRSQRTE]>;
224 def : Processor<"604e", G3Itineraries, [Directive604,
225 FeatureFRES, FeatureFRSQRTE]>;
226 def : Processor<"620", G3Itineraries, [Directive620,
227 FeatureFRES, FeatureFRSQRTE]>;
228 def : Processor<"750", G4Itineraries, [Directive750,
229 FeatureFRES, FeatureFRSQRTE]>;
230 def : Processor<"g3", G3Itineraries, [Directive750,
231 FeatureFRES, FeatureFRSQRTE]>;
232 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
233 FeatureFRES, FeatureFRSQRTE]>;
234 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
235 FeatureFRES, FeatureFRSQRTE]>;
236 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
237 FeatureFRES, FeatureFRSQRTE]>;
238 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
239 FeatureFRES, FeatureFRSQRTE]>;
240 def : ProcessorModel<"970", G5Model,
241 [Directive970, FeatureAltivec,
242 FeatureMFOCRF, FeatureFSqrt,
243 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
244 Feature64Bit /*, Feature64BitRegs */]>;
245 def : ProcessorModel<"g5", G5Model,
246 [Directive970, FeatureAltivec,
247 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
248 FeatureFRES, FeatureFRSQRTE,
249 Feature64Bit /*, Feature64BitRegs */,
250 DeprecatedMFTB, DeprecatedDST]>;
251 def : ProcessorModel<"e500mc", PPCE500mcModel,
252 [DirectiveE500mc, FeatureMFOCRF,
253 FeatureSTFIWX, FeatureICBT, FeatureBookE,
254 FeatureISEL, DeprecatedMFTB]>;
255 def : ProcessorModel<"e5500", PPCE5500Model,
256 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
257 FeatureSTFIWX, FeatureICBT, FeatureBookE,
258 FeatureISEL, DeprecatedMFTB]>;
259 def : ProcessorModel<"a2", PPCA2Model,
260 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
261 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
262 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
263 FeatureSTFIWX, FeatureLFIWAX,
264 FeatureFPRND, FeatureFPCVT, FeatureISEL,
265 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
266 /*, Feature64BitRegs */, DeprecatedMFTB]>;
267 def : ProcessorModel<"a2q", PPCA2Model,
268 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
269 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
270 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
271 FeatureSTFIWX, FeatureLFIWAX,
272 FeatureFPRND, FeatureFPCVT, FeatureISEL,
273 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
274 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
275 def : ProcessorModel<"pwr3", G5Model,
276 [DirectivePwr3, FeatureAltivec,
277 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
278 FeatureSTFIWX, Feature64Bit]>;
279 def : ProcessorModel<"pwr4", G5Model,
280 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
281 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
282 FeatureSTFIWX, Feature64Bit]>;
283 def : ProcessorModel<"pwr5", G5Model,
284 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
285 FeatureFSqrt, FeatureFRE, FeatureFRES,
286 FeatureFRSQRTE, FeatureFRSQRTES,
287 FeatureSTFIWX, Feature64Bit,
288 DeprecatedMFTB, DeprecatedDST]>;
289 def : ProcessorModel<"pwr5x", G5Model,
290 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
291 FeatureFSqrt, FeatureFRE, FeatureFRES,
292 FeatureFRSQRTE, FeatureFRSQRTES,
293 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
294 DeprecatedMFTB, DeprecatedDST]>;
295 def : ProcessorModel<"pwr6", G5Model,
296 [DirectivePwr6, FeatureAltivec,
297 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
298 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
299 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
300 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
301 DeprecatedMFTB, DeprecatedDST]>;
302 def : ProcessorModel<"pwr6x", G5Model,
303 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
304 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
305 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
306 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
307 FeatureFPRND, Feature64Bit,
308 DeprecatedMFTB, DeprecatedDST]>;
309 def : ProcessorModel<"pwr7", P7Model,
310 [DirectivePwr7, FeatureAltivec, FeatureVSX,
311 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
312 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
313 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
314 FeatureFPRND, FeatureFPCVT, FeatureISEL,
315 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
316 Feature64Bit /*, Feature64BitRegs */,
317 DeprecatedMFTB, DeprecatedDST]>;
318 def : ProcessorModel<"pwr8", P8Model,
319 [DirectivePwr8, FeatureAltivec, FeatureVSX, FeatureP8Vector,
320 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
321 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
322 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
323 FeatureFPRND, FeatureFPCVT, FeatureISEL,
324 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
325 Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
326 DeprecatedMFTB, DeprecatedDST]>;
327 def : Processor<"ppc", G3Itineraries, [Directive32]>;
328 def : ProcessorModel<"ppc64", G5Model,
329 [Directive64, FeatureAltivec,
330 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
331 FeatureFRSQRTE, FeatureSTFIWX,
332 Feature64Bit /*, Feature64BitRegs */]>;
333 def : ProcessorModel<"ppc64le", G5Model,
334 [Directive64, FeatureAltivec,
335 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
336 FeatureFRSQRTE, FeatureSTFIWX,
337 Feature64Bit /*, Feature64BitRegs */]>;
339 //===----------------------------------------------------------------------===//
340 // Calling Conventions
341 //===----------------------------------------------------------------------===//
343 include "PPCCallingConv.td"
345 def PPCInstrInfo : InstrInfo {
346 let isLittleEndianEncoding = 1;
348 // FIXME: Unset this when no longer needed!
349 let decodePositionallyEncodedOperands = 1;
351 let noNamedPositionallyEncodedOperands = 1;
354 def PPCAsmParser : AsmParser {
355 let ShouldEmitMatchRegisterName = 0;
358 def PPCAsmParserVariant : AsmParserVariant {
361 // We do not use hard coded registers in asm strings. However, some
362 // InstAlias definitions use immediate literals. Set RegisterPrefix
363 // so that those are not misinterpreted as registers.
364 string RegisterPrefix = "%";
368 // Information about the instructions.
369 let InstructionSet = PPCInstrInfo;
371 let AssemblyParsers = [PPCAsmParser];
372 let AssemblyParserVariants = [PPCAsmParserVariant];